diff mbox series

[v6,1/1] net/mlx5: support match ICMP identifier fields

Message ID 20201005093138.9409-1-lizh@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Raslan Darawsheh
Headers
Series [v6,1/1] net/mlx5: support match ICMP identifier fields |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-testing fail Testing issues
ci/Intel-compilation success Compilation OK
ci/iol-intel-Performance success Performance Testing PASS
ci/travis-robot success Travis build: passed
ci/iol-mellanox-Performance success Performance Testing PASS

Commit Message

Li Zhang Oct. 5, 2020, 9:31 a.m. UTC 
PRM expose fields "Icmp_header_data" in IPv4 ICMP.
Update ICMP mask parameter with ICMP identifier and sequence number fields.
ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set.
ICMP identifier spec with mask, Icmp_header_data high 16 bits are set.

Signed-off-by: Li Zhang <lizh@nvidia.com>
---
 doc/guides/nics/mlx5.rst               |  4 ++--
 doc/guides/rel_notes/release_20_11.rst |  2 +-
 drivers/net/mlx5/mlx5_flow.c           | 10 ++++++++--
 drivers/net/mlx5/mlx5_flow_dv.c        | 12 ++++++++++++
 4 files changed, 23 insertions(+), 5 deletions(-)

Comments

Ori Kam Oct. 5, 2020, 10:33 a.m. UTC | #1 
Hi Li,

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang
> Sent: Monday, October 5, 2020 12:32 PM
> To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>;
> Raslan Darawsheh <rasland@nvidia.com>
> Subject: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP identifier
> fields
> 
> PRM expose fields "Icmp_header_data" in IPv4 ICMP.
> Update ICMP mask parameter with ICMP identifier and sequence number
> fields.
> ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set.
> ICMP identifier spec with mask, Icmp_header_data high 16 bits are set.
> 
> Signed-off-by: Li Zhang <lizh@nvidia.com>
> ---

Acked-by: Ori Kam <orika@nvidia.com>
Thanks,
Ori
Li Zhang Oct. 6, 2020, 5:12 a.m. UTC | #2 
Hi Ori,

What's your comment?
I can not find it in last mail.
Can you help give more detail about it?

Thanks,
Regards,
Li Zhang

> -----Original Message-----
> From: Ori Kam <orika@nvidia.com>
> Sent: Monday, October 5, 2020 6:33 PM
> To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>;
> Raslan Darawsheh <rasland@nvidia.com>
> Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> identifier fields
> 
> Hi Li,
> 
> > -----Original Message-----
> > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang
> > Sent: Monday, October 5, 2020 12:32 PM
> > To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>; Slava
> > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon
> <thomas@monjalon.net>;
> > Raslan Darawsheh <rasland@nvidia.com>
> > Subject: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> > identifier fields
> >
> > PRM expose fields "Icmp_header_data" in IPv4 ICMP.
> > Update ICMP mask parameter with ICMP identifier and sequence number
> > fields.
> > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are
> set.
> > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set.
> >
> > Signed-off-by: Li Zhang <lizh@nvidia.com>
> > ---
> 
> Acked-by: Ori Kam <orika@nvidia.com>
> Thanks,
> Ori
Ori Kam Oct. 6, 2020, 12:07 p.m. UTC | #3 
Hi Li

There was no comment. I acked your patch.

Thanks,
Ori

> -----Original Message-----
> From: Li Zhang <lizh@nvidia.com>
> Sent: Tuesday, October 6, 2020 8:12 AM
> To: Ori Kam <orika@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>;
> Raslan Darawsheh <rasland@nvidia.com>
> Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> identifier fields
> 
> Hi Ori,
> 
> What's your comment?
> I can not find it in last mail.
> Can you help give more detail about it?
> 
> Thanks,
> Regards,
> Li Zhang
> 
> > -----Original Message-----
> > From: Ori Kam <orika@nvidia.com>
> > Sent: Monday, October 5, 2020 6:33 PM
> > To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava
> > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>;
> > Raslan Darawsheh <rasland@nvidia.com>
> > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> > identifier fields
> >
> > Hi Li,
> >
> > > -----Original Message-----
> > > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang
> > > Sent: Monday, October 5, 2020 12:32 PM
> > > To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>; Slava
> > > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon
> > <thomas@monjalon.net>;
> > > Raslan Darawsheh <rasland@nvidia.com>
> > > Subject: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> > > identifier fields
> > >
> > > PRM expose fields "Icmp_header_data" in IPv4 ICMP.
> > > Update ICMP mask parameter with ICMP identifier and sequence number
> > > fields.
> > > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are
> > set.
> > > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set.
> > >
> > > Signed-off-by: Li Zhang <lizh@nvidia.com>
> > > ---
> >
> > Acked-by: Ori Kam <orika@nvidia.com>
> > Thanks,
> > Ori
Li Zhang Oct. 7, 2020, 6:08 a.m. UTC | #4 
Hi Ori,

My latest patch V6 as below:
Please help review it.
https://patchwork.dpdk.org/patch/79613/

Thanks,
Regards,
Li Zhang
> -----Original Message-----
> From: Ori Kam <orika@nvidia.com>
> Sent: Tuesday, October 6, 2020 8:07 PM
> To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>;
> Raslan Darawsheh <rasland@nvidia.com>
> Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> identifier fields
> 
> Hi Li
> 
> There was no comment. I acked your patch.
> 
> Thanks,
> Ori
> 
> > -----Original Message-----
> > From: Li Zhang <lizh@nvidia.com>
> > Sent: Tuesday, October 6, 2020 8:12 AM
> > To: Ori Kam <orika@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava
> > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>
> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon
> <thomas@monjalon.net>;
> > Raslan Darawsheh <rasland@nvidia.com>
> > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> > identifier fields
> >
> > Hi Ori,
> >
> > What's your comment?
> > I can not find it in last mail.
> > Can you help give more detail about it?
> >
> > Thanks,
> > Regards,
> > Li Zhang
> >
> > > -----Original Message-----
> > > From: Ori Kam <orika@nvidia.com>
> > > Sent: Monday, October 5, 2020 6:33 PM
> > > To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>;
> > > Slava Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad
> > > <matan@nvidia.com>
> > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon
> <thomas@monjalon.net>;
> > > Raslan Darawsheh <rasland@nvidia.com>
> > > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> > > identifier fields
> > >
> > > Hi Li,
> > >
> > > > -----Original Message-----
> > > > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang
> > > > Sent: Monday, October 5, 2020 12:32 PM
> > > > To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>;
> > > > Slava Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad
> > > > <matan@nvidia.com>
> > > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon
> > > <thomas@monjalon.net>;
> > > > Raslan Darawsheh <rasland@nvidia.com>
> > > > Subject: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP
> > > > identifier fields
> > > >
> > > > PRM expose fields "Icmp_header_data" in IPv4 ICMP.
> > > > Update ICMP mask parameter with ICMP identifier and sequence
> > > > number fields.
> > > > ICMP sequence number spec with mask, Icmp_header_data low 16 bits
> > > > are
> > > set.
> > > > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set.
> > > >
> > > > Signed-off-by: Li Zhang <lizh@nvidia.com>
> > > > ---
> > >
> > > Acked-by: Ori Kam <orika@nvidia.com> Thanks, Ori
diff mbox series

Patch

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 211c0c5a6c..576dbe5efd 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -288,7 +288,7 @@  Limitations
   - The input buffer, providing the removal size, is not validated.
   - The buffer size must match the length of the headers to be removed.
 
-- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all
+- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all
   mutually exclusive features which cannot be supported together
   (see :ref:`mlx5_firmware_config`).
 
@@ -1009,7 +1009,7 @@  Below are some firmware configurations listed.
 
     FLEX_PARSER_PROFILE_ENABLE=1
 
-- enable ICMP/ICMP6 code/type fields matching::
+- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching::
 
     FLEX_PARSER_PROFILE_ENABLE=2
 
diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index c6642f5f94..791f133d8f 100644
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -73,7 +73,7 @@  New Features
   * Added flag action.
   * Added raw encap/decap actions.
   * Added VXLAN encap/decap actions.
-  * Added ICMP and ICMP6 matching items.
+  * Added ICMP(code/type/identifier/sequence number) and ICMP6(code/type) matching items.
   * Added option to set port mask for insertion/deletion:
     ``--portmask=N``
     where N represents the hexadecimal bitmask of ports used.
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 416505f1c8..3cabfd4627 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1303,6 +1303,12 @@  mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
 			     struct rte_flow_error *error)
 {
 	const struct rte_flow_item_icmp *mask = item->mask;
+	const struct rte_flow_item_icmp nic_mask = {
+		.hdr.icmp_type = 0xff,
+		.hdr.icmp_code = 0xff,
+		.hdr.icmp_ident = RTE_BE16(0xffff),
+		.hdr.icmp_seq_nb = RTE_BE16(0xffff),
+	};
 	const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
 	const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
 				      MLX5_FLOW_LAYER_OUTER_L3_IPV4;
@@ -1325,10 +1331,10 @@  mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
 					  RTE_FLOW_ERROR_TYPE_ITEM, item,
 					  "multiple L4 layers not supported");
 	if (!mask)
-		mask = &rte_flow_item_icmp_mask;
+		mask = &nic_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_icmp_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_icmp), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 3819cdb266..73361eef12 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7378,6 +7378,8 @@  flow_dv_translate_item_icmp(void *matcher, void *key,
 {
 	const struct rte_flow_item_icmp *icmp_m = item->mask;
 	const struct rte_flow_item_icmp *icmp_v = item->spec;
+	uint32_t icmp_header_data_m = 0;
+	uint32_t icmp_header_data_v = 0;
 	void *headers_m;
 	void *headers_v;
 	void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -7412,6 +7414,16 @@  flow_dv_translate_item_icmp(void *matcher, void *key,
 		 icmp_m->hdr.icmp_code);
 	MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
 		 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
+	icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
+	icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
+	if (icmp_header_data_m) {
+		icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
+		icmp_header_data_v |= rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
+		MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
+			 icmp_header_data_m);
+		MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
+			 icmp_header_data_v & icmp_header_data_m);
+	}
 }
 
 /**