From patchwork Thu Apr 29 09:55:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 92398 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4EE42A0547; Thu, 29 Apr 2021 11:56:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4AFE24131A; Thu, 29 Apr 2021 11:56:33 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2040.outbound.protection.outlook.com [40.107.94.40]) by mails.dpdk.org (Postfix) with ESMTP id AD4C1412FC for ; Thu, 29 Apr 2021 11:56:28 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aFdsrWbXknlpAspWBbYsQyfdgvNbRbAB4mLljIq78lGHile3RfaInvVTKuhikEdNyz9QRVd6ogTy6JBsgXOxKRkMbIcHXN+on9eSVwd4S6EOOb9d7CQZnOn6FiJ9xb2FDiznVF+ML58pRarfHVuC2DUFHzZgusANq2iWhK3YkYadN/8s1/n6kszpeKFqjKgla2w1tQ/dasMfJkFFvlBsm4kW7pz2uuRFQLTxfWPzx7UduSt3XjnnavoRhA1kx0oMd+fXm9NkUHlbhvL1TmUqiB3FR4HZNIPKTueHc5G1kGF6GVUxWHvEgJFAmzWpY9uE6Rx0AZ/e99XUrNVGJD2L7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jKY4GARGf7cFe6kYo7UEXRjHObM5WbMIdmYN953bGwU=; b=YegNI1/o5XFxyvTOS1zTIHqea+flt9toHpAFvKWCODdjd3XNoWzxxZImEVfRDLfQbIzaZ7JQ6evEMUjDrYUC7nIgQHY4bE9k810AkvaboslIC3vrYDxV2Apuw9Do8g/4RiORQoP3wxbepgNDFIekYkYec4KEM8vZxVpCtIcv93nbgV/r6sO7rjRHmjLcMpuwZttqMPeVAVzu5jB7esQcaQUfE4tDZ2u0Olglc72rr0AezqUyKGGN7xUicBtdp4rwnSgCT+43o8SnzKSj+zg0WNQJQtBerqfcwzcbbQhGv11td91sFhDqVEXeePlms05MqsPcxdiHTbuCxFVqX+te6A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jKY4GARGf7cFe6kYo7UEXRjHObM5WbMIdmYN953bGwU=; b=eNDdvrF99VdX2QLjIUB3bAT0EA2TEH0gzUvv+/Kq3+G/Q3hqYMlwOjs8CqjHHYVk1/auc+LXccNzVuf7gP8rT49k4kj6GqJ8Zs+YCxrO4SJu1Qsdt6QPNHlpkfAht17SovG0Tlgcz+S8wbwS99Q7iUO3lS6sxFmwYDnRsllCuTH4sxk0nxFaVr7F61OTv13rT4KdG+flZTD1/k0N/We4guGc1fIiLWTtLOoPPkeCe5UxDbyJjNv9BBwcWa+RByJEBvlxcsgRc6fobXJXIEtCsoMiK9XjXGYdrqBsuUawqPdiiuPeV4N9kMoOxKyOKwmF/NPAPGWRVR+hvtcS603oEg== Received: from BN6PR19CA0050.namprd19.prod.outlook.com (2603:10b6:404:e3::12) by MN2PR12MB3805.namprd12.prod.outlook.com (2603:10b6:208:15a::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Thu, 29 Apr 2021 09:56:27 +0000 Received: from BN8NAM11FT005.eop-nam11.prod.protection.outlook.com (2603:10b6:404:e3:cafe::2d) by BN6PR19CA0050.outlook.office365.com (2603:10b6:404:e3::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.32 via Frontend Transport; Thu, 29 Apr 2021 09:56:27 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT005.mail.protection.outlook.com (10.13.176.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.27 via Frontend Transport; Thu, 29 Apr 2021 09:56:27 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 09:56:25 +0000 From: Viacheslav Ovsiienko To: CC: , , , Michael Baum Date: Thu, 29 Apr 2021 12:55:42 +0300 Message-ID: <20210429095542.7800-6-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210429095542.7800-1-viacheslavo@nvidia.com> References: <20210426124250.42771-1-michaelba@nvidia.com> <20210429095542.7800-1-viacheslavo@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 391629cd-7eb2-458f-364a-08d90af50e41 X-MS-TrafficTypeDiagnostic: MN2PR12MB3805: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZXxW+3TL5IsDNfJoNMXS5OV5GsZFj4xqmFkOi9c2ZPN9klYk7+j4aSbPiY5M4ui2IU8YpEXvbdz3h9roSQmmsHpyyey8mbBalLEQ4bJc6QqsZ5t/MQWd8H0G7k7GCxRIWTtRCQcLVtMSsG1sp9/1R9aqJlc1v6/C2GOXDuzz+iIfE7Ct83WmamHyjrtcCuCMoIhfryircIHJsBPRnDxsSsQUNtbwyFTw12gtpVfDYNM+KTfYj3vwG33GaW97wvEoumWgYeFMR3bLA+hkNQ4mwfUsuchdHbZkHxgGAv3RmG+9bmAEPu0QcegIBZJ9zV1xOTrJ/uvGpsMWNq/nIKD2IZoNXlnr7SBlQsM2PnLbKuExg3ciL+eMCWgdklgqD5wqH9B6sLzc5x23ARXkkSmd0C7Rb/+ba92RAH3ArHBJdq59XfU84zoaSJ97k4t2v761KQh83tN3dCOZEDt7aGBZwrDsviG/UrmATmLjtRuiZXvAmcoXrCmY/h7jkkiGgmDOiOnbef/afpAWuDaaYmCueuIJvBRUAXJU0YOU4uqGz9XMu+1EN86X6IuMiv5xSz69ZZhK4tVWcZbqYl5UmkFfs9KIfwMMKAtQayI5xOOrfy8j1nXQfzYQXrPqvUUjT2gLVoK3Ge6cYa1wHemYLb38qF71v9yAmvNqzciAoJT4n1I= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(376002)(136003)(346002)(39860400002)(36840700001)(46966006)(82310400003)(55016002)(1076003)(4326008)(54906003)(356005)(6916009)(7636003)(6286002)(426003)(478600001)(83380400001)(70586007)(36860700001)(316002)(82740400003)(36906005)(36756003)(8936002)(186003)(6666004)(2616005)(86362001)(7696005)(26005)(5660300002)(8676002)(16526019)(47076005)(70206006)(2906002)(336012)(107886003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 09:56:27.0196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 391629cd-7eb2-458f-364a-08d90af50e41 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3805 Subject: [dpdk-dev] [PATCH v2 5/5] net/mlx5: use aging by counter when counter is existed X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Michael Baum The driver support 2 mechanisms in order to support AGE action: 1. Aging by counter - HW counter will be configured to the flow traffic, the driver polls the counter values efficiently to detect flow timeout. 2. Aging by ASO flow hit bit - HW ASO flow-hit bit is allocated for the flow, the driver polls the bit efficiently to detect flow timeout. ASO bit is only single bit resource while counter is 16 bytes, hence, it is better to use ASO instead of counter for aging. When a non-shared COUNT action is also configured to the flow, the driver can use the same counter also for AGE action and no need to create more ASO action for it. The current code always uses ASO when it is supported in the device, change it to reuse the non-shared counter if it exists in the flow. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow_dv.c | 149 ++++++++++++++++++++++---------- 1 file changed, 102 insertions(+), 47 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index b74bac1083..2fb6621017 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7143,6 +7143,12 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "Shared ASO age action is not supported for group 0"); + if (action_flags & MLX5_FLOW_ACTION_AGE) + return rte_flow_error_set + (error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, + "duplicate age actions set"); action_flags |= MLX5_FLOW_ACTION_AGE; ++actions_n; break; @@ -11162,6 +11168,47 @@ flow_dv_translate_create_aso_age(struct rte_eth_dev *dev, return age_idx; } +/** + * Prepares DV flow counter with aging configuration. + * Gets it by index when exists, creates a new one when doesn't. + * + * @param[in] dev + * Pointer to rte_eth_dev structure. + * @param[in] dev_flow + * Pointer to the mlx5_flow. + * @param[in, out] flow + * Pointer to the sub flow. + * @param[in] count + * Pointer to the counter action configuration. + * @param[in] age + * Pointer to the aging action configuration. + * @param[out] error + * Pointer to the error structure. + * + * @return + * Pointer to the counter, NULL otherwise. + */ +static struct mlx5_flow_counter * +flow_dv_prepare_counter(struct rte_eth_dev *dev, + struct mlx5_flow *dev_flow, + struct rte_flow *flow, + const struct rte_flow_action_count *count, + const struct rte_flow_action_age *age, + struct rte_flow_error *error) +{ + if (!flow->counter) { + flow->counter = flow_dv_translate_create_counter(dev, dev_flow, + count, age); + if (!flow->counter) { + rte_flow_error_set(error, rte_errno, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "cannot create counter object."); + return NULL; + } + } + return flow_dv_counter_get_by_idx(dev, flow->counter, NULL); +} + /** * Fill the flow with DV spec, lock free * (mutex should be acquired by caller). @@ -11215,7 +11262,7 @@ flow_dv_translate(struct rte_eth_dev *dev, } mhdr_dummy; struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res; const struct rte_flow_action_count *count = NULL; - const struct rte_flow_action_age *age = NULL; + const struct rte_flow_action_age *non_shared_age = NULL; union flow_dv_attr flow_attr = { .attr = 0 }; uint32_t tag_be; union mlx5_flow_tbl_key tbl_key; @@ -11230,6 +11277,7 @@ flow_dv_translate(struct rte_eth_dev *dev, const struct rte_flow_action_sample *sample = NULL; struct mlx5_flow_sub_actions_list *sample_act; uint32_t sample_act_pos = UINT32_MAX; + uint32_t age_act_pos = UINT32_MAX; uint32_t num_of_dest = 0; int tmp_actions_n = 0; uint32_t table; @@ -11452,7 +11500,12 @@ flow_dv_translate(struct rte_eth_dev *dev, age_act = flow_aso_age_get_by_idx(dev, flow->age); __atomic_fetch_add(&age_act->refcnt, 1, __ATOMIC_RELAXED); - dev_flow->dv.actions[actions_n++] = age_act->dr_action; + age_act_pos = actions_n++; + action_flags |= MLX5_FLOW_ACTION_AGE; + break; + case RTE_FLOW_ACTION_TYPE_AGE: + non_shared_age = action->conf; + age_act_pos = actions_n++; action_flags |= MLX5_FLOW_ACTION_AGE; break; case MLX5_RTE_FLOW_ACTION_TYPE_COUNT: @@ -11464,31 +11517,6 @@ flow_dv_translate(struct rte_eth_dev *dev, /* Save information first, will apply later. */ action_flags |= MLX5_FLOW_ACTION_COUNT; break; - case RTE_FLOW_ACTION_TYPE_AGE: - if (priv->sh->flow_hit_aso_en && attr->group) { - /* - * Create one shared age action, to be used - * by all sub-flows. - */ - if (!flow->age) { - flow->age = - flow_dv_translate_create_aso_age - (dev, action->conf, - error); - if (!flow->age) - return rte_flow_error_set - (error, rte_errno, - RTE_FLOW_ERROR_TYPE_ACTION, - NULL, - "can't create ASO age action"); - } - dev_flow->dv.actions[actions_n++] = - (flow_aso_age_get_by_idx - (dev, flow->age))->dr_action; - action_flags |= MLX5_FLOW_ACTION_AGE; - break; - } - /* Fall-through */ case RTE_FLOW_ACTION_TYPE_COUNT: if (!dev_conf->devx) { return rte_flow_error_set @@ -11498,10 +11526,7 @@ flow_dv_translate(struct rte_eth_dev *dev, "count action not supported"); } /* Save information first, will apply later. */ - if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT) - count = action->conf; - else - age = action->conf; + count = action->conf; action_flags |= MLX5_FLOW_ACTION_COUNT; break; case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: @@ -11801,27 +11826,57 @@ flow_dv_translate(struct rte_eth_dev *dev, dev_flow->dv.actions[modify_action_position] = handle->dvh.modify_hdr->action; } + /* + * Handle AGE and COUNT action by single HW counter + * when they are not shared. + */ + if (action_flags & MLX5_FLOW_ACTION_AGE) { + if ((non_shared_age && + count && !count->shared) || + !(priv->sh->flow_hit_aso_en && + attr->group)) { + /* Creates age by counters. */ + cnt_act = flow_dv_prepare_counter + (dev, dev_flow, + flow, count, + non_shared_age, + error); + if (!cnt_act) + return -rte_errno; + dev_flow->dv.actions[age_act_pos] = + cnt_act->action; + break; + } + if (!flow->age && non_shared_age) { + flow->age = + flow_dv_translate_create_aso_age + (dev, + non_shared_age, + error); + if (!flow->age) + return rte_flow_error_set + (error, rte_errno, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, + "can't create ASO age action"); + } + age_act = flow_aso_age_get_by_idx(dev, + flow->age); + dev_flow->dv.actions[age_act_pos] = + age_act->dr_action; + } if (action_flags & MLX5_FLOW_ACTION_COUNT) { /* * Create one count action, to be used * by all sub-flows. */ - if (!flow->counter) { - flow->counter = - flow_dv_translate_create_counter - (dev, dev_flow, count, - age); - if (!flow->counter) - return rte_flow_error_set - (error, rte_errno, - RTE_FLOW_ERROR_TYPE_ACTION, - NULL, "cannot create counter" - " object."); - } - dev_flow->dv.actions[actions_n] = - (flow_dv_counter_get_by_idx(dev, - flow->counter, NULL))->action; - actions_n++; + cnt_act = flow_dv_prepare_counter(dev, dev_flow, + flow, count, + NULL, error); + if (!cnt_act) + return -rte_errno; + dev_flow->dv.actions[actions_n++] = + cnt_act->action; } default: break;