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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT041.mail.protection.outlook.com (10.13.172.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.27 via Frontend Transport; Thu, 29 Apr 2021 15:45:07 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:45:05 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:33 +0300 Message-ID: <20210429154335.2820028-15-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a14cef10-cf10-4860-aba9-08d90b25c40c X-MS-TrafficTypeDiagnostic: BN8PR12MB3586: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:45:07.9276 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a14cef10-cf10-4860-aba9-08d90b25c40c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3586 Subject: [dpdk-dev] [PATCH v2 14/16] common/mlx5: add crypto register structs and defs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled Encryption key management requires use of several related registers. This patch adds the relevant structs and values, according to PRM definitions. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 432c8fdb63..c2cd2d9f70 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3307,6 +3307,10 @@ enum { enum { MLX5_REGISTER_ID_MTUTC = 0x9055, + MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, + MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, + MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, + MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, }; struct mlx5_ifc_register_mtutc_bits { @@ -3324,6 +3328,43 @@ struct mlx5_ifc_register_mtutc_bits { #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 +struct mlx5_ifc_crypto_operational_register_bits { + u8 wrapped_crypto_operational[0x1]; + u8 reserved_at_1[0x1b]; + u8 kek_size[0x4]; + u8 reserved_at_20[0x20]; + u8 credential[0x140]; + u8 kek[0x100]; + u8 reserved_at_280[0x180]; +}; + +struct mlx5_ifc_crypto_commissioning_register_bits { + u8 token[0x1]; /* TODO: add size after PRM update */ +}; + +struct mlx5_ifc_import_kek_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_import_kek_bits import_kek_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 import_kek_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +struct mlx5_ifc_credential_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_credential_bits credential_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 credential_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +enum { + MLX5_REGISTER_ADD_OPERATION = 0x1, + MLX5_REGISTER_DELETE_OPERATION = 0x2, +}; + struct mlx5_ifc_parse_graph_arc_bits { u8 start_inner_tunnel[0x1]; u8 reserved_at_1[0x7];