From patchwork Thu Apr 29 15:47:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92441 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 94FF6A0547; Thu, 29 Apr 2021 17:48:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A01654134A; Thu, 29 Apr 2021 17:48:31 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2075.outbound.protection.outlook.com [40.107.237.75]) by mails.dpdk.org (Postfix) with ESMTP id 292484135F for ; Thu, 29 Apr 2021 17:48:28 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=k7vSMsJC521nyc+RUUpbi/KDJHVXJM59ZBuZzGOerjeGZ4ogxNQotq+vARZ0gR5L1Jldzpg2OEgCx8lhlV+rRs73UV53+84ko/+DJxGRYLzAwpxFV3diGaVX8Su/JC4++frb3AHvYgKRgjsWLu1fkgFJsbJc0AMjs1zUYHMl5nOq2GBht27OvyLi6MezUnFrgknhXJR8SE7iq1TLTxpIuCsgziYvNj7an9t+afm5l+tWRBjw2YW+cFtwp+k4LT9kzad88FJRIprcH4DZg9Qxug3CcdLrTftwuLVJ3ZRQFQRI5hU+fZfusvS/onjn53zEDEspNBvZSDG+uHGN345McA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lnQm+QjlEtbkCRytP6U0tqL/Cx4DE1mYWPn0bqFd0/4=; b=Dgztr18Yh7Bxeq9wbZjgss3bGDhfmuZWrSR9awaStJfCGWbX3Ckm4agee4AN5K5RrPULru5jbENXT7DAjuiz54H1/14IbHf4wcfuu25gKjojZ6yRa1lva+qfapPAIYqyyN07IXpcRWMc6BHZBBaVmbRU4f0NS6Q+plNx/0DunX5jR1WZLkpwmWYV+gBTndBUYLL1FHfHClGZM6ed914/191l88kO07KL+PrGbeLWAiwy+UHZuZ7ySFyQhUMDjQ8u5CZOBRSvHc+piqKSDL/KrWDKQkQGPCyt+q+sSKhernY1H4Ys80YAkB9ZCtl41rj8cEwKiS0ydwVRNS0jkaQPwQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lnQm+QjlEtbkCRytP6U0tqL/Cx4DE1mYWPn0bqFd0/4=; b=IH0pMqWaV2lPJ6z7ZBbKHfXCf5yCaZnRzy3jB6l+3V989GC/ieRoJZeAtIkh3aEhWNgzOA54PhXJbFCMgEfJzk00jlBZoC6TXpSX/Hv9oDozDFFq1qNebKBGQqTRvebxPeRaAuFLPpcJTRIdadgXgRKyFvcGkXdjVWdUzeKFXAt1+fzl8HiEVrgs+UilSkByqhpGo3kLbaJh0mlpbGBTpPon8/vcNTT9SBnhfykrINaG6d9rJC/w+Xz3sxA+c0OkQxFzFnUM6as/eoDQcUMniAEd5TU/FNSKYFfbooN5Vw0lb/5o2RNAzCQYTXMHUEefp2uqbCi+WcOrVjQYHQHhuQ== Received: from DM5PR13CA0044.namprd13.prod.outlook.com (2603:10b6:3:7b::30) by CH0PR12MB5267.namprd12.prod.outlook.com (2603:10b6:610:d2::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.21; Thu, 29 Apr 2021 15:48:26 +0000 Received: from DM6NAM11FT014.eop-nam11.prod.protection.outlook.com (2603:10b6:3:7b:cafe::57) by DM5PR13CA0044.outlook.office365.com (2603:10b6:3:7b::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; Thu, 29 Apr 2021 15:48:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT014.mail.protection.outlook.com (10.13.173.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.32 via Frontend Transport; Thu, 29 Apr 2021 15:48:26 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:48:24 +0000 From: Matan Azrad To: CC: , , , "Shiri Kuzin" Date: Thu, 29 Apr 2021 18:47:06 +0300 Message-ID: <20210429154712.2820159-10-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154712.2820159-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154712.2820159-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fa3673d0-fb63-4501-58a5-08d90b263a84 X-MS-TrafficTypeDiagnostic: CH0PR12MB5267: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VqK18ruD2teFyY8kHsTmJmESFjOR7yic4WDDji17NHYz2c64gGDuc6RUdezUrAfaK3XC6u7epe/WBbbI2xjtqocvL0duwSdl4Lnu379LnisAo4RMeRQQCGO4BDbBG/fHg76vuAJKmHZ4OmrG1O1jRDRbit88hYA+aOLWzFAjWnHWC4f85GtV0gKqDausLEkayzXay5tYsVe3GWWYCY6oKb8bGnJFEIZQazneaTZuvUmFP3nTYflAzu4VBEifgAC1plwusY5GJTXudip/yc5ve4x6RPtySGUEEzuJqJvvhLE/KwgephvyNMniuQ7PcAR4Rz+DxfSZGkHRc3x2royJ03nEl9OkI6mLvORmGzWjzn6Vio2LE6GikvsYHKFytlrjCfBUKt62jo5wpYIh4bMJcQSdSoKZk0ZLfyCH2/D3A7GxEY21FSzTkTDUThpmC1FdTQySOc0OS8t8dRl2HpTCE/T/yCVdRnLG4yJLh7dpuBscWwiwq/SYgWpxb0EHVa3sZkoNEA0LjbxLeKHsiF7i2+8LaY6cBeQXPFPIDApt1YV32M5mWLrUp1EEx5tT8uJWHgwbp3bw76iUknIfRvmXHtlLVwNSmfJF6WUlhJlupHBX0sOLtMQfPAQYhYYAquzR/TAwE03NZAW4DvfkdYhl3Hq4q0XYEFeiPWyCdXtQteVYusUvbeSbwUnoMsywOhEEKTzxL82TX8Fc9UlZHPHXIbS+OPmR88Pblby/KkuE+s8= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(136003)(396003)(39860400002)(376002)(36840700001)(46966006)(966005)(4326008)(70586007)(7636003)(54906003)(86362001)(316002)(55016002)(6916009)(1076003)(83380400001)(8936002)(82310400003)(2616005)(36860700001)(478600001)(7696005)(16526019)(186003)(356005)(2906002)(70206006)(47076005)(336012)(5660300002)(6666004)(8676002)(82740400003)(36906005)(26005)(107886003)(6286002)(36756003)(426003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:48:26.6251 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa3673d0-fb63-4501-58a5-08d90b263a84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5267 Subject: [dpdk-dev] [PATCH v2 09/15] crypto/mlx5: adjust to the multiple data unit API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shiri Kuzin In AES-XTS the data to be encrypted\decrypted does not have to be in multiples of 16B size, the unit of data is called data-unit. As a result of patch [1] a new field is added to the cipher capability, called dataunit_set, where the devices can report the range of supported data-unit sizes. The new field enables saving the data-unit size in the session structure to the block size pointer variable in order to support several data-unit sizes. [1] https://www.mail-archive.com/dev@dpdk.org/msg205337.html Signed-off-by: Shiri Kuzin --- drivers/crypto/mlx5/mlx5_crypto.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 44038f0e05..1dcebce04c 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -48,6 +48,11 @@ struct mlx5_crypto_session { * bsf_size, bsf_p_type, encryption_order and encryption standard, * saved in big endian format. */ + uint32_t bsp_res; + /* + * crypto_block_size_pointer and reserved 24 bits saved in big endian + * format. + */ uint32_t iv_offset:16; /* Starting point for Initialisation Vector. */ struct mlx5_crypto_dek *dek; /* Pointer to dek struct. */ @@ -171,6 +176,24 @@ mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev, MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET | encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET | MLX5_ENCRYPTION_STANDARD_AES_XTS); + switch (xform->cipher.dataunit_len) { + case 0: + sess_private_data->bsp_res = 0; + break; + case 512: + sess_private_data->bsp_res = rte_cpu_to_be_32 + ((uint32_t)MLX5_BLOCK_SIZE_512B << + MLX5_BLOCK_SIZE_OFFSET); + break; + case 4096: + sess_private_data->bsp_res = rte_cpu_to_be_32 + ((uint32_t)MLX5_BLOCK_SIZE_4096B << + MLX5_BLOCK_SIZE_OFFSET); + break; + default: + DRV_LOG(ERR, "Cipher data unit length is not supported."); + return -ENOTSUP; + } sess_private_data->iv_offset = cipher->iv.offset; sess_private_data->dek_id = rte_cpu_to_be_32(sess_private_data->dek->obj->id &