From patchwork Fri Apr 30 12:57:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 92499 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1CD70A0546; Fri, 30 Apr 2021 14:58:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 69AE341269; Fri, 30 Apr 2021 14:57:55 +0200 (CEST) Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mails.dpdk.org (Postfix) with ESMTP id 65FEB4069E for ; Fri, 30 Apr 2021 14:57:49 +0200 (CEST) Received: by mail-wr1-f52.google.com with SMTP id d4so2051159wru.7 for ; Fri, 30 Apr 2021 05:57:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iHwAcvDJNpVs1MTOpW9jxXhTdpahOycpDibt5hM7LN0=; b=mQ4WOSslN9Hf3qOG9T5+D9aiPB9XT5Xan6SYXddIn/CwhHkHxrGirkgoUfpvFx71s2 LGc5i6tKKLLFH++o28niHa7CkNEDeeqBENp2tL7jrBA/UQ5QWNG5ZOTI7fNFx39g2HVK fcpaqdFtC76KN1ExHW+az527vr2s5PoppQzz8/72T8UwF4j57kkjg1lumWfBLmGvwRp/ kKWa18QmnI8tNflC7+rLsfmuX5yOX0J07NJ8OVnSknktmcpmLMy1S04e0iXRhMjpJBU1 zb4/dfXiANuP+QHFhtdpLp2/RDX85a0z3c1KGbB2mnFfarT89xWbiQwSDGXEWnjZA7xa zV7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iHwAcvDJNpVs1MTOpW9jxXhTdpahOycpDibt5hM7LN0=; b=LE/YoiV/RnQu4akmJpeqKFTeIV0k2GA2Is/CnA5rnMxdkehMrpp6gCz5ZyXssVcnAo +2K1YkqDVhryBG+UAv7D5iHoUvUCGYrafE5T3QhgH1P5JHlu1UDZFYlBB6/6imSL1iwm 9Vt61bE+dNvqKDsL7U5RXG55tAJ4IWnnpGa6uL0Whn43X1/FE33jAWbuhQlpXFJj806O Ha3LkJlX/9yavvLK+Gw+i5D3ZiFEJ34MIutopSisC6O/9M6/DhuWgXpUlbxocLfWR4vU 7PQhWD5LuGqbbpc0jsDdCeW7QeNU2dZMYcVsJvyYnDFINcsc8WIYa3GBv30RcxUbzU7V 60mw== X-Gm-Message-State: AOAM533GNDRMb3Fdve+CBT56ck5VPQ90phE+pBGpJ5Onqn1OWp0ibZMT fCAtJyR2IHOhijgVShAXgR0RfA8+VC94I1VY X-Google-Smtp-Source: ABdhPJw1ofjr9Ave0WFsJH0Pd/3ov2jm50W00Krw7Yw0LIeZIAYqEg7m1kuQPzBmu9kjnPegnA5rxA== X-Received: by 2002:a05:6000:2ad:: with SMTP id l13mr6465336wry.417.1619787468885; Fri, 30 Apr 2021 05:57:48 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id l13sm13476245wmj.3.2021.04.30.05.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 05:57:48 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazom.com, gtzalik@amazon.com, igorch@amazon.com, mw@semihalf.com, Michal Krawczyk , Amit Bernstein Date: Fri, 30 Apr 2021 14:57:13 +0200 Message-Id: <20210430125725.28796-11-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430125725.28796-1-mk@semihalf.com> References: <20210430125725.28796-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 10/22] net/ena/base: use rte_prefetch0_write X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As in the v20.11 rte_prefetch0_write API was added, it should be used in the platform file for the definition of the macro prefetchw, instead of using simply prefetch0. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_plat_dpdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index bfc0a658ef..1eec4f0c72 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -287,7 +287,7 @@ extern rte_atomic32_t ena_alloc_cnt; #define might_sleep() #define prefetch(x) rte_prefetch0(x) -#define prefetchw(x) prefetch(x) +#define prefetchw(x) rte_prefetch0_write(x) #define lower_32_bits(x) ((uint32_t)(x)) #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))