diff mbox series

[08/15] crypto/qat: add aes gcm in ucs spc mode

Message ID 20210531141027.13289-9-arkadiuszx.kusztal@intel.com (mailing list archive)
State Superseded, archived
Delegated to: akhil goyal
Headers
Series Add support for fourth generation of Intel QuickAssist Technology devices |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Arkadiusz Kusztal May 31, 2021, 2:10 p.m. UTC 
  This commit adds AES-GCM algorithm that works
in UCS (Unified crypto slice) SPC(Single-Pass) mode.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
 drivers/crypto/qat/qat_sym.c         | 32 ++++++++++++++++++++--------
 drivers/crypto/qat/qat_sym_session.c |  9 ++++----
 2 files changed, 27 insertions(+), 14 deletions(-)
diff mbox series

Patch

diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index eef4a886c5..00fc4d6b1a 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -217,6 +217,7 @@  qat_sym_build_request(void *in_op, uint8_t *out_msg,
 	int ret = 0;
 	struct qat_sym_session *ctx = NULL;
 	struct icp_qat_fw_la_cipher_req_params *cipher_param;
+	struct icp_qat_fw_la_cipher_20_req_params *cipher_param20;
 	struct icp_qat_fw_la_auth_req_params *auth_param;
 	register struct icp_qat_fw_la_bulk_req *qat_req;
 	uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
@@ -286,6 +287,7 @@  qat_sym_build_request(void *in_op, uint8_t *out_msg,
 	rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 	qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
 	cipher_param = (void *)&qat_req->serv_specif_rqpars;
+	cipher_param20 = (void *)&qat_req->serv_specif_rqpars;
 	auth_param = (void *)((uint8_t *)cipher_param +
 			ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);
 
@@ -563,13 +565,17 @@  qat_sym_build_request(void *in_op, uint8_t *out_msg,
 		cipher_param->cipher_length = 0;
 	}
 
-	if (do_auth || do_aead) {
-		auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
+	if (!ctx->is_single_pass) {
+		/* Do not let to owerwrite spc_aad len */
+		if (do_auth || do_aead) {
+			auth_param->auth_off =
+				(uint32_t)rte_pktmbuf_iova_offset(
 				op->sym->m_src, auth_ofs) - src_buf_start;
-		auth_param->auth_len = auth_len;
-	} else {
-		auth_param->auth_off = 0;
-		auth_param->auth_len = 0;
+			auth_param->auth_len = auth_len;
+		} else {
+			auth_param->auth_off = 0;
+			auth_param->auth_len = 0;
+		}
 	}
 
 	qat_req->comn_mid.dst_length =
@@ -675,10 +681,18 @@  qat_sym_build_request(void *in_op, uint8_t *out_msg,
 	}
 
 	if (ctx->is_single_pass) {
-		/* Handle Single-Pass GCM */
-		cipher_param->spc_aad_addr = op->sym->aead.aad.phys_addr;
-		cipher_param->spc_auth_res_addr =
+		if (ctx->is_ucs) {
+			/* GEN 4 */
+			cipher_param20->spc_aad_addr =
+				op->sym->aead.aad.phys_addr;
+			cipher_param20->spc_auth_res_addr =
 				op->sym->aead.digest.phys_addr;
+		} else {
+			cipher_param->spc_aad_addr =
+				op->sym->aead.aad.phys_addr;
+			cipher_param->spc_auth_res_addr =
+					op->sym->aead.digest.phys_addr;
+		}
 	} else if (ctx->is_single_pass_gmac &&
 		       op->sym->auth.data.length <= QAT_AES_GMAC_SPC_MAX_SIZE) {
 		/* Handle Single-Pass AES-GMAC */
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 4b52ffd459..7d66ca5172 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -897,16 +897,15 @@  qat_sym_session_configure_aead(struct rte_cryptodev *dev,
 
 		if (qat_dev_gen == QAT_GEN4)
 			session->is_ucs = 1;
-
 		if (session->cipher_iv.length == 0) {
 			session->cipher_iv.length = AES_GCM_J0_LEN;
 			break;
 		}
 		session->is_iv12B = 1;
-		if (qat_dev_gen == QAT_GEN3) {
-			qat_sym_session_handle_single_pass(session,
-					aead_xform);
-		}
+		if (qat_dev_gen < QAT_GEN3)
+			break;
+		qat_sym_session_handle_single_pass(session,
+				aead_xform);
 		break;
 	case RTE_CRYPTO_AEAD_AES_CCM:
 		if (qat_sym_validate_aes_key(aead_xform->key.length,