[v2,10/62] net/cnxk: add platform specific probe and remove
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Commit Message
Add platform specific probe and remove callbacks for CN9K
and CN10K which use common probe and remove functions.
Register ethdev driver for CN9K and CN10K.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
drivers/net/cnxk/cn10k_ethdev.c | 64 ++++++++++++++++++++++++++++++++
drivers/net/cnxk/cn10k_ethdev.h | 9 +++++
drivers/net/cnxk/cn9k_ethdev.c | 82 +++++++++++++++++++++++++++++++++++++++++
drivers/net/cnxk/cn9k_ethdev.h | 9 +++++
drivers/net/cnxk/cnxk_ethdev.c | 42 +++++++++++++++++++++
drivers/net/cnxk/cnxk_ethdev.h | 19 ++++++++++
drivers/net/cnxk/meson.build | 5 +++
7 files changed, 230 insertions(+)
create mode 100644 drivers/net/cnxk/cn10k_ethdev.c
create mode 100644 drivers/net/cnxk/cn10k_ethdev.h
create mode 100644 drivers/net/cnxk/cn9k_ethdev.c
create mode 100644 drivers/net/cnxk/cn9k_ethdev.h
Comments
On Mon, Jun 7, 2021 at 11:34 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> Add platform specific probe and remove callbacks for CN9K
> and CN10K which use common probe and remove functions.
> Register ethdev driver for CN9K and CN10K.
>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> ---
> drivers/net/cnxk/cn10k_ethdev.c | 64 ++++++++++++++++++++++++++++++++
> drivers/net/cnxk/cn10k_ethdev.h | 9 +++++
> drivers/net/cnxk/cn9k_ethdev.c | 82 +++++++++++++++++++++++++++++++++++++++++
> drivers/net/cnxk/cn9k_ethdev.h | 9 +++++
> drivers/net/cnxk/cnxk_ethdev.c | 42 +++++++++++++++++++++
> drivers/net/cnxk/cnxk_ethdev.h | 19 ++++++++++
> drivers/net/cnxk/meson.build | 5 +++
> 7 files changed, 230 insertions(+)
> create mode 100644 drivers/net/cnxk/cn10k_ethdev.c
> create mode 100644 drivers/net/cnxk/cn10k_ethdev.h
> create mode 100644 drivers/net/cnxk/cn9k_ethdev.c
> create mode 100644 drivers/net/cnxk/cn9k_ethdev.h
>
> diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
> new file mode 100644
> index 0000000..ff8ce31
> --- /dev/null
> +++ b/drivers/net/cnxk/cn10k_ethdev.c
> @@ -0,0 +1,64 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +#include "cn10k_ethdev.h"
> +
> +static int
> +cn10k_nix_remove(struct rte_pci_device *pci_dev)
> +{
> + return cnxk_nix_remove(pci_dev);
> +}
> +
> +static int
> +cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
> +{
> + struct rte_eth_dev *eth_dev;
> + int rc;
> +
> + if (RTE_CACHE_LINE_SIZE != 64) {
> + plt_err("Driver not compiled for CN10K");
> + return -EFAULT;
> + }
> +
> + rc = roc_plt_init();
> + if (rc) {
> + plt_err("Failed to initialize platform model, rc=%d", rc);
> + return rc;
> + }
> +
> + /* Common probe */
> + rc = cnxk_nix_probe(pci_drv, pci_dev);
> + if (rc)
> + return rc;
> +
> + if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
> + eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
> + if (!eth_dev)
> + return -ENOENT;
> + }
> + return 0;
> +}
> +
> +static const struct rte_pci_id cn10k_pci_nix_map[] = {
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
> + {
> + .vendor_id = 0,
> + },
> +};
> +
> +static struct rte_pci_driver cn10k_pci_nix = {
> + .id_table = cn10k_pci_nix_map,
> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
> + RTE_PCI_DRV_INTR_LSC,
> + .probe = cn10k_nix_probe,
> + .remove = cn10k_nix_remove,
> +};
> +
> +RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);
> +RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);
> +RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci");
> diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h
> new file mode 100644
> index 0000000..1bf4a65
> --- /dev/null
> +++ b/drivers/net/cnxk/cn10k_ethdev.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +#ifndef __CN10K_ETHDEV_H__
> +#define __CN10K_ETHDEV_H__
> +
> +#include <cnxk_ethdev.h>
> +
> +#endif /* __CN10K_ETHDEV_H__ */
> diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c
> new file mode 100644
> index 0000000..701dc12
> --- /dev/null
> +++ b/drivers/net/cnxk/cn9k_ethdev.c
> @@ -0,0 +1,82 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +#include "cn9k_ethdev.h"
> +
> +static int
> +cn9k_nix_remove(struct rte_pci_device *pci_dev)
> +{
> + return cnxk_nix_remove(pci_dev);
> +}
> +
> +static int
> +cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
> +{
> + struct rte_eth_dev *eth_dev;
> + struct cnxk_eth_dev *dev;
> + int rc;
> +
> + if (RTE_CACHE_LINE_SIZE != 128) {
> + plt_err("Driver not compiled for CN9K");
> + return -EFAULT;
> + }
> +
> + rc = roc_plt_init();
> + if (rc) {
> + plt_err("Failed to initialize platform model, rc=%d", rc);
> + return rc;
> + }
> +
> + /* Common probe */
> + rc = cnxk_nix_probe(pci_drv, pci_dev);
> + if (rc)
> + return rc;
> +
> + /* Find eth dev allocated */
> + eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
> + if (!eth_dev)
> + return -ENOENT;
> +
> + dev = cnxk_eth_pmd_priv(eth_dev);
> + /* Update capabilities already set for TSO.
> + * TSO not supported for earlier chip revisions
> + */
> + if (roc_model_is_cn96_A0() || roc_model_is_cn95_A0())
> + dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
> + DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
> + DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
> + DEV_TX_OFFLOAD_GRE_TNL_TSO);
> +
> + /* 50G and 100G to be supported for board version C0
> + * and above of CN9K.
> + */
> + if (roc_model_is_cn96_A0() || roc_model_is_cn95_A0()) {
> + dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;
> + dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;
> + }
> +
> + dev->hwcap = 0;
> +
> + /* Update HW erratas */
> + if (roc_model_is_cn96_A0() || roc_model_is_cn95_A0())
> + dev->cq_min_4k = 1;
> + return 0;
> +}
> +
> +static const struct rte_pci_id cn9k_pci_nix_map[] = {
> + {
> + .vendor_id = 0,
> + },
> +};
> +
> +static struct rte_pci_driver cn9k_pci_nix = {
> + .id_table = cn9k_pci_nix_map,
> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
> + RTE_PCI_DRV_INTR_LSC,
> + .probe = cn9k_nix_probe,
> + .remove = cn9k_nix_remove,
> +};
> +
> +RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
> +RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
> +RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");
> diff --git a/drivers/net/cnxk/cn9k_ethdev.h b/drivers/net/cnxk/cn9k_ethdev.h
> new file mode 100644
> index 0000000..15d9397
> --- /dev/null
> +++ b/drivers/net/cnxk/cn9k_ethdev.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +#ifndef __CN9K_ETHDEV_H__
> +#define __CN9K_ETHDEV_H__
> +
> +#include <cnxk_ethdev.h>
> +
> +#endif /* __CN9K_ETHDEV_H__ */
> diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
> index 6717410..b836fc2 100644
> --- a/drivers/net/cnxk/cnxk_ethdev.c
> +++ b/drivers/net/cnxk/cnxk_ethdev.c
> @@ -3,6 +3,40 @@
> */
> #include <cnxk_ethdev.h>
>
> +static inline uint64_t
> +nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
> +{
> + uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
> +
> + if (roc_nix_is_vf_or_sdp(&dev->nix))
> + capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
> +
> + return capa;
> +}
> +
> +static inline uint64_t
> +nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
> +{
> + RTE_SET_USED(dev);
> + return CNXK_NIX_TX_OFFLOAD_CAPA;
> +}
> +
> +static inline uint32_t
> +nix_get_speed_capa(struct cnxk_eth_dev *dev)
> +{
> + uint32_t speed_capa;
> +
> + /* Auto negotiation disabled */
> + speed_capa = ETH_LINK_SPEED_FIXED;
> + if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
> + speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
> + ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
> + ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
> + }
> +
> + return speed_capa;
> +}
> +
> /* CNXK platform independent eth dev ops */
> struct eth_dev_ops cnxk_eth_dev_ops;
>
> @@ -77,6 +111,14 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
> }
> }
>
> + /* Union of all capabilities supported by CNXK.
> + * Platform specific capabilities will be
> + * updated later.
> + */
> + dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
> + dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
> + dev->speed_capa = nix_get_speed_capa(dev);
> +
> /* Initialize roc npc */
> plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
> " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
> diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
> index 0460d1e..ba2bfcd 100644
> --- a/drivers/net/cnxk/cnxk_ethdev.h
> +++ b/drivers/net/cnxk/cnxk_ethdev.h
> @@ -14,6 +14,22 @@
>
> #define CNXK_ETH_DEV_PMD_VERSION "1.0"
>
> +#define CNXK_NIX_TX_OFFLOAD_CAPA \
> + (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
> + DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
> + DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
> + DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
> + DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
> + DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
> + DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
> + DEV_TX_OFFLOAD_IPV4_CKSUM)
> +
> +#define CNXK_NIX_RX_OFFLOAD_CAPA \
> + (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
> + DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
> + DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
> + DEV_RX_OFFLOAD_RSS_HASH)
> +
> struct cnxk_eth_dev {
> /* ROC NIX */
> struct roc_nix nix;
> @@ -28,6 +44,9 @@ struct cnxk_eth_dev {
>
> /* HW capabilities / Limitations */
> union {
> + struct {
> + uint64_t cq_min_4k : 1;
> + };
> uint64_t hwcap;
> };
>
> diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build
> index 77b2f18..57dea5e 100644
> --- a/drivers/net/cnxk/meson.build
> +++ b/drivers/net/cnxk/meson.build
> @@ -10,6 +10,11 @@ endif
>
> sources = files('cnxk_ethdev.c')
>
> +# CN9K
> +sources += files('cn9k_ethdev.c')
> +# CN10K
> +sources += files('cn10k_ethdev.c')
> +
> deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']
> deps += ['common_cnxk', 'mempool_cnxk']
>
> --
> 2.8.4
>
new file mode 100644
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include "cn10k_ethdev.h"
+
+static int
+cn10k_nix_remove(struct rte_pci_device *pci_dev)
+{
+ return cnxk_nix_remove(pci_dev);
+}
+
+static int
+cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
+{
+ struct rte_eth_dev *eth_dev;
+ int rc;
+
+ if (RTE_CACHE_LINE_SIZE != 64) {
+ plt_err("Driver not compiled for CN10K");
+ return -EFAULT;
+ }
+
+ rc = roc_plt_init();
+ if (rc) {
+ plt_err("Failed to initialize platform model, rc=%d", rc);
+ return rc;
+ }
+
+ /* Common probe */
+ rc = cnxk_nix_probe(pci_drv, pci_dev);
+ if (rc)
+ return rc;
+
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
+ eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
+ if (!eth_dev)
+ return -ENOENT;
+ }
+ return 0;
+}
+
+static const struct rte_pci_id cn10k_pci_nix_map[] = {
+ CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
+ CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
+ CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
+ CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
+ CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
+ CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
+ {
+ .vendor_id = 0,
+ },
+};
+
+static struct rte_pci_driver cn10k_pci_nix = {
+ .id_table = cn10k_pci_nix_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
+ RTE_PCI_DRV_INTR_LSC,
+ .probe = cn10k_nix_probe,
+ .remove = cn10k_nix_remove,
+};
+
+RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix);
+RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map);
+RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci");
new file mode 100644
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#ifndef __CN10K_ETHDEV_H__
+#define __CN10K_ETHDEV_H__
+
+#include <cnxk_ethdev.h>
+
+#endif /* __CN10K_ETHDEV_H__ */
new file mode 100644
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include "cn9k_ethdev.h"
+
+static int
+cn9k_nix_remove(struct rte_pci_device *pci_dev)
+{
+ return cnxk_nix_remove(pci_dev);
+}
+
+static int
+cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
+{
+ struct rte_eth_dev *eth_dev;
+ struct cnxk_eth_dev *dev;
+ int rc;
+
+ if (RTE_CACHE_LINE_SIZE != 128) {
+ plt_err("Driver not compiled for CN9K");
+ return -EFAULT;
+ }
+
+ rc = roc_plt_init();
+ if (rc) {
+ plt_err("Failed to initialize platform model, rc=%d", rc);
+ return rc;
+ }
+
+ /* Common probe */
+ rc = cnxk_nix_probe(pci_drv, pci_dev);
+ if (rc)
+ return rc;
+
+ /* Find eth dev allocated */
+ eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
+ if (!eth_dev)
+ return -ENOENT;
+
+ dev = cnxk_eth_pmd_priv(eth_dev);
+ /* Update capabilities already set for TSO.
+ * TSO not supported for earlier chip revisions
+ */
+ if (roc_model_is_cn96_A0() || roc_model_is_cn95_A0())
+ dev->tx_offload_capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
+ DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
+ DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
+ DEV_TX_OFFLOAD_GRE_TNL_TSO);
+
+ /* 50G and 100G to be supported for board version C0
+ * and above of CN9K.
+ */
+ if (roc_model_is_cn96_A0() || roc_model_is_cn95_A0()) {
+ dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_50G;
+ dev->speed_capa &= ~(uint64_t)ETH_LINK_SPEED_100G;
+ }
+
+ dev->hwcap = 0;
+
+ /* Update HW erratas */
+ if (roc_model_is_cn96_A0() || roc_model_is_cn95_A0())
+ dev->cq_min_4k = 1;
+ return 0;
+}
+
+static const struct rte_pci_id cn9k_pci_nix_map[] = {
+ {
+ .vendor_id = 0,
+ },
+};
+
+static struct rte_pci_driver cn9k_pci_nix = {
+ .id_table = cn9k_pci_nix_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
+ RTE_PCI_DRV_INTR_LSC,
+ .probe = cn9k_nix_probe,
+ .remove = cn9k_nix_remove,
+};
+
+RTE_PMD_REGISTER_PCI(net_cn9k, cn9k_pci_nix);
+RTE_PMD_REGISTER_PCI_TABLE(net_cn9k, cn9k_pci_nix_map);
+RTE_PMD_REGISTER_KMOD_DEP(net_cn9k, "vfio-pci");
new file mode 100644
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#ifndef __CN9K_ETHDEV_H__
+#define __CN9K_ETHDEV_H__
+
+#include <cnxk_ethdev.h>
+
+#endif /* __CN9K_ETHDEV_H__ */
@@ -3,6 +3,40 @@
*/
#include <cnxk_ethdev.h>
+static inline uint64_t
+nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
+{
+ uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
+
+ if (roc_nix_is_vf_or_sdp(&dev->nix))
+ capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
+
+ return capa;
+}
+
+static inline uint64_t
+nix_get_tx_offload_capa(struct cnxk_eth_dev *dev)
+{
+ RTE_SET_USED(dev);
+ return CNXK_NIX_TX_OFFLOAD_CAPA;
+}
+
+static inline uint32_t
+nix_get_speed_capa(struct cnxk_eth_dev *dev)
+{
+ uint32_t speed_capa;
+
+ /* Auto negotiation disabled */
+ speed_capa = ETH_LINK_SPEED_FIXED;
+ if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) {
+ speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
+ ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
+ ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
+ }
+
+ return speed_capa;
+}
+
/* CNXK platform independent eth dev ops */
struct eth_dev_ops cnxk_eth_dev_ops;
@@ -77,6 +111,14 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
}
}
+ /* Union of all capabilities supported by CNXK.
+ * Platform specific capabilities will be
+ * updated later.
+ */
+ dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
+ dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
+ dev->speed_capa = nix_get_speed_capa(dev);
+
/* Initialize roc npc */
plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
" rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
@@ -14,6 +14,22 @@
#define CNXK_ETH_DEV_PMD_VERSION "1.0"
+#define CNXK_NIX_TX_OFFLOAD_CAPA \
+ (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
+ DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
+ DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
+ DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
+ DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
+ DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
+ DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
+ DEV_TX_OFFLOAD_IPV4_CKSUM)
+
+#define CNXK_NIX_RX_OFFLOAD_CAPA \
+ (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
+ DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
+ DEV_RX_OFFLOAD_RSS_HASH)
+
struct cnxk_eth_dev {
/* ROC NIX */
struct roc_nix nix;
@@ -28,6 +44,9 @@ struct cnxk_eth_dev {
/* HW capabilities / Limitations */
union {
+ struct {
+ uint64_t cq_min_4k : 1;
+ };
uint64_t hwcap;
};
@@ -10,6 +10,11 @@ endif
sources = files('cnxk_ethdev.c')
+# CN9K
+sources += files('cn9k_ethdev.c')
+# CN10K
+sources += files('cn10k_ethdev.c')
+
deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']
deps += ['common_cnxk', 'mempool_cnxk']