diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 2c1a2a7be3..ec272c3a8f 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -79,21 +79,23 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
 			    struct ulp_rte_parser_params *params,
 			    enum bnxt_ulp_fdb_type flow_type)
 {
-	mapper_cparms->flow_type	= flow_type;
-	mapper_cparms->app_priority	= params->priority;
-	mapper_cparms->dir_attr		= params->dir_attr;
-	mapper_cparms->class_tid	= params->class_id;
-	mapper_cparms->act_tid		= params->act_tmpl;
-	mapper_cparms->func_id		= params->func_id;
-	mapper_cparms->hdr_bitmap	= &params->hdr_bitmap;
-	mapper_cparms->hdr_field	= params->hdr_field;
-	mapper_cparms->comp_fld		= params->comp_fld;
-	mapper_cparms->act		= &params->act_bitmap;
-	mapper_cparms->act_prop		= &params->act_prop;
-	mapper_cparms->flow_id		= params->fid;
-	mapper_cparms->parent_flow	= params->parent_flow;
-	mapper_cparms->parent_fid	= params->parent_fid;
-	mapper_cparms->fld_bitmap	= &params->fld_bitmap;
+	mapper_cparms->flow_type = flow_type;
+	mapper_cparms->app_priority = params->priority;
+	mapper_cparms->dir_attr = params->dir_attr;
+	mapper_cparms->class_tid = params->class_id;
+	mapper_cparms->act_tid = params->act_tmpl;
+	mapper_cparms->func_id = params->func_id;
+	mapper_cparms->hdr_bitmap = &params->hdr_bitmap;
+	mapper_cparms->hdr_field = params->hdr_field;
+	mapper_cparms->comp_fld = params->comp_fld;
+	mapper_cparms->act = &params->act_bitmap;
+	mapper_cparms->act_prop = &params->act_prop;
+	mapper_cparms->flow_id = params->fid;
+	mapper_cparms->parent_flow = params->parent_flow;
+	mapper_cparms->parent_fid = params->parent_fid;
+	mapper_cparms->fld_bitmap = &params->fld_bitmap;
+	mapper_cparms->flow_pattern_id = params->flow_pattern_id;
+	mapper_cparms->act_pattern_id = params->act_pattern_id;
 
 	/* update the signature fields into the computed field list */
 	ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index f3b8d81766..75640ce092 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -360,6 +360,9 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
 		goto err1;
 	}
 
+	BNXT_TF_DBG(DEBUG, "Creating default flow with template id: %u\n",
+		    ulp_class_tid);
+
 	/* Protect flow creation */
 	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
 		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 8537388da6..1326f79ff5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -48,21 +48,17 @@ ulp_flow_db_active_flows_bit_set(struct bnxt_ulp_flow_db *flow_db,
 	uint32_t a_idx = idx / ULP_INDEX_BITMAP_SIZE;
 
 	if (flag) {
-		if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type ==
-		    BNXT_ULP_FDB_TYPE_RID)
+		if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
 			ULP_INDEX_BITMAP_SET(f_tbl->active_reg_flows[a_idx],
 					     idx);
-		if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type ==
-		    BNXT_ULP_FDB_TYPE_RID)
+		else
 			ULP_INDEX_BITMAP_SET(f_tbl->active_dflt_flows[a_idx],
 					     idx);
 	} else {
-		if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR || flow_type ==
-		    BNXT_ULP_FDB_TYPE_RID)
+		if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
 			ULP_INDEX_BITMAP_RESET(f_tbl->active_reg_flows[a_idx],
 					       idx);
-		if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT || flow_type ==
-		    BNXT_ULP_FDB_TYPE_RID)
+		else
 			ULP_INDEX_BITMAP_RESET(f_tbl->active_dflt_flows[a_idx],
 					       idx);
 	}
@@ -89,15 +85,9 @@ ulp_flow_db_active_flows_bit_is_set(struct bnxt_ulp_flow_db *flow_db,
 	if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
 		return ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],
 					    idx);
-	else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT)
+	else
 		return ULP_INDEX_BITMAP_GET(f_tbl->active_dflt_flows[a_idx],
 					    idx);
-	else if (flow_type == BNXT_ULP_FDB_TYPE_RID)
-		return (ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],
-					     idx) &&
-			ULP_INDEX_BITMAP_GET(f_tbl->active_reg_flows[a_idx],
-					     idx));
-	return 0;
 }
 
 static inline enum tf_dir
@@ -223,7 +213,7 @@ ulp_flow_db_alloc_resource(struct bnxt_ulp_flow_db *flow_db)
 		return -ENOMEM;
 	}
 	size = (flow_tbl->num_flows / sizeof(uint64_t)) + 1;
-	size = ULP_BYTE_ROUND_OFF_8(size);
+	size =  ULP_BYTE_ROUND_OFF_8(size);
 	flow_tbl->active_reg_flows = rte_zmalloc("active reg flows", size,
 						 ULP_BUFFER_ALIGN_64_BYTE);
 	if (!flow_tbl->active_reg_flows) {
@@ -627,7 +617,7 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt,
 		return -EINVAL;
 	}
 
-	if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
+	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
 	}
@@ -684,7 +674,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
 		return -EINVAL;
 	}
 
-	if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
+	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
 	}
@@ -698,7 +688,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
 
 	/* check if the flow is active or not */
 	if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {
-		BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid);
+		BNXT_TF_DBG(ERR, "flow does not exist\n");
 		return -EINVAL;
 	}
 
@@ -779,7 +769,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
 		return -EINVAL;
 	}
 
-	if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
+	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
 	}
@@ -793,7 +783,7 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
 
 	/* check if the flow is active or not */
 	if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {
-		BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid);
+		BNXT_TF_DBG(ERR, "flow does not exist\n");
 		return -EINVAL;
 	}
 
@@ -887,7 +877,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
 		return -EINVAL;
 	}
 
-	if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
+	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
 	}
@@ -902,7 +892,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
 
 	/* check if the flow is active or not */
 	if (!ulp_flow_db_active_flows_bit_is_set(flow_db, flow_type, fid)) {
-		BNXT_TF_DBG(ERR, "flow does not exist %x:%x\n", flow_type, fid);
+		BNXT_TF_DBG(ERR, "flow does not exist\n");
 		return -EINVAL;
 	}
 	flow_tbl->head_index--;
@@ -910,7 +900,6 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
 		BNXT_TF_DBG(ERR, "FlowDB: Head Ptr is zero\n");
 		return -ENOENT;
 	}
-
 	flow_tbl->flow_tbl_stack[flow_tbl->head_index] = fid;
 
 	/* Clear the flows bitmap */
@@ -924,7 +913,7 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt,
 }
 
 /*
- *Get the flow database entry details
+ * Get the flow database entry details
  *
  * ulp_ctxt [in] Ptr to ulp_context
  * flow_type [in] - specify default or regular
@@ -951,7 +940,7 @@ ulp_flow_db_resource_get(struct bnxt_ulp_context *ulp_ctxt,
 		return -EINVAL;
 	}
 
-	if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
+	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
 	}
@@ -1007,14 +996,10 @@ ulp_flow_db_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
 	uint64_t *active_flows;
 	struct bnxt_ulp_flow_tbl *flowtbl = &flow_db->flow_tbl;
 
-	if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) {
+	if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR)
 		active_flows = flowtbl->active_reg_flows;
-	} else if (flow_type == BNXT_ULP_FDB_TYPE_DEFAULT) {
+	else
 		active_flows = flowtbl->active_dflt_flows;
-	} else {
-		BNXT_TF_DBG(ERR, "Invalid flow type %x\n", flow_type);
-			return -EINVAL;
-	}
 
 	do {
 		/* increment the flow id to find the next valid flow id */
@@ -1207,7 +1192,7 @@ ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx,
 		return -EINVAL;
 	}
 
-	if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
+	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
 	}
@@ -1609,7 +1594,7 @@ ulp_flow_db_child_flow_reset(struct bnxt_ulp_context *ulp_ctxt,
 		return -EINVAL;
 	}
 
-	if (flow_type >= BNXT_ULP_FDB_TYPE_LAST) {
+	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
 	}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index e1717b5dc4..c231f765e6 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -19,6 +19,11 @@
 #include "tf_util.h"
 #include "ulp_template_db_tbl.h"
 
+static uint8_t mapper_fld_ones[16] = {
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+};
+
 static const char *
 ulp_mapper_tmpl_name_str(enum bnxt_ulp_template_type tmpl_type)
 {
@@ -591,12 +596,11 @@ ulp_mapper_fdb_opc_process(struct bnxt_ulp_mapper_parms *parms,
 	int32_t rc = 0;
 
 	switch (tbl->fdb_opcode) {
-	case BNXT_ULP_FDB_OPC_PUSH:
+	case BNXT_ULP_FDB_OPC_PUSH_FID:
 		push_fid = parms->fid;
 		flow_type = parms->flow_type;
 		break;
-	case BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE:
-	case BNXT_ULP_FDB_OPC_PUSH_REGFILE:
+	case BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE:
 		/* get the fid from the regfile */
 		rc = ulp_regfile_read(parms->regfile, tbl->fdb_operand,
 				      &val64);
@@ -1049,6 +1053,13 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,
 			return -EINVAL;
 		}
 		break;
+	case BNXT_ULP_FIELD_SRC_ONES:
+		val = mapper_fld_ones;
+		if (!ulp_blob_push(blob, val, bitlen)) {
+			BNXT_TF_DBG(ERR, "%s too large for blob\n", name);
+			return -EINVAL;
+		}
+		break;
 	case BNXT_ULP_FIELD_SRC_CF:
 		if (!ulp_operand_read(fld_src_oper,
 				      (uint8_t *)&idx, sizeof(uint16_t))) {
@@ -2076,6 +2087,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		write = true;
 		break;
 	case BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE:
+		if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) {
+			BNXT_TF_DBG(ERR, "Template error, wrong fdb opcode\n");
+			return -EINVAL;
+		}
 		/*
 		 * get the index to write to from the global regfile and then
 		 * write the table.
@@ -2470,8 +2485,10 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 					    "Failed to scan ident list\n");
 				return -EINVAL;
 			}
-			/* increment the reference count */
-			ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent);
+			if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) {
+				/* increment the reference count */
+				ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent);
+			}
 
 			/* it is a hit */
 			gen_tbl_hit = 1;
@@ -2545,6 +2562,23 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 	return rc;
 }
 
+static int32_t
+ulp_mapper_ctrl_tbl_process(struct bnxt_ulp_mapper_parms *parms,
+			    struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+	int32_t rc = 0;
+
+	/* process the fdb opcode for alloc push */
+	if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE) {
+		rc = ulp_mapper_fdb_opc_alloc_rid(parms, tbl);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Failed to do fdb alloc\n");
+			return rc;
+		}
+	}
+	return rc;
+}
+
 static int32_t
 ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
 				  struct bnxt_ulp_mapper_data *mapper_data)
@@ -2598,7 +2632,10 @@ ulp_mapper_tbl_memtype_opcode_process(struct bnxt_ulp_mapper_parms *parms,
 	enum bnxt_ulp_flow_mem_type mtype = BNXT_ULP_FLOW_MEM_TYPE_INT;
 	int32_t rc = 1;
 
-	bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);
+	if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
+		BNXT_TF_DBG(ERR, "Failed to get the mem type\n");
+		return rc;
+	}
 
 	switch (tbl->mem_type_opcode) {
 	case BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT:
@@ -2725,6 +2762,20 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
 		}
 		*res = regval == 0;
 		break;
+	case BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:
+		if (parms->flow_pattern_id == operand) {
+			BNXT_TF_DBG(ERR, "field pattern match failed %x\n",
+				    parms->flow_pattern_id);
+			return -EINVAL;
+		}
+		break;
+	case BNXT_ULP_COND_OPC_ACT_PAT_MATCH:
+		if (parms->act_pattern_id == operand) {
+			BNXT_TF_DBG(ERR, "act pattern match failed %x\n",
+				    parms->act_pattern_id);
+			return -EINVAL;
+		}
+		break;
 	default:
 		BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc);
 		rc = -EINVAL;
@@ -2748,7 +2799,7 @@ ulp_mapper_cond_opc_list_process(struct bnxt_ulp_mapper_parms *parms,
 				 int32_t *res)
 {
 	uint32_t i;
-	int32_t rc = 0, trc;
+	int32_t rc = 0, trc = 0;
 
 	switch (list_opc) {
 	case BNXT_ULP_COND_LIST_OPC_AND:
@@ -2870,7 +2921,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
 	struct bnxt_ulp_mapper_tbl_info *tbl;
 	uint32_t num_tbls, tbl_idx, num_cond_tbls;
 	int32_t rc = -EINVAL, cond_rc = 0;
-	uint32_t cond_goto = 1;
+	int32_t cond_goto = 1;
 
 	cond_tbls = ulp_mapper_tmpl_reject_list_get(parms, tid,
 						    &num_cond_tbls,
@@ -2907,11 +2958,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
 
 	for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) {
 		tbl = &tbls[tbl_idx];
-		cond_goto = tbl->execute_info.cond_goto;
 		/* Handle the table level opcodes to determine if required. */
 		if (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) {
-			tbl_idx += 1;
-			continue;
+			cond_goto = tbl->execute_info.cond_false_goto;
+			goto next_iteration;
 		}
 
 		cond_tbls = ulp_mapper_tbl_execute_list_get(parms, tbl,
@@ -2927,17 +2977,8 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
 		}
 		/* Skip the table if False */
 		if (!cond_rc) {
-			tbl_idx += 1;
-			continue;
-		}
-
-		/* process the fdb opcode for alloc push */
-		if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE) {
-			rc = ulp_mapper_fdb_opc_alloc_rid(parms, tbl);
-			if (rc) {
-				BNXT_TF_DBG(ERR, "Failed to do fdb alloc\n");
-				return rc;
-			}
+			cond_goto = tbl->execute_info.cond_false_goto;
+			goto next_iteration;
 		}
 
 		switch (tbl->resource_func) {
@@ -2957,8 +2998,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
 		case BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE:
 			rc = ulp_mapper_gen_tbl_process(parms, tbl);
 			break;
+		case BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE:
+			rc = ulp_mapper_ctrl_tbl_process(parms, tbl);
+			break;
 		case BNXT_ULP_RESOURCE_FUNC_INVALID:
-		case BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE:
 			rc = 0;
 			break;
 		default:
@@ -2982,6 +3025,12 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
 			rc = -EINVAL;
 			goto error;
 		}
+next_iteration:
+		if (cond_goto < 0 && ((int32_t)tbl_idx + cond_goto) < 0) {
+			BNXT_TF_DBG(ERR, "invalid conditional goto %d\n",
+				    cond_goto);
+			goto error;
+		}
 		tbl_idx += cond_goto;
 	}
 
@@ -3062,7 +3111,9 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
 	 * Set the critical resource on the first resource del, then iterate
 	 * while status is good
 	 */
-	res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
+	if (flow_type != BNXT_ULP_FDB_TYPE_RID)
+		res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
+
 	rc = ulp_flow_db_resource_del(ulp_ctx, flow_type, fid, &res_parms);
 
 	if (rc) {
@@ -3236,6 +3287,8 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 	parms.fid = cparms->flow_id;
 	parms.tun_idx = cparms->tun_idx;
 	parms.app_priority = cparms->app_priority;
+	parms.flow_pattern_id = cparms->flow_pattern_id;
+	parms.act_pattern_id = cparms->act_pattern_id;
 
 	/* Get the device id from the ulp context */
 	if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index b7399b8949..8f0b894d39 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -58,6 +58,8 @@ struct bnxt_ulp_mapper_parms {
 	uint8_t					tun_idx;
 	uint32_t				app_priority;
 	uint64_t				shared_hndl;
+	uint32_t				flow_pattern_id;
+	uint32_t				act_pattern_id;
 };
 
 struct bnxt_ulp_mapper_create_parms {
@@ -80,6 +82,11 @@ struct bnxt_ulp_mapper_create_parms {
 	/* if set then create a parent flow */
 	uint32_t			parent_flow;
 	uint8_t				tun_idx;
+
+	/* support pattern based rejection */
+	uint32_t			flow_pattern_id;
+	uint32_t			act_pattern_id;
+
 };
 
 /* Function to initialize any dynamic mapper data. */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index 275214d489..46ac57ac00 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -79,6 +79,7 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
 	*class_id = class_match->class_tid;
 	params->hdr_sig_id = class_match->hdr_sig_id;
 	params->flow_sig_id = class_match->flow_sig_id;
+	params->flow_pattern_id = class_match->flow_pattern_id;
 	return BNXT_TF_RC_SUCCESS;
 
 error:
@@ -115,6 +116,7 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params,
 		goto error;
 	}
 	*act_id = act_match->act_tid;
+	params->act_pattern_id = act_match->act_pattern_id;
 	BNXT_TF_DBG(DEBUG, "Found matching action template %u\n", *act_id);
 	return BNXT_TF_RC_SUCCESS;
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index 50eac7f99b..29ec409ee8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Tue Dec  8 14:57:13 2020 */
+/* date: Thu Dec 17 19:43:07 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -18,32 +18,88 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_ACT_HID_0000] = 1,
 	[BNXT_ULP_ACT_HID_0001] = 2,
 	[BNXT_ULP_ACT_HID_0400] = 3,
-	[BNXT_ULP_ACT_HID_0325] = 4,
+	[BNXT_ULP_ACT_HID_01ab] = 4,
 	[BNXT_ULP_ACT_HID_0010] = 5,
-	[BNXT_ULP_ACT_HID_0725] = 6,
-	[BNXT_ULP_ACT_HID_0335] = 7,
+	[BNXT_ULP_ACT_HID_05ab] = 6,
+	[BNXT_ULP_ACT_HID_01bb] = 7,
 	[BNXT_ULP_ACT_HID_0002] = 8,
 	[BNXT_ULP_ACT_HID_0003] = 9,
 	[BNXT_ULP_ACT_HID_0402] = 10,
-	[BNXT_ULP_ACT_HID_0327] = 11,
+	[BNXT_ULP_ACT_HID_01ad] = 11,
 	[BNXT_ULP_ACT_HID_0012] = 12,
-	[BNXT_ULP_ACT_HID_0727] = 13,
-	[BNXT_ULP_ACT_HID_0337] = 14,
-	[BNXT_ULP_ACT_HID_01de] = 15,
-	[BNXT_ULP_ACT_HID_00c6] = 16,
-	[BNXT_ULP_ACT_HID_0506] = 17,
-	[BNXT_ULP_ACT_HID_01ed] = 18,
-	[BNXT_ULP_ACT_HID_03ef] = 19,
-	[BNXT_ULP_ACT_HID_0516] = 20,
-	[BNXT_ULP_ACT_HID_01df] = 21,
-	[BNXT_ULP_ACT_HID_01e4] = 22,
-	[BNXT_ULP_ACT_HID_00cc] = 23,
-	[BNXT_ULP_ACT_HID_0504] = 24,
-	[BNXT_ULP_ACT_HID_01ef] = 25,
-	[BNXT_ULP_ACT_HID_03ed] = 26,
-	[BNXT_ULP_ACT_HID_0514] = 27,
-	[BNXT_ULP_ACT_HID_00db] = 28,
-	[BNXT_ULP_ACT_HID_00df] = 29
+	[BNXT_ULP_ACT_HID_05ad] = 13,
+	[BNXT_ULP_ACT_HID_01bd] = 14,
+	[BNXT_ULP_ACT_HID_0613] = 15,
+	[BNXT_ULP_ACT_HID_02a9] = 16,
+	[BNXT_ULP_ACT_HID_0054] = 17,
+	[BNXT_ULP_ACT_HID_0622] = 18,
+	[BNXT_ULP_ACT_HID_0454] = 19,
+	[BNXT_ULP_ACT_HID_0064] = 20,
+	[BNXT_ULP_ACT_HID_0614] = 21,
+	[BNXT_ULP_ACT_HID_0615] = 22,
+	[BNXT_ULP_ACT_HID_02ab] = 23,
+	[BNXT_ULP_ACT_HID_0056] = 24,
+	[BNXT_ULP_ACT_HID_0624] = 25,
+	[BNXT_ULP_ACT_HID_0456] = 26,
+	[BNXT_ULP_ACT_HID_0066] = 27,
+	[BNXT_ULP_ACT_HID_048d] = 28,
+	[BNXT_ULP_ACT_HID_048f] = 29,
+	[BNXT_ULP_ACT_HID_04bc] = 30,
+	[BNXT_ULP_ACT_HID_00a9] = 31,
+	[BNXT_ULP_ACT_HID_020f] = 32,
+	[BNXT_ULP_ACT_HID_04a9] = 33,
+	[BNXT_ULP_ACT_HID_01fc] = 34,
+	[BNXT_ULP_ACT_HID_04be] = 35,
+	[BNXT_ULP_ACT_HID_00ab] = 36,
+	[BNXT_ULP_ACT_HID_0211] = 37,
+	[BNXT_ULP_ACT_HID_04ab] = 38,
+	[BNXT_ULP_ACT_HID_01fe] = 39,
+	[BNXT_ULP_ACT_HID_0667] = 40,
+	[BNXT_ULP_ACT_HID_0254] = 41,
+	[BNXT_ULP_ACT_HID_03ba] = 42,
+	[BNXT_ULP_ACT_HID_0654] = 43,
+	[BNXT_ULP_ACT_HID_03a7] = 44,
+	[BNXT_ULP_ACT_HID_0669] = 45,
+	[BNXT_ULP_ACT_HID_0256] = 46,
+	[BNXT_ULP_ACT_HID_03bc] = 47,
+	[BNXT_ULP_ACT_HID_0656] = 48,
+	[BNXT_ULP_ACT_HID_03a9] = 49,
+	[BNXT_ULP_ACT_HID_021b] = 50,
+	[BNXT_ULP_ACT_HID_021c] = 51,
+	[BNXT_ULP_ACT_HID_021e] = 52,
+	[BNXT_ULP_ACT_HID_063f] = 53,
+	[BNXT_ULP_ACT_HID_0510] = 54,
+	[BNXT_ULP_ACT_HID_03c6] = 55,
+	[BNXT_ULP_ACT_HID_0082] = 56,
+	[BNXT_ULP_ACT_HID_06bb] = 57,
+	[BNXT_ULP_ACT_HID_021d] = 58,
+	[BNXT_ULP_ACT_HID_0641] = 59,
+	[BNXT_ULP_ACT_HID_0512] = 60,
+	[BNXT_ULP_ACT_HID_03c8] = 61,
+	[BNXT_ULP_ACT_HID_0084] = 62,
+	[BNXT_ULP_ACT_HID_06bd] = 63,
+	[BNXT_ULP_ACT_HID_06d7] = 64,
+	[BNXT_ULP_ACT_HID_02c4] = 65,
+	[BNXT_ULP_ACT_HID_042a] = 66,
+	[BNXT_ULP_ACT_HID_06c4] = 67,
+	[BNXT_ULP_ACT_HID_0417] = 68,
+	[BNXT_ULP_ACT_HID_06d9] = 69,
+	[BNXT_ULP_ACT_HID_02c6] = 70,
+	[BNXT_ULP_ACT_HID_042c] = 71,
+	[BNXT_ULP_ACT_HID_06c6] = 72,
+	[BNXT_ULP_ACT_HID_0419] = 73,
+	[BNXT_ULP_ACT_HID_0119] = 74,
+	[BNXT_ULP_ACT_HID_046f] = 75,
+	[BNXT_ULP_ACT_HID_05d5] = 76,
+	[BNXT_ULP_ACT_HID_0106] = 77,
+	[BNXT_ULP_ACT_HID_05c2] = 78,
+	[BNXT_ULP_ACT_HID_011b] = 79,
+	[BNXT_ULP_ACT_HID_0471] = 80,
+	[BNXT_ULP_ACT_HID_05d7] = 81,
+	[BNXT_ULP_ACT_HID_0108] = 82,
+	[BNXT_ULP_ACT_HID_05c4] = 83,
+	[BNXT_ULP_ACT_HID_00a2] = 84,
+	[BNXT_ULP_ACT_HID_00a4] = 85
 };
 
 /* Array for the act matcher list */
@@ -69,7 +125,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[4] = {
-	.act_hid = BNXT_ULP_ACT_HID_0325,
+	.act_hid = BNXT_ULP_ACT_HID_01ab,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -83,7 +139,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[6] = {
-	.act_hid = BNXT_ULP_ACT_HID_0725,
+	.act_hid = BNXT_ULP_ACT_HID_05ab,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_DEC_TTL |
 		BNXT_ULP_ACT_BIT_POP_VLAN |
@@ -91,7 +147,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[7] = {
-	.act_hid = BNXT_ULP_ACT_HID_0335,
+	.act_hid = BNXT_ULP_ACT_HID_01bb,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -122,7 +178,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[11] = {
-	.act_hid = BNXT_ULP_ACT_HID_0327,
+	.act_hid = BNXT_ULP_ACT_HID_01ad,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -138,7 +194,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[13] = {
-	.act_hid = BNXT_ULP_ACT_HID_0727,
+	.act_hid = BNXT_ULP_ACT_HID_05ad,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -147,7 +203,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[14] = {
-	.act_hid = BNXT_ULP_ACT_HID_0337,
+	.act_hid = BNXT_ULP_ACT_HID_01bd,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
@@ -156,7 +212,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[15] = {
-	.act_hid = BNXT_ULP_ACT_HID_01de,
+	.act_hid = BNXT_ULP_ACT_HID_0613,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_DROP |
@@ -164,7 +220,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[16] = {
-	.act_hid = BNXT_ULP_ACT_HID_00c6,
+	.act_hid = BNXT_ULP_ACT_HID_02a9,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_POP_VLAN |
@@ -172,7 +228,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[17] = {
-	.act_hid = BNXT_ULP_ACT_HID_0506,
+	.act_hid = BNXT_ULP_ACT_HID_0054,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -180,7 +236,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[18] = {
-	.act_hid = BNXT_ULP_ACT_HID_01ed,
+	.act_hid = BNXT_ULP_ACT_HID_0622,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
@@ -188,7 +244,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[19] = {
-	.act_hid = BNXT_ULP_ACT_HID_03ef,
+	.act_hid = BNXT_ULP_ACT_HID_0454,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -197,7 +253,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[20] = {
-	.act_hid = BNXT_ULP_ACT_HID_0516,
+	.act_hid = BNXT_ULP_ACT_HID_0064,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_VXLAN_DECAP |
@@ -206,7 +262,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[21] = {
-	.act_hid = BNXT_ULP_ACT_HID_01df,
+	.act_hid = BNXT_ULP_ACT_HID_0614,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
@@ -214,7 +270,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[22] = {
-	.act_hid = BNXT_ULP_ACT_HID_01e4,
+	.act_hid = BNXT_ULP_ACT_HID_0615,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
@@ -223,7 +279,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[23] = {
-	.act_hid = BNXT_ULP_ACT_HID_00cc,
+	.act_hid = BNXT_ULP_ACT_HID_02ab,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
@@ -232,7 +288,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[24] = {
-	.act_hid = BNXT_ULP_ACT_HID_0504,
+	.act_hid = BNXT_ULP_ACT_HID_0056,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
@@ -241,7 +297,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[25] = {
-	.act_hid = BNXT_ULP_ACT_HID_01ef,
+	.act_hid = BNXT_ULP_ACT_HID_0624,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
@@ -250,7 +306,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[26] = {
-	.act_hid = BNXT_ULP_ACT_HID_03ed,
+	.act_hid = BNXT_ULP_ACT_HID_0456,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
@@ -260,7 +316,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[27] = {
-	.act_hid = BNXT_ULP_ACT_HID_0514,
+	.act_hid = BNXT_ULP_ACT_HID_0066,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
@@ -270,7 +326,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 1
 	},
 	[28] = {
-	.act_hid = BNXT_ULP_ACT_HID_00db,
+	.act_hid = BNXT_ULP_ACT_HID_048d,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED |
 		BNXT_ULP_ACT_BIT_SAMPLE |
@@ -278,12 +334,514 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 2
 	},
 	[29] = {
-	.act_hid = BNXT_ULP_ACT_HID_00df,
+	.act_hid = BNXT_ULP_ACT_HID_048f,
 	.act_sig = { .bits =
 		BNXT_ULP_ACT_BIT_SHARED |
 		BNXT_ULP_ACT_BIT_SAMPLE |
 		BNXT_ULP_ACT_BIT_COUNT |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.act_tid = 2
+	},
+	[30] = {
+	.act_hid = BNXT_ULP_ACT_HID_04bc,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[31] = {
+	.act_hid = BNXT_ULP_ACT_HID_00a9,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[32] = {
+	.act_hid = BNXT_ULP_ACT_HID_020f,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[33] = {
+	.act_hid = BNXT_ULP_ACT_HID_04a9,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[34] = {
+	.act_hid = BNXT_ULP_ACT_HID_01fc,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[35] = {
+	.act_hid = BNXT_ULP_ACT_HID_04be,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[36] = {
+	.act_hid = BNXT_ULP_ACT_HID_00ab,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[37] = {
+	.act_hid = BNXT_ULP_ACT_HID_0211,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[38] = {
+	.act_hid = BNXT_ULP_ACT_HID_04ab,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[39] = {
+	.act_hid = BNXT_ULP_ACT_HID_01fe,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[40] = {
+	.act_hid = BNXT_ULP_ACT_HID_0667,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[41] = {
+	.act_hid = BNXT_ULP_ACT_HID_0254,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[42] = {
+	.act_hid = BNXT_ULP_ACT_HID_03ba,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[43] = {
+	.act_hid = BNXT_ULP_ACT_HID_0654,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[44] = {
+	.act_hid = BNXT_ULP_ACT_HID_03a7,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[45] = {
+	.act_hid = BNXT_ULP_ACT_HID_0669,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[46] = {
+	.act_hid = BNXT_ULP_ACT_HID_0256,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[47] = {
+	.act_hid = BNXT_ULP_ACT_HID_03bc,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[48] = {
+	.act_hid = BNXT_ULP_ACT_HID_0656,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[49] = {
+	.act_hid = BNXT_ULP_ACT_HID_03a9,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.act_tid = 3
+	},
+	[50] = {
+	.act_hid = BNXT_ULP_ACT_HID_021b,
+	.act_sig = { .bits =
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[51] = {
+	.act_hid = BNXT_ULP_ACT_HID_021c,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[52] = {
+	.act_hid = BNXT_ULP_ACT_HID_021e,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DROP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[53] = {
+	.act_hid = BNXT_ULP_ACT_HID_063f,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[54] = {
+	.act_hid = BNXT_ULP_ACT_HID_0510,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[55] = {
+	.act_hid = BNXT_ULP_ACT_HID_03c6,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[56] = {
+	.act_hid = BNXT_ULP_ACT_HID_0082,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[57] = {
+	.act_hid = BNXT_ULP_ACT_HID_06bb,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[58] = {
+	.act_hid = BNXT_ULP_ACT_HID_021d,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[59] = {
+	.act_hid = BNXT_ULP_ACT_HID_0641,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[60] = {
+	.act_hid = BNXT_ULP_ACT_HID_0512,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[61] = {
+	.act_hid = BNXT_ULP_ACT_HID_03c8,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[62] = {
+	.act_hid = BNXT_ULP_ACT_HID_0084,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[63] = {
+	.act_hid = BNXT_ULP_ACT_HID_06bd,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+		BNXT_ULP_ACT_BIT_PUSH_VLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 4
+	},
+	[64] = {
+	.act_hid = BNXT_ULP_ACT_HID_06d7,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[65] = {
+	.act_hid = BNXT_ULP_ACT_HID_02c4,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[66] = {
+	.act_hid = BNXT_ULP_ACT_HID_042a,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[67] = {
+	.act_hid = BNXT_ULP_ACT_HID_06c4,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[68] = {
+	.act_hid = BNXT_ULP_ACT_HID_0417,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[69] = {
+	.act_hid = BNXT_ULP_ACT_HID_06d9,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[70] = {
+	.act_hid = BNXT_ULP_ACT_HID_02c6,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[71] = {
+	.act_hid = BNXT_ULP_ACT_HID_042c,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[72] = {
+	.act_hid = BNXT_ULP_ACT_HID_06c6,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[73] = {
+	.act_hid = BNXT_ULP_ACT_HID_0419,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[74] = {
+	.act_hid = BNXT_ULP_ACT_HID_0119,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[75] = {
+	.act_hid = BNXT_ULP_ACT_HID_046f,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[76] = {
+	.act_hid = BNXT_ULP_ACT_HID_05d5,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[77] = {
+	.act_hid = BNXT_ULP_ACT_HID_0106,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[78] = {
+	.act_hid = BNXT_ULP_ACT_HID_05c2,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[79] = {
+	.act_hid = BNXT_ULP_ACT_HID_011b,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[80] = {
+	.act_hid = BNXT_ULP_ACT_HID_0471,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[81] = {
+	.act_hid = BNXT_ULP_ACT_HID_05d7,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[82] = {
+	.act_hid = BNXT_ULP_ACT_HID_0108,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[83] = {
+	.act_hid = BNXT_ULP_ACT_HID_05c4,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_DEC_TTL |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+		BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+		BNXT_ULP_ACT_BIT_SET_TP_SRC |
+		BNXT_ULP_ACT_BIT_SET_TP_DST |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 5
+	},
+	[84] = {
+	.act_hid = BNXT_ULP_ACT_HID_00a2,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
+	},
+	[85] = {
+	.act_hid = BNXT_ULP_ACT_HID_00a4,
+	.act_sig = { .bits =
+		BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+		BNXT_ULP_ACT_BIT_COUNT |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.act_tid = 6
 	}
 };
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index 0d9531fa0f..c37829aea9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Dec  7 09:51:03 2020 */
+/* date: Wed Dec 16 16:37:41 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -16,1736 +16,80484 @@
  * maps hash id to ulp_class_match_list[] index
  */
 uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
-	[BNXT_ULP_CLASS_HID_005c] = 1,
-	[BNXT_ULP_CLASS_HID_0003] = 2,
-	[BNXT_ULP_CLASS_HID_0132] = 3,
-	[BNXT_ULP_CLASS_HID_00e1] = 4,
-	[BNXT_ULP_CLASS_HID_0044] = 5,
-	[BNXT_ULP_CLASS_HID_001b] = 6,
-	[BNXT_ULP_CLASS_HID_012a] = 7,
-	[BNXT_ULP_CLASS_HID_00f9] = 8,
-	[BNXT_ULP_CLASS_HID_018d] = 9,
-	[BNXT_ULP_CLASS_HID_00a7] = 10,
-	[BNXT_ULP_CLASS_HID_006f] = 11,
-	[BNXT_ULP_CLASS_HID_0181] = 12,
-	[BNXT_ULP_CLASS_HID_0195] = 13,
-	[BNXT_ULP_CLASS_HID_00bf] = 14,
-	[BNXT_ULP_CLASS_HID_0077] = 15,
-	[BNXT_ULP_CLASS_HID_0199] = 16,
-	[BNXT_ULP_CLASS_HID_009a] = 17,
-	[BNXT_ULP_CLASS_HID_0192] = 18,
-	[BNXT_ULP_CLASS_HID_01e2] = 19,
-	[BNXT_ULP_CLASS_HID_00fa] = 20,
-	[BNXT_ULP_CLASS_HID_0165] = 21,
-	[BNXT_ULP_CLASS_HID_0042] = 22,
-	[BNXT_ULP_CLASS_HID_00cd] = 23,
-	[BNXT_ULP_CLASS_HID_01aa] = 24,
-	[BNXT_ULP_CLASS_HID_0178] = 25,
-	[BNXT_ULP_CLASS_HID_0070] = 26,
-	[BNXT_ULP_CLASS_HID_00f3] = 27,
-	[BNXT_ULP_CLASS_HID_01d8] = 28,
-	[BNXT_ULP_CLASS_HID_005b] = 29,
-	[BNXT_ULP_CLASS_HID_0153] = 30,
-	[BNXT_ULP_CLASS_HID_01a3] = 31,
-	[BNXT_ULP_CLASS_HID_00bb] = 32,
-	[BNXT_ULP_CLASS_HID_0082] = 33,
-	[BNXT_ULP_CLASS_HID_018a] = 34,
-	[BNXT_ULP_CLASS_HID_01fa] = 35,
-	[BNXT_ULP_CLASS_HID_00e2] = 36,
-	[BNXT_ULP_CLASS_HID_017d] = 37,
-	[BNXT_ULP_CLASS_HID_005a] = 38,
-	[BNXT_ULP_CLASS_HID_00d5] = 39,
-	[BNXT_ULP_CLASS_HID_01b2] = 40,
-	[BNXT_ULP_CLASS_HID_0160] = 41,
-	[BNXT_ULP_CLASS_HID_0068] = 42,
-	[BNXT_ULP_CLASS_HID_00eb] = 43,
-	[BNXT_ULP_CLASS_HID_01c0] = 44,
-	[BNXT_ULP_CLASS_HID_0043] = 45,
-	[BNXT_ULP_CLASS_HID_014b] = 46,
-	[BNXT_ULP_CLASS_HID_01bb] = 47,
-	[BNXT_ULP_CLASS_HID_00a3] = 48,
-	[BNXT_ULP_CLASS_HID_00cb] = 49,
-	[BNXT_ULP_CLASS_HID_00b4] = 50,
-	[BNXT_ULP_CLASS_HID_0013] = 51,
-	[BNXT_ULP_CLASS_HID_001c] = 52,
-	[BNXT_ULP_CLASS_HID_017b] = 53,
-	[BNXT_ULP_CLASS_HID_0164] = 54,
-	[BNXT_ULP_CLASS_HID_00c3] = 55,
-	[BNXT_ULP_CLASS_HID_00cc] = 56,
-	[BNXT_ULP_CLASS_HID_01a5] = 57,
-	[BNXT_ULP_CLASS_HID_0196] = 58,
-	[BNXT_ULP_CLASS_HID_010d] = 59,
-	[BNXT_ULP_CLASS_HID_00fe] = 60,
-	[BNXT_ULP_CLASS_HID_0084] = 61,
-	[BNXT_ULP_CLASS_HID_0046] = 62,
-	[BNXT_ULP_CLASS_HID_01ec] = 63,
-	[BNXT_ULP_CLASS_HID_01ae] = 64,
-	[BNXT_ULP_CLASS_HID_00d3] = 65,
-	[BNXT_ULP_CLASS_HID_00ac] = 66,
-	[BNXT_ULP_CLASS_HID_000b] = 67,
-	[BNXT_ULP_CLASS_HID_0004] = 68,
-	[BNXT_ULP_CLASS_HID_0163] = 69,
-	[BNXT_ULP_CLASS_HID_017c] = 70,
-	[BNXT_ULP_CLASS_HID_00db] = 71,
-	[BNXT_ULP_CLASS_HID_00d4] = 72,
-	[BNXT_ULP_CLASS_HID_01bd] = 73,
-	[BNXT_ULP_CLASS_HID_018e] = 74,
-	[BNXT_ULP_CLASS_HID_0115] = 75,
-	[BNXT_ULP_CLASS_HID_00e6] = 76,
-	[BNXT_ULP_CLASS_HID_009c] = 77,
-	[BNXT_ULP_CLASS_HID_005e] = 78,
-	[BNXT_ULP_CLASS_HID_01f4] = 79,
-	[BNXT_ULP_CLASS_HID_01b6] = 80
+	[BNXT_ULP_CLASS_HID_26d1] = 1,
+	[BNXT_ULP_CLASS_HID_0071] = 2,
+	[BNXT_ULP_CLASS_HID_53a5] = 3,
+	[BNXT_ULP_CLASS_HID_1d49] = 4,
+	[BNXT_ULP_CLASS_HID_2095] = 5,
+	[BNXT_ULP_CLASS_HID_5701] = 6,
+	[BNXT_ULP_CLASS_HID_4d79] = 7,
+	[BNXT_ULP_CLASS_HID_170d] = 8,
+	[BNXT_ULP_CLASS_HID_1a69] = 9,
+	[BNXT_ULP_CLASS_HID_50c5] = 10,
+	[BNXT_ULP_CLASS_HID_473d] = 11,
+	[BNXT_ULP_CLASS_HID_10c1] = 12,
+	[BNXT_ULP_CLASS_HID_142d] = 13,
+	[BNXT_ULP_CLASS_HID_4a99] = 14,
+	[BNXT_ULP_CLASS_HID_40f1] = 15,
+	[BNXT_ULP_CLASS_HID_0a85] = 16,
+	[BNXT_ULP_CLASS_HID_0179] = 17,
+	[BNXT_ULP_CLASS_HID_37d5] = 18,
+	[BNXT_ULP_CLASS_HID_2e4d] = 19,
+	[BNXT_ULP_CLASS_HID_54ad] = 20,
+	[BNXT_ULP_CLASS_HID_5809] = 21,
+	[BNXT_ULP_CLASS_HID_31a9] = 22,
+	[BNXT_ULP_CLASS_HID_2801] = 23,
+	[BNXT_ULP_CLASS_HID_4e61] = 24,
+	[BNXT_ULP_CLASS_HID_2561] = 25,
+	[BNXT_ULP_CLASS_HID_2bad] = 26,
+	[BNXT_ULP_CLASS_HID_26f1] = 27,
+	[BNXT_ULP_CLASS_HID_13cf1] = 28,
+	[BNXT_ULP_CLASS_HID_252f1] = 29,
+	[BNXT_ULP_CLASS_HID_30c25] = 30,
+	[BNXT_ULP_CLASS_HID_0051] = 31,
+	[BNXT_ULP_CLASS_HID_11651] = 32,
+	[BNXT_ULP_CLASS_HID_22c51] = 33,
+	[BNXT_ULP_CLASS_HID_34251] = 34,
+	[BNXT_ULP_CLASS_HID_5385] = 35,
+	[BNXT_ULP_CLASS_HID_10cc9] = 36,
+	[BNXT_ULP_CLASS_HID_222c9] = 37,
+	[BNXT_ULP_CLASS_HID_338c9] = 38,
+	[BNXT_ULP_CLASS_HID_1d69] = 39,
+	[BNXT_ULP_CLASS_HID_13369] = 40,
+	[BNXT_ULP_CLASS_HID_24969] = 41,
+	[BNXT_ULP_CLASS_HID_3025d] = 42,
+	[BNXT_ULP_CLASS_HID_20b5] = 43,
+	[BNXT_ULP_CLASS_HID_136b5] = 44,
+	[BNXT_ULP_CLASS_HID_24cb5] = 45,
+	[BNXT_ULP_CLASS_HID_305f9] = 46,
+	[BNXT_ULP_CLASS_HID_5721] = 47,
+	[BNXT_ULP_CLASS_HID_11015] = 48,
+	[BNXT_ULP_CLASS_HID_22615] = 49,
+	[BNXT_ULP_CLASS_HID_33c15] = 50,
+	[BNXT_ULP_CLASS_HID_4d59] = 51,
+	[BNXT_ULP_CLASS_HID_1068d] = 52,
+	[BNXT_ULP_CLASS_HID_21c8d] = 53,
+	[BNXT_ULP_CLASS_HID_3328d] = 54,
+	[BNXT_ULP_CLASS_HID_172d] = 55,
+	[BNXT_ULP_CLASS_HID_12d2d] = 56,
+	[BNXT_ULP_CLASS_HID_2432d] = 57,
+	[BNXT_ULP_CLASS_HID_3592d] = 58,
+	[BNXT_ULP_CLASS_HID_1a49] = 59,
+	[BNXT_ULP_CLASS_HID_13049] = 60,
+	[BNXT_ULP_CLASS_HID_24649] = 61,
+	[BNXT_ULP_CLASS_HID_35c49] = 62,
+	[BNXT_ULP_CLASS_HID_50e5] = 63,
+	[BNXT_ULP_CLASS_HID_10a29] = 64,
+	[BNXT_ULP_CLASS_HID_22029] = 65,
+	[BNXT_ULP_CLASS_HID_33629] = 66,
+	[BNXT_ULP_CLASS_HID_471d] = 67,
+	[BNXT_ULP_CLASS_HID_10041] = 68,
+	[BNXT_ULP_CLASS_HID_21641] = 69,
+	[BNXT_ULP_CLASS_HID_32c41] = 70,
+	[BNXT_ULP_CLASS_HID_10e1] = 71,
+	[BNXT_ULP_CLASS_HID_126e1] = 72,
+	[BNXT_ULP_CLASS_HID_23ce1] = 73,
+	[BNXT_ULP_CLASS_HID_352e1] = 74,
+	[BNXT_ULP_CLASS_HID_140d] = 75,
+	[BNXT_ULP_CLASS_HID_12a0d] = 76,
+	[BNXT_ULP_CLASS_HID_2400d] = 77,
+	[BNXT_ULP_CLASS_HID_3560d] = 78,
+	[BNXT_ULP_CLASS_HID_4ab9] = 79,
+	[BNXT_ULP_CLASS_HID_103ed] = 80,
+	[BNXT_ULP_CLASS_HID_219ed] = 81,
+	[BNXT_ULP_CLASS_HID_32fed] = 82,
+	[BNXT_ULP_CLASS_HID_40d1] = 83,
+	[BNXT_ULP_CLASS_HID_156d1] = 84,
+	[BNXT_ULP_CLASS_HID_21005] = 85,
+	[BNXT_ULP_CLASS_HID_32605] = 86,
+	[BNXT_ULP_CLASS_HID_0aa5] = 87,
+	[BNXT_ULP_CLASS_HID_120a5] = 88,
+	[BNXT_ULP_CLASS_HID_236a5] = 89,
+	[BNXT_ULP_CLASS_HID_34ca5] = 90,
+	[BNXT_ULP_CLASS_HID_0159] = 91,
+	[BNXT_ULP_CLASS_HID_11759] = 92,
+	[BNXT_ULP_CLASS_HID_22d59] = 93,
+	[BNXT_ULP_CLASS_HID_34359] = 94,
+	[BNXT_ULP_CLASS_HID_37f5] = 95,
+	[BNXT_ULP_CLASS_HID_14df5] = 96,
+	[BNXT_ULP_CLASS_HID_20739] = 97,
+	[BNXT_ULP_CLASS_HID_31d39] = 98,
+	[BNXT_ULP_CLASS_HID_2e6d] = 99,
+	[BNXT_ULP_CLASS_HID_1446d] = 100,
+	[BNXT_ULP_CLASS_HID_25a6d] = 101,
+	[BNXT_ULP_CLASS_HID_31351] = 102,
+	[BNXT_ULP_CLASS_HID_548d] = 103,
+	[BNXT_ULP_CLASS_HID_10df1] = 104,
+	[BNXT_ULP_CLASS_HID_223f1] = 105,
+	[BNXT_ULP_CLASS_HID_339f1] = 106,
+	[BNXT_ULP_CLASS_HID_5829] = 107,
+	[BNXT_ULP_CLASS_HID_1111d] = 108,
+	[BNXT_ULP_CLASS_HID_2271d] = 109,
+	[BNXT_ULP_CLASS_HID_33d1d] = 110,
+	[BNXT_ULP_CLASS_HID_3189] = 111,
+	[BNXT_ULP_CLASS_HID_14789] = 112,
+	[BNXT_ULP_CLASS_HID_200fd] = 113,
+	[BNXT_ULP_CLASS_HID_316fd] = 114,
+	[BNXT_ULP_CLASS_HID_2821] = 115,
+	[BNXT_ULP_CLASS_HID_13e21] = 116,
+	[BNXT_ULP_CLASS_HID_25421] = 117,
+	[BNXT_ULP_CLASS_HID_30d15] = 118,
+	[BNXT_ULP_CLASS_HID_4e41] = 119,
+	[BNXT_ULP_CLASS_HID_107b5] = 120,
+	[BNXT_ULP_CLASS_HID_21db5] = 121,
+	[BNXT_ULP_CLASS_HID_333b5] = 122,
+	[BNXT_ULP_CLASS_HID_2541] = 123,
+	[BNXT_ULP_CLASS_HID_2b8d] = 124,
+	[BNXT_ULP_CLASS_HID_2691] = 125,
+	[BNXT_ULP_CLASS_HID_13c91] = 126,
+	[BNXT_ULP_CLASS_HID_25291] = 127,
+	[BNXT_ULP_CLASS_HID_30c45] = 128,
+	[BNXT_ULP_CLASS_HID_0031] = 129,
+	[BNXT_ULP_CLASS_HID_11631] = 130,
+	[BNXT_ULP_CLASS_HID_22c31] = 131,
+	[BNXT_ULP_CLASS_HID_34231] = 132,
+	[BNXT_ULP_CLASS_HID_53e5] = 133,
+	[BNXT_ULP_CLASS_HID_10ca9] = 134,
+	[BNXT_ULP_CLASS_HID_222a9] = 135,
+	[BNXT_ULP_CLASS_HID_338a9] = 136,
+	[BNXT_ULP_CLASS_HID_1d09] = 137,
+	[BNXT_ULP_CLASS_HID_13309] = 138,
+	[BNXT_ULP_CLASS_HID_24909] = 139,
+	[BNXT_ULP_CLASS_HID_3023d] = 140,
+	[BNXT_ULP_CLASS_HID_20d5] = 141,
+	[BNXT_ULP_CLASS_HID_136d5] = 142,
+	[BNXT_ULP_CLASS_HID_24cd5] = 143,
+	[BNXT_ULP_CLASS_HID_30599] = 144,
+	[BNXT_ULP_CLASS_HID_5741] = 145,
+	[BNXT_ULP_CLASS_HID_11075] = 146,
+	[BNXT_ULP_CLASS_HID_22675] = 147,
+	[BNXT_ULP_CLASS_HID_33c75] = 148,
+	[BNXT_ULP_CLASS_HID_4d39] = 149,
+	[BNXT_ULP_CLASS_HID_106ed] = 150,
+	[BNXT_ULP_CLASS_HID_21ced] = 151,
+	[BNXT_ULP_CLASS_HID_332ed] = 152,
+	[BNXT_ULP_CLASS_HID_174d] = 153,
+	[BNXT_ULP_CLASS_HID_12d4d] = 154,
+	[BNXT_ULP_CLASS_HID_2434d] = 155,
+	[BNXT_ULP_CLASS_HID_3594d] = 156,
+	[BNXT_ULP_CLASS_HID_1a29] = 157,
+	[BNXT_ULP_CLASS_HID_13029] = 158,
+	[BNXT_ULP_CLASS_HID_24629] = 159,
+	[BNXT_ULP_CLASS_HID_35c29] = 160,
+	[BNXT_ULP_CLASS_HID_5085] = 161,
+	[BNXT_ULP_CLASS_HID_10a49] = 162,
+	[BNXT_ULP_CLASS_HID_22049] = 163,
+	[BNXT_ULP_CLASS_HID_33649] = 164,
+	[BNXT_ULP_CLASS_HID_477d] = 165,
+	[BNXT_ULP_CLASS_HID_10021] = 166,
+	[BNXT_ULP_CLASS_HID_21621] = 167,
+	[BNXT_ULP_CLASS_HID_32c21] = 168,
+	[BNXT_ULP_CLASS_HID_1081] = 169,
+	[BNXT_ULP_CLASS_HID_12681] = 170,
+	[BNXT_ULP_CLASS_HID_23c81] = 171,
+	[BNXT_ULP_CLASS_HID_35281] = 172,
+	[BNXT_ULP_CLASS_HID_146d] = 173,
+	[BNXT_ULP_CLASS_HID_12a6d] = 174,
+	[BNXT_ULP_CLASS_HID_2406d] = 175,
+	[BNXT_ULP_CLASS_HID_3566d] = 176,
+	[BNXT_ULP_CLASS_HID_4ad9] = 177,
+	[BNXT_ULP_CLASS_HID_1038d] = 178,
+	[BNXT_ULP_CLASS_HID_2198d] = 179,
+	[BNXT_ULP_CLASS_HID_32f8d] = 180,
+	[BNXT_ULP_CLASS_HID_40b1] = 181,
+	[BNXT_ULP_CLASS_HID_156b1] = 182,
+	[BNXT_ULP_CLASS_HID_21065] = 183,
+	[BNXT_ULP_CLASS_HID_32665] = 184,
+	[BNXT_ULP_CLASS_HID_0ac5] = 185,
+	[BNXT_ULP_CLASS_HID_120c5] = 186,
+	[BNXT_ULP_CLASS_HID_236c5] = 187,
+	[BNXT_ULP_CLASS_HID_34cc5] = 188,
+	[BNXT_ULP_CLASS_HID_0139] = 189,
+	[BNXT_ULP_CLASS_HID_11739] = 190,
+	[BNXT_ULP_CLASS_HID_22d39] = 191,
+	[BNXT_ULP_CLASS_HID_34339] = 192,
+	[BNXT_ULP_CLASS_HID_3795] = 193,
+	[BNXT_ULP_CLASS_HID_14d95] = 194,
+	[BNXT_ULP_CLASS_HID_20759] = 195,
+	[BNXT_ULP_CLASS_HID_31d59] = 196,
+	[BNXT_ULP_CLASS_HID_2e0d] = 197,
+	[BNXT_ULP_CLASS_HID_1440d] = 198,
+	[BNXT_ULP_CLASS_HID_25a0d] = 199,
+	[BNXT_ULP_CLASS_HID_31331] = 200,
+	[BNXT_ULP_CLASS_HID_54ed] = 201,
+	[BNXT_ULP_CLASS_HID_10d91] = 202,
+	[BNXT_ULP_CLASS_HID_22391] = 203,
+	[BNXT_ULP_CLASS_HID_33991] = 204,
+	[BNXT_ULP_CLASS_HID_5849] = 205,
+	[BNXT_ULP_CLASS_HID_1117d] = 206,
+	[BNXT_ULP_CLASS_HID_2277d] = 207,
+	[BNXT_ULP_CLASS_HID_33d7d] = 208,
+	[BNXT_ULP_CLASS_HID_31e9] = 209,
+	[BNXT_ULP_CLASS_HID_147e9] = 210,
+	[BNXT_ULP_CLASS_HID_2009d] = 211,
+	[BNXT_ULP_CLASS_HID_3169d] = 212,
+	[BNXT_ULP_CLASS_HID_2841] = 213,
+	[BNXT_ULP_CLASS_HID_13e41] = 214,
+	[BNXT_ULP_CLASS_HID_25441] = 215,
+	[BNXT_ULP_CLASS_HID_30d75] = 216,
+	[BNXT_ULP_CLASS_HID_4e21] = 217,
+	[BNXT_ULP_CLASS_HID_107d5] = 218,
+	[BNXT_ULP_CLASS_HID_21dd5] = 219,
+	[BNXT_ULP_CLASS_HID_333d5] = 220,
+	[BNXT_ULP_CLASS_HID_2521] = 221,
+	[BNXT_ULP_CLASS_HID_2bed] = 222,
+	[BNXT_ULP_CLASS_HID_1865] = 223,
+	[BNXT_ULP_CLASS_HID_389d] = 224,
+	[BNXT_ULP_CLASS_HID_123d] = 225,
+	[BNXT_ULP_CLASS_HID_4ef1] = 226,
+	[BNXT_ULP_CLASS_HID_1229] = 227,
+	[BNXT_ULP_CLASS_HID_3241] = 228,
+	[BNXT_ULP_CLASS_HID_0be1] = 229,
+	[BNXT_ULP_CLASS_HID_48b5] = 230,
+	[BNXT_ULP_CLASS_HID_0bed] = 231,
+	[BNXT_ULP_CLASS_HID_2c05] = 232,
+	[BNXT_ULP_CLASS_HID_05a5] = 233,
+	[BNXT_ULP_CLASS_HID_4279] = 234,
+	[BNXT_ULP_CLASS_HID_05d1] = 235,
+	[BNXT_ULP_CLASS_HID_25c9] = 236,
+	[BNXT_ULP_CLASS_HID_5c55] = 237,
+	[BNXT_ULP_CLASS_HID_3c3d] = 238,
+	[BNXT_ULP_CLASS_HID_4fc9] = 239,
+	[BNXT_ULP_CLASS_HID_1335] = 240,
+	[BNXT_ULP_CLASS_HID_4981] = 241,
+	[BNXT_ULP_CLASS_HID_2969] = 242,
+	[BNXT_ULP_CLASS_HID_498d] = 243,
+	[BNXT_ULP_CLASS_HID_0cf9] = 244,
+	[BNXT_ULP_CLASS_HID_4345] = 245,
+	[BNXT_ULP_CLASS_HID_232d] = 246,
+	[BNXT_ULP_CLASS_HID_2579] = 247,
+	[BNXT_ULP_CLASS_HID_2bb5] = 248,
+	[BNXT_ULP_CLASS_HID_1845] = 249,
+	[BNXT_ULP_CLASS_HID_1399] = 250,
+	[BNXT_ULP_CLASS_HID_0eed] = 251,
+	[BNXT_ULP_CLASS_HID_0a21] = 252,
+	[BNXT_ULP_CLASS_HID_38bd] = 253,
+	[BNXT_ULP_CLASS_HID_33f1] = 254,
+	[BNXT_ULP_CLASS_HID_2ec5] = 255,
+	[BNXT_ULP_CLASS_HID_2a19] = 256,
+	[BNXT_ULP_CLASS_HID_121d] = 257,
+	[BNXT_ULP_CLASS_HID_0d51] = 258,
+	[BNXT_ULP_CLASS_HID_08a5] = 259,
+	[BNXT_ULP_CLASS_HID_03f9] = 260,
+	[BNXT_ULP_CLASS_HID_4ed1] = 261,
+	[BNXT_ULP_CLASS_HID_4a25] = 262,
+	[BNXT_ULP_CLASS_HID_4579] = 263,
+	[BNXT_ULP_CLASS_HID_404d] = 264,
+	[BNXT_ULP_CLASS_HID_1209] = 265,
+	[BNXT_ULP_CLASS_HID_0d5d] = 266,
+	[BNXT_ULP_CLASS_HID_0891] = 267,
+	[BNXT_ULP_CLASS_HID_03e5] = 268,
+	[BNXT_ULP_CLASS_HID_3261] = 269,
+	[BNXT_ULP_CLASS_HID_2db5] = 270,
+	[BNXT_ULP_CLASS_HID_2889] = 271,
+	[BNXT_ULP_CLASS_HID_23dd] = 272,
+	[BNXT_ULP_CLASS_HID_0bc1] = 273,
+	[BNXT_ULP_CLASS_HID_0715] = 274,
+	[BNXT_ULP_CLASS_HID_0269] = 275,
+	[BNXT_ULP_CLASS_HID_5a69] = 276,
+	[BNXT_ULP_CLASS_HID_4895] = 277,
+	[BNXT_ULP_CLASS_HID_43e9] = 278,
+	[BNXT_ULP_CLASS_HID_3f3d] = 279,
+	[BNXT_ULP_CLASS_HID_3a71] = 280,
+	[BNXT_ULP_CLASS_HID_0bcd] = 281,
+	[BNXT_ULP_CLASS_HID_0701] = 282,
+	[BNXT_ULP_CLASS_HID_0255] = 283,
+	[BNXT_ULP_CLASS_HID_5a55] = 284,
+	[BNXT_ULP_CLASS_HID_2c25] = 285,
+	[BNXT_ULP_CLASS_HID_2779] = 286,
+	[BNXT_ULP_CLASS_HID_224d] = 287,
+	[BNXT_ULP_CLASS_HID_1d81] = 288,
+	[BNXT_ULP_CLASS_HID_0585] = 289,
+	[BNXT_ULP_CLASS_HID_00d9] = 290,
+	[BNXT_ULP_CLASS_HID_58d9] = 291,
+	[BNXT_ULP_CLASS_HID_542d] = 292,
+	[BNXT_ULP_CLASS_HID_4259] = 293,
+	[BNXT_ULP_CLASS_HID_3dad] = 294,
+	[BNXT_ULP_CLASS_HID_38e1] = 295,
+	[BNXT_ULP_CLASS_HID_3435] = 296,
+	[BNXT_ULP_CLASS_HID_05f1] = 297,
+	[BNXT_ULP_CLASS_HID_00c5] = 298,
+	[BNXT_ULP_CLASS_HID_58c5] = 299,
+	[BNXT_ULP_CLASS_HID_5419] = 300,
+	[BNXT_ULP_CLASS_HID_25e9] = 301,
+	[BNXT_ULP_CLASS_HID_213d] = 302,
+	[BNXT_ULP_CLASS_HID_1c71] = 303,
+	[BNXT_ULP_CLASS_HID_1745] = 304,
+	[BNXT_ULP_CLASS_HID_5c75] = 305,
+	[BNXT_ULP_CLASS_HID_5749] = 306,
+	[BNXT_ULP_CLASS_HID_529d] = 307,
+	[BNXT_ULP_CLASS_HID_4dd1] = 308,
+	[BNXT_ULP_CLASS_HID_3c1d] = 309,
+	[BNXT_ULP_CLASS_HID_3751] = 310,
+	[BNXT_ULP_CLASS_HID_32a5] = 311,
+	[BNXT_ULP_CLASS_HID_2df9] = 312,
+	[BNXT_ULP_CLASS_HID_4fe9] = 313,
+	[BNXT_ULP_CLASS_HID_4b3d] = 314,
+	[BNXT_ULP_CLASS_HID_4671] = 315,
+	[BNXT_ULP_CLASS_HID_4145] = 316,
+	[BNXT_ULP_CLASS_HID_1315] = 317,
+	[BNXT_ULP_CLASS_HID_0e69] = 318,
+	[BNXT_ULP_CLASS_HID_09bd] = 319,
+	[BNXT_ULP_CLASS_HID_04f1] = 320,
+	[BNXT_ULP_CLASS_HID_49a1] = 321,
+	[BNXT_ULP_CLASS_HID_44f5] = 322,
+	[BNXT_ULP_CLASS_HID_3fc9] = 323,
+	[BNXT_ULP_CLASS_HID_3b1d] = 324,
+	[BNXT_ULP_CLASS_HID_2949] = 325,
+	[BNXT_ULP_CLASS_HID_249d] = 326,
+	[BNXT_ULP_CLASS_HID_1fd1] = 327,
+	[BNXT_ULP_CLASS_HID_1b25] = 328,
+	[BNXT_ULP_CLASS_HID_49ad] = 329,
+	[BNXT_ULP_CLASS_HID_44e1] = 330,
+	[BNXT_ULP_CLASS_HID_4035] = 331,
+	[BNXT_ULP_CLASS_HID_3b09] = 332,
+	[BNXT_ULP_CLASS_HID_0cd9] = 333,
+	[BNXT_ULP_CLASS_HID_082d] = 334,
+	[BNXT_ULP_CLASS_HID_0361] = 335,
+	[BNXT_ULP_CLASS_HID_5b61] = 336,
+	[BNXT_ULP_CLASS_HID_4365] = 337,
+	[BNXT_ULP_CLASS_HID_3eb9] = 338,
+	[BNXT_ULP_CLASS_HID_398d] = 339,
+	[BNXT_ULP_CLASS_HID_34c1] = 340,
+	[BNXT_ULP_CLASS_HID_230d] = 341,
+	[BNXT_ULP_CLASS_HID_1e41] = 342,
+	[BNXT_ULP_CLASS_HID_1995] = 343,
+	[BNXT_ULP_CLASS_HID_14e9] = 344,
+	[BNXT_ULP_CLASS_HID_2559] = 345,
+	[BNXT_ULP_CLASS_HID_2b95] = 346,
+	[BNXT_ULP_CLASS_HID_1825] = 347,
+	[BNXT_ULP_CLASS_HID_13f9] = 348,
+	[BNXT_ULP_CLASS_HID_0e8d] = 349,
+	[BNXT_ULP_CLASS_HID_0a41] = 350,
+	[BNXT_ULP_CLASS_HID_38dd] = 351,
+	[BNXT_ULP_CLASS_HID_3391] = 352,
+	[BNXT_ULP_CLASS_HID_2ea5] = 353,
+	[BNXT_ULP_CLASS_HID_2a79] = 354,
+	[BNXT_ULP_CLASS_HID_127d] = 355,
+	[BNXT_ULP_CLASS_HID_0d31] = 356,
+	[BNXT_ULP_CLASS_HID_08c5] = 357,
+	[BNXT_ULP_CLASS_HID_0399] = 358,
+	[BNXT_ULP_CLASS_HID_4eb1] = 359,
+	[BNXT_ULP_CLASS_HID_4a45] = 360,
+	[BNXT_ULP_CLASS_HID_4519] = 361,
+	[BNXT_ULP_CLASS_HID_402d] = 362,
+	[BNXT_ULP_CLASS_HID_1269] = 363,
+	[BNXT_ULP_CLASS_HID_0d3d] = 364,
+	[BNXT_ULP_CLASS_HID_08f1] = 365,
+	[BNXT_ULP_CLASS_HID_0385] = 366,
+	[BNXT_ULP_CLASS_HID_3201] = 367,
+	[BNXT_ULP_CLASS_HID_2dd5] = 368,
+	[BNXT_ULP_CLASS_HID_28e9] = 369,
+	[BNXT_ULP_CLASS_HID_23bd] = 370,
+	[BNXT_ULP_CLASS_HID_0ba1] = 371,
+	[BNXT_ULP_CLASS_HID_0775] = 372,
+	[BNXT_ULP_CLASS_HID_0209] = 373,
+	[BNXT_ULP_CLASS_HID_5a09] = 374,
+	[BNXT_ULP_CLASS_HID_48f5] = 375,
+	[BNXT_ULP_CLASS_HID_4389] = 376,
+	[BNXT_ULP_CLASS_HID_3f5d] = 377,
+	[BNXT_ULP_CLASS_HID_3a11] = 378,
+	[BNXT_ULP_CLASS_HID_0bad] = 379,
+	[BNXT_ULP_CLASS_HID_0761] = 380,
+	[BNXT_ULP_CLASS_HID_0235] = 381,
+	[BNXT_ULP_CLASS_HID_5a35] = 382,
+	[BNXT_ULP_CLASS_HID_2c45] = 383,
+	[BNXT_ULP_CLASS_HID_2719] = 384,
+	[BNXT_ULP_CLASS_HID_222d] = 385,
+	[BNXT_ULP_CLASS_HID_1de1] = 386,
+	[BNXT_ULP_CLASS_HID_05e5] = 387,
+	[BNXT_ULP_CLASS_HID_00b9] = 388,
+	[BNXT_ULP_CLASS_HID_58b9] = 389,
+	[BNXT_ULP_CLASS_HID_544d] = 390,
+	[BNXT_ULP_CLASS_HID_4239] = 391,
+	[BNXT_ULP_CLASS_HID_3dcd] = 392,
+	[BNXT_ULP_CLASS_HID_3881] = 393,
+	[BNXT_ULP_CLASS_HID_3455] = 394,
+	[BNXT_ULP_CLASS_HID_0591] = 395,
+	[BNXT_ULP_CLASS_HID_00a5] = 396,
+	[BNXT_ULP_CLASS_HID_58a5] = 397,
+	[BNXT_ULP_CLASS_HID_5479] = 398,
+	[BNXT_ULP_CLASS_HID_2589] = 399,
+	[BNXT_ULP_CLASS_HID_215d] = 400,
+	[BNXT_ULP_CLASS_HID_1c11] = 401,
+	[BNXT_ULP_CLASS_HID_1725] = 402,
+	[BNXT_ULP_CLASS_HID_5c15] = 403,
+	[BNXT_ULP_CLASS_HID_5729] = 404,
+	[BNXT_ULP_CLASS_HID_52fd] = 405,
+	[BNXT_ULP_CLASS_HID_4db1] = 406,
+	[BNXT_ULP_CLASS_HID_3c7d] = 407,
+	[BNXT_ULP_CLASS_HID_3731] = 408,
+	[BNXT_ULP_CLASS_HID_32c5] = 409,
+	[BNXT_ULP_CLASS_HID_2d99] = 410,
+	[BNXT_ULP_CLASS_HID_4f89] = 411,
+	[BNXT_ULP_CLASS_HID_4b5d] = 412,
+	[BNXT_ULP_CLASS_HID_4611] = 413,
+	[BNXT_ULP_CLASS_HID_4125] = 414,
+	[BNXT_ULP_CLASS_HID_1375] = 415,
+	[BNXT_ULP_CLASS_HID_0e09] = 416,
+	[BNXT_ULP_CLASS_HID_09dd] = 417,
+	[BNXT_ULP_CLASS_HID_0491] = 418,
+	[BNXT_ULP_CLASS_HID_49c1] = 419,
+	[BNXT_ULP_CLASS_HID_4495] = 420,
+	[BNXT_ULP_CLASS_HID_3fa9] = 421,
+	[BNXT_ULP_CLASS_HID_3b7d] = 422,
+	[BNXT_ULP_CLASS_HID_2929] = 423,
+	[BNXT_ULP_CLASS_HID_24fd] = 424,
+	[BNXT_ULP_CLASS_HID_1fb1] = 425,
+	[BNXT_ULP_CLASS_HID_1b45] = 426,
+	[BNXT_ULP_CLASS_HID_49cd] = 427,
+	[BNXT_ULP_CLASS_HID_4481] = 428,
+	[BNXT_ULP_CLASS_HID_4055] = 429,
+	[BNXT_ULP_CLASS_HID_3b69] = 430,
+	[BNXT_ULP_CLASS_HID_0cb9] = 431,
+	[BNXT_ULP_CLASS_HID_084d] = 432,
+	[BNXT_ULP_CLASS_HID_0301] = 433,
+	[BNXT_ULP_CLASS_HID_5b01] = 434,
+	[BNXT_ULP_CLASS_HID_4305] = 435,
+	[BNXT_ULP_CLASS_HID_3ed9] = 436,
+	[BNXT_ULP_CLASS_HID_39ed] = 437,
+	[BNXT_ULP_CLASS_HID_34a1] = 438,
+	[BNXT_ULP_CLASS_HID_236d] = 439,
+	[BNXT_ULP_CLASS_HID_1e21] = 440,
+	[BNXT_ULP_CLASS_HID_19f5] = 441,
+	[BNXT_ULP_CLASS_HID_1489] = 442,
+	[BNXT_ULP_CLASS_HID_2539] = 443,
+	[BNXT_ULP_CLASS_HID_2bf5] = 444,
+	[BNXT_ULP_CLASS_HID_b6af] = 445,
+	[BNXT_ULP_CLASS_HID_b1d3] = 446,
+	[BNXT_ULP_CLASS_HID_1c7d3] = 447,
+	[BNXT_ULP_CLASS_HID_1ccaf] = 448,
+	[BNXT_ULP_CLASS_HID_da33] = 449,
+	[BNXT_ULP_CLASS_HID_d567] = 450,
+	[BNXT_ULP_CLASS_HID_18eab] = 451,
+	[BNXT_ULP_CLASS_HID_19367] = 452,
+	[BNXT_ULP_CLASS_HID_a10b] = 453,
+	[BNXT_ULP_CLASS_HID_9c3f] = 454,
+	[BNXT_ULP_CLASS_HID_1b23f] = 455,
+	[BNXT_ULP_CLASS_HID_1b70b] = 456,
+	[BNXT_ULP_CLASS_HID_c49f] = 457,
+	[BNXT_ULP_CLASS_HID_bfc3] = 458,
+	[BNXT_ULP_CLASS_HID_1d5c3] = 459,
+	[BNXT_ULP_CLASS_HID_1da9f] = 460,
+	[BNXT_ULP_CLASS_HID_b063] = 461,
+	[BNXT_ULP_CLASS_HID_ab97] = 462,
+	[BNXT_ULP_CLASS_HID_1c197] = 463,
+	[BNXT_ULP_CLASS_HID_1c663] = 464,
+	[BNXT_ULP_CLASS_HID_d3f7] = 465,
+	[BNXT_ULP_CLASS_HID_cf3b] = 466,
+	[BNXT_ULP_CLASS_HID_1886f] = 467,
+	[BNXT_ULP_CLASS_HID_18d3b] = 468,
+	[BNXT_ULP_CLASS_HID_9acf] = 469,
+	[BNXT_ULP_CLASS_HID_95f3] = 470,
+	[BNXT_ULP_CLASS_HID_1abf3] = 471,
+	[BNXT_ULP_CLASS_HID_1b0cf] = 472,
+	[BNXT_ULP_CLASS_HID_be53] = 473,
+	[BNXT_ULP_CLASS_HID_b987] = 474,
+	[BNXT_ULP_CLASS_HID_1cf87] = 475,
+	[BNXT_ULP_CLASS_HID_1d453] = 476,
+	[BNXT_ULP_CLASS_HID_aa27] = 477,
+	[BNXT_ULP_CLASS_HID_a56b] = 478,
+	[BNXT_ULP_CLASS_HID_1bb6b] = 479,
+	[BNXT_ULP_CLASS_HID_1c027] = 480,
+	[BNXT_ULP_CLASS_HID_cdcb] = 481,
+	[BNXT_ULP_CLASS_HID_c8ff] = 482,
+	[BNXT_ULP_CLASS_HID_18223] = 483,
+	[BNXT_ULP_CLASS_HID_186ff] = 484,
+	[BNXT_ULP_CLASS_HID_9483] = 485,
+	[BNXT_ULP_CLASS_HID_8fb7] = 486,
+	[BNXT_ULP_CLASS_HID_1a5b7] = 487,
+	[BNXT_ULP_CLASS_HID_1aa83] = 488,
+	[BNXT_ULP_CLASS_HID_b817] = 489,
+	[BNXT_ULP_CLASS_HID_b35b] = 490,
+	[BNXT_ULP_CLASS_HID_1c95b] = 491,
+	[BNXT_ULP_CLASS_HID_1ce17] = 492,
+	[BNXT_ULP_CLASS_HID_a3fb] = 493,
+	[BNXT_ULP_CLASS_HID_9f2f] = 494,
+	[BNXT_ULP_CLASS_HID_1b52f] = 495,
+	[BNXT_ULP_CLASS_HID_1b9fb] = 496,
+	[BNXT_ULP_CLASS_HID_c78f] = 497,
+	[BNXT_ULP_CLASS_HID_c2b3] = 498,
+	[BNXT_ULP_CLASS_HID_1d8b3] = 499,
+	[BNXT_ULP_CLASS_HID_180b3] = 500,
+	[BNXT_ULP_CLASS_HID_8e47] = 501,
+	[BNXT_ULP_CLASS_HID_898b] = 502,
+	[BNXT_ULP_CLASS_HID_19f8b] = 503,
+	[BNXT_ULP_CLASS_HID_1a447] = 504,
+	[BNXT_ULP_CLASS_HID_b1eb] = 505,
+	[BNXT_ULP_CLASS_HID_ad1f] = 506,
+	[BNXT_ULP_CLASS_HID_1c31f] = 507,
+	[BNXT_ULP_CLASS_HID_1c7eb] = 508,
+	[BNXT_ULP_CLASS_HID_9137] = 509,
+	[BNXT_ULP_CLASS_HID_8c7b] = 510,
+	[BNXT_ULP_CLASS_HID_1a27b] = 511,
+	[BNXT_ULP_CLASS_HID_1a737] = 512,
+	[BNXT_ULP_CLASS_HID_b4db] = 513,
+	[BNXT_ULP_CLASS_HID_b00f] = 514,
+	[BNXT_ULP_CLASS_HID_1c60f] = 515,
+	[BNXT_ULP_CLASS_HID_1cadb] = 516,
+	[BNXT_ULP_CLASS_HID_8b0b] = 517,
+	[BNXT_ULP_CLASS_HID_863f] = 518,
+	[BNXT_ULP_CLASS_HID_19c3f] = 519,
+	[BNXT_ULP_CLASS_HID_1a10b] = 520,
+	[BNXT_ULP_CLASS_HID_ae9f] = 521,
+	[BNXT_ULP_CLASS_HID_a9c3] = 522,
+	[BNXT_ULP_CLASS_HID_1bfc3] = 523,
+	[BNXT_ULP_CLASS_HID_1c49f] = 524,
+	[BNXT_ULP_CLASS_HID_2563] = 525,
+	[BNXT_ULP_CLASS_HID_2baf] = 526,
+	[BNXT_ULP_CLASS_HID_4f33] = 527,
+	[BNXT_ULP_CLASS_HID_160b] = 528,
+	[BNXT_ULP_CLASS_HID_399f] = 529,
+	[BNXT_ULP_CLASS_HID_48f7] = 530,
+	[BNXT_ULP_CLASS_HID_0fcf] = 531,
+	[BNXT_ULP_CLASS_HID_3353] = 532,
+	[BNXT_ULP_CLASS_HID_b68f] = 533,
+	[BNXT_ULP_CLASS_HID_b94f] = 534,
+	[BNXT_ULP_CLASS_HID_fc0f] = 535,
+	[BNXT_ULP_CLASS_HID_fecf] = 536,
+	[BNXT_ULP_CLASS_HID_b1f3] = 537,
+	[BNXT_ULP_CLASS_HID_b4b3] = 538,
+	[BNXT_ULP_CLASS_HID_f773] = 539,
+	[BNXT_ULP_CLASS_HID_fa33] = 540,
+	[BNXT_ULP_CLASS_HID_1c7f3] = 541,
+	[BNXT_ULP_CLASS_HID_1eab3] = 542,
+	[BNXT_ULP_CLASS_HID_1cd73] = 543,
+	[BNXT_ULP_CLASS_HID_1f033] = 544,
+	[BNXT_ULP_CLASS_HID_1cc8f] = 545,
+	[BNXT_ULP_CLASS_HID_1ef4f] = 546,
+	[BNXT_ULP_CLASS_HID_1d20f] = 547,
+	[BNXT_ULP_CLASS_HID_1f4cf] = 548,
+	[BNXT_ULP_CLASS_HID_da13] = 549,
+	[BNXT_ULP_CLASS_HID_a007] = 550,
+	[BNXT_ULP_CLASS_HID_c2c7] = 551,
+	[BNXT_ULP_CLASS_HID_e587] = 552,
+	[BNXT_ULP_CLASS_HID_d547] = 553,
+	[BNXT_ULP_CLASS_HID_f807] = 554,
+	[BNXT_ULP_CLASS_HID_dac7] = 555,
+	[BNXT_ULP_CLASS_HID_e0cb] = 556,
+	[BNXT_ULP_CLASS_HID_18e8b] = 557,
+	[BNXT_ULP_CLASS_HID_1b14b] = 558,
+	[BNXT_ULP_CLASS_HID_1d40b] = 559,
+	[BNXT_ULP_CLASS_HID_1f6cb] = 560,
+	[BNXT_ULP_CLASS_HID_19347] = 561,
+	[BNXT_ULP_CLASS_HID_1b607] = 562,
+	[BNXT_ULP_CLASS_HID_1d8c7] = 563,
+	[BNXT_ULP_CLASS_HID_1fb87] = 564,
+	[BNXT_ULP_CLASS_HID_a12b] = 565,
+	[BNXT_ULP_CLASS_HID_a3eb] = 566,
+	[BNXT_ULP_CLASS_HID_e6ab] = 567,
+	[BNXT_ULP_CLASS_HID_e96b] = 568,
+	[BNXT_ULP_CLASS_HID_9c1f] = 569,
+	[BNXT_ULP_CLASS_HID_bedf] = 570,
+	[BNXT_ULP_CLASS_HID_e19f] = 571,
+	[BNXT_ULP_CLASS_HID_e45f] = 572,
+	[BNXT_ULP_CLASS_HID_1b21f] = 573,
+	[BNXT_ULP_CLASS_HID_1b4df] = 574,
+	[BNXT_ULP_CLASS_HID_1f79f] = 575,
+	[BNXT_ULP_CLASS_HID_1fa5f] = 576,
+	[BNXT_ULP_CLASS_HID_1b72b] = 577,
+	[BNXT_ULP_CLASS_HID_1b9eb] = 578,
+	[BNXT_ULP_CLASS_HID_1fcab] = 579,
+	[BNXT_ULP_CLASS_HID_1ff6b] = 580,
+	[BNXT_ULP_CLASS_HID_c4bf] = 581,
+	[BNXT_ULP_CLASS_HID_e77f] = 582,
+	[BNXT_ULP_CLASS_HID_ca3f] = 583,
+	[BNXT_ULP_CLASS_HID_ecff] = 584,
+	[BNXT_ULP_CLASS_HID_bfe3] = 585,
+	[BNXT_ULP_CLASS_HID_e2a3] = 586,
+	[BNXT_ULP_CLASS_HID_c563] = 587,
+	[BNXT_ULP_CLASS_HID_e823] = 588,
+	[BNXT_ULP_CLASS_HID_1d5e3] = 589,
+	[BNXT_ULP_CLASS_HID_1f8a3] = 590,
+	[BNXT_ULP_CLASS_HID_1db63] = 591,
+	[BNXT_ULP_CLASS_HID_1e117] = 592,
+	[BNXT_ULP_CLASS_HID_1dabf] = 593,
+	[BNXT_ULP_CLASS_HID_1a0a3] = 594,
+	[BNXT_ULP_CLASS_HID_1c363] = 595,
+	[BNXT_ULP_CLASS_HID_1e623] = 596,
+	[BNXT_ULP_CLASS_HID_b043] = 597,
+	[BNXT_ULP_CLASS_HID_b303] = 598,
+	[BNXT_ULP_CLASS_HID_f5c3] = 599,
+	[BNXT_ULP_CLASS_HID_f883] = 600,
+	[BNXT_ULP_CLASS_HID_abb7] = 601,
+	[BNXT_ULP_CLASS_HID_ae77] = 602,
+	[BNXT_ULP_CLASS_HID_f137] = 603,
+	[BNXT_ULP_CLASS_HID_f3f7] = 604,
+	[BNXT_ULP_CLASS_HID_1c1b7] = 605,
+	[BNXT_ULP_CLASS_HID_1e477] = 606,
+	[BNXT_ULP_CLASS_HID_1c737] = 607,
+	[BNXT_ULP_CLASS_HID_1e9f7] = 608,
+	[BNXT_ULP_CLASS_HID_1c643] = 609,
+	[BNXT_ULP_CLASS_HID_1e903] = 610,
+	[BNXT_ULP_CLASS_HID_1cbc3] = 611,
+	[BNXT_ULP_CLASS_HID_1ee83] = 612,
+	[BNXT_ULP_CLASS_HID_d3d7] = 613,
+	[BNXT_ULP_CLASS_HID_f697] = 614,
+	[BNXT_ULP_CLASS_HID_d957] = 615,
+	[BNXT_ULP_CLASS_HID_fc17] = 616,
+	[BNXT_ULP_CLASS_HID_cf1b] = 617,
+	[BNXT_ULP_CLASS_HID_f1db] = 618,
+	[BNXT_ULP_CLASS_HID_d49b] = 619,
+	[BNXT_ULP_CLASS_HID_f75b] = 620,
+	[BNXT_ULP_CLASS_HID_1884f] = 621,
+	[BNXT_ULP_CLASS_HID_1ab0f] = 622,
+	[BNXT_ULP_CLASS_HID_1cdcf] = 623,
+	[BNXT_ULP_CLASS_HID_1f08f] = 624,
+	[BNXT_ULP_CLASS_HID_18d1b] = 625,
+	[BNXT_ULP_CLASS_HID_1afdb] = 626,
+	[BNXT_ULP_CLASS_HID_1d29b] = 627,
+	[BNXT_ULP_CLASS_HID_1f55b] = 628,
+	[BNXT_ULP_CLASS_HID_9aef] = 629,
+	[BNXT_ULP_CLASS_HID_bdaf] = 630,
+	[BNXT_ULP_CLASS_HID_e06f] = 631,
+	[BNXT_ULP_CLASS_HID_e32f] = 632,
+	[BNXT_ULP_CLASS_HID_95d3] = 633,
+	[BNXT_ULP_CLASS_HID_b893] = 634,
+	[BNXT_ULP_CLASS_HID_db53] = 635,
+	[BNXT_ULP_CLASS_HID_fe13] = 636,
+	[BNXT_ULP_CLASS_HID_1abd3] = 637,
+	[BNXT_ULP_CLASS_HID_1ae93] = 638,
+	[BNXT_ULP_CLASS_HID_1f153] = 639,
+	[BNXT_ULP_CLASS_HID_1f413] = 640,
+	[BNXT_ULP_CLASS_HID_1b0ef] = 641,
+	[BNXT_ULP_CLASS_HID_1b3af] = 642,
+	[BNXT_ULP_CLASS_HID_1f66f] = 643,
+	[BNXT_ULP_CLASS_HID_1f92f] = 644,
+	[BNXT_ULP_CLASS_HID_be73] = 645,
+	[BNXT_ULP_CLASS_HID_e133] = 646,
+	[BNXT_ULP_CLASS_HID_c3f3] = 647,
+	[BNXT_ULP_CLASS_HID_e6b3] = 648,
+	[BNXT_ULP_CLASS_HID_b9a7] = 649,
+	[BNXT_ULP_CLASS_HID_bc67] = 650,
+	[BNXT_ULP_CLASS_HID_ff27] = 651,
+	[BNXT_ULP_CLASS_HID_e1e7] = 652,
+	[BNXT_ULP_CLASS_HID_1cfa7] = 653,
+	[BNXT_ULP_CLASS_HID_1f267] = 654,
+	[BNXT_ULP_CLASS_HID_1d527] = 655,
+	[BNXT_ULP_CLASS_HID_1f7e7] = 656,
+	[BNXT_ULP_CLASS_HID_1d473] = 657,
+	[BNXT_ULP_CLASS_HID_1f733] = 658,
+	[BNXT_ULP_CLASS_HID_1d9f3] = 659,
+	[BNXT_ULP_CLASS_HID_1fcb3] = 660,
+	[BNXT_ULP_CLASS_HID_aa07] = 661,
+	[BNXT_ULP_CLASS_HID_acc7] = 662,
+	[BNXT_ULP_CLASS_HID_ef87] = 663,
+	[BNXT_ULP_CLASS_HID_f247] = 664,
+	[BNXT_ULP_CLASS_HID_a54b] = 665,
+	[BNXT_ULP_CLASS_HID_a80b] = 666,
+	[BNXT_ULP_CLASS_HID_eacb] = 667,
+	[BNXT_ULP_CLASS_HID_ed8b] = 668,
+	[BNXT_ULP_CLASS_HID_1bb4b] = 669,
+	[BNXT_ULP_CLASS_HID_1be0b] = 670,
+	[BNXT_ULP_CLASS_HID_1c0cb] = 671,
+	[BNXT_ULP_CLASS_HID_1e38b] = 672,
+	[BNXT_ULP_CLASS_HID_1c007] = 673,
+	[BNXT_ULP_CLASS_HID_1e2c7] = 674,
+	[BNXT_ULP_CLASS_HID_1c587] = 675,
+	[BNXT_ULP_CLASS_HID_1e847] = 676,
+	[BNXT_ULP_CLASS_HID_cdeb] = 677,
+	[BNXT_ULP_CLASS_HID_f0ab] = 678,
+	[BNXT_ULP_CLASS_HID_d36b] = 679,
+	[BNXT_ULP_CLASS_HID_f62b] = 680,
+	[BNXT_ULP_CLASS_HID_c8df] = 681,
+	[BNXT_ULP_CLASS_HID_eb9f] = 682,
+	[BNXT_ULP_CLASS_HID_ce5f] = 683,
+	[BNXT_ULP_CLASS_HID_f11f] = 684,
+	[BNXT_ULP_CLASS_HID_18203] = 685,
+	[BNXT_ULP_CLASS_HID_1a4c3] = 686,
+	[BNXT_ULP_CLASS_HID_1c783] = 687,
+	[BNXT_ULP_CLASS_HID_1ea43] = 688,
+	[BNXT_ULP_CLASS_HID_186df] = 689,
+	[BNXT_ULP_CLASS_HID_1a99f] = 690,
+	[BNXT_ULP_CLASS_HID_1cc5f] = 691,
+	[BNXT_ULP_CLASS_HID_1ef1f] = 692,
+	[BNXT_ULP_CLASS_HID_94a3] = 693,
+	[BNXT_ULP_CLASS_HID_b763] = 694,
+	[BNXT_ULP_CLASS_HID_da23] = 695,
+	[BNXT_ULP_CLASS_HID_fce3] = 696,
+	[BNXT_ULP_CLASS_HID_8f97] = 697,
+	[BNXT_ULP_CLASS_HID_b257] = 698,
+	[BNXT_ULP_CLASS_HID_d517] = 699,
+	[BNXT_ULP_CLASS_HID_f7d7] = 700,
+	[BNXT_ULP_CLASS_HID_1a597] = 701,
+	[BNXT_ULP_CLASS_HID_1a857] = 702,
+	[BNXT_ULP_CLASS_HID_1eb17] = 703,
+	[BNXT_ULP_CLASS_HID_1edd7] = 704,
+	[BNXT_ULP_CLASS_HID_1aaa3] = 705,
+	[BNXT_ULP_CLASS_HID_1ad63] = 706,
+	[BNXT_ULP_CLASS_HID_1f023] = 707,
+	[BNXT_ULP_CLASS_HID_1f2e3] = 708,
+	[BNXT_ULP_CLASS_HID_b837] = 709,
+	[BNXT_ULP_CLASS_HID_baf7] = 710,
+	[BNXT_ULP_CLASS_HID_fdb7] = 711,
+	[BNXT_ULP_CLASS_HID_e077] = 712,
+	[BNXT_ULP_CLASS_HID_b37b] = 713,
+	[BNXT_ULP_CLASS_HID_b63b] = 714,
+	[BNXT_ULP_CLASS_HID_f8fb] = 715,
+	[BNXT_ULP_CLASS_HID_fbbb] = 716,
+	[BNXT_ULP_CLASS_HID_1c97b] = 717,
+	[BNXT_ULP_CLASS_HID_1ec3b] = 718,
+	[BNXT_ULP_CLASS_HID_1cefb] = 719,
+	[BNXT_ULP_CLASS_HID_1f1bb] = 720,
+	[BNXT_ULP_CLASS_HID_1ce37] = 721,
+	[BNXT_ULP_CLASS_HID_1f0f7] = 722,
+	[BNXT_ULP_CLASS_HID_1d3b7] = 723,
+	[BNXT_ULP_CLASS_HID_1f677] = 724,
+	[BNXT_ULP_CLASS_HID_a3db] = 725,
+	[BNXT_ULP_CLASS_HID_a69b] = 726,
+	[BNXT_ULP_CLASS_HID_e95b] = 727,
+	[BNXT_ULP_CLASS_HID_ec1b] = 728,
+	[BNXT_ULP_CLASS_HID_9f0f] = 729,
+	[BNXT_ULP_CLASS_HID_a1cf] = 730,
+	[BNXT_ULP_CLASS_HID_e48f] = 731,
+	[BNXT_ULP_CLASS_HID_e74f] = 732,
+	[BNXT_ULP_CLASS_HID_1b50f] = 733,
+	[BNXT_ULP_CLASS_HID_1b7cf] = 734,
+	[BNXT_ULP_CLASS_HID_1fa8f] = 735,
+	[BNXT_ULP_CLASS_HID_1fd4f] = 736,
+	[BNXT_ULP_CLASS_HID_1b9db] = 737,
+	[BNXT_ULP_CLASS_HID_1bc9b] = 738,
+	[BNXT_ULP_CLASS_HID_1ff5b] = 739,
+	[BNXT_ULP_CLASS_HID_1e21b] = 740,
+	[BNXT_ULP_CLASS_HID_c7af] = 741,
+	[BNXT_ULP_CLASS_HID_ea6f] = 742,
+	[BNXT_ULP_CLASS_HID_cd2f] = 743,
+	[BNXT_ULP_CLASS_HID_efef] = 744,
+	[BNXT_ULP_CLASS_HID_c293] = 745,
+	[BNXT_ULP_CLASS_HID_e553] = 746,
+	[BNXT_ULP_CLASS_HID_c813] = 747,
+	[BNXT_ULP_CLASS_HID_ead3] = 748,
+	[BNXT_ULP_CLASS_HID_1d893] = 749,
+	[BNXT_ULP_CLASS_HID_1fb53] = 750,
+	[BNXT_ULP_CLASS_HID_1c147] = 751,
+	[BNXT_ULP_CLASS_HID_1e407] = 752,
+	[BNXT_ULP_CLASS_HID_18093] = 753,
+	[BNXT_ULP_CLASS_HID_1a353] = 754,
+	[BNXT_ULP_CLASS_HID_1c613] = 755,
+	[BNXT_ULP_CLASS_HID_1e8d3] = 756,
+	[BNXT_ULP_CLASS_HID_8e67] = 757,
+	[BNXT_ULP_CLASS_HID_b127] = 758,
+	[BNXT_ULP_CLASS_HID_d3e7] = 759,
+	[BNXT_ULP_CLASS_HID_f6a7] = 760,
+	[BNXT_ULP_CLASS_HID_89ab] = 761,
+	[BNXT_ULP_CLASS_HID_ac6b] = 762,
+	[BNXT_ULP_CLASS_HID_cf2b] = 763,
+	[BNXT_ULP_CLASS_HID_f1eb] = 764,
+	[BNXT_ULP_CLASS_HID_19fab] = 765,
+	[BNXT_ULP_CLASS_HID_1a26b] = 766,
+	[BNXT_ULP_CLASS_HID_1e52b] = 767,
+	[BNXT_ULP_CLASS_HID_1e7eb] = 768,
+	[BNXT_ULP_CLASS_HID_1a467] = 769,
+	[BNXT_ULP_CLASS_HID_1a727] = 770,
+	[BNXT_ULP_CLASS_HID_1e9e7] = 771,
+	[BNXT_ULP_CLASS_HID_1eca7] = 772,
+	[BNXT_ULP_CLASS_HID_b1cb] = 773,
+	[BNXT_ULP_CLASS_HID_b48b] = 774,
+	[BNXT_ULP_CLASS_HID_f74b] = 775,
+	[BNXT_ULP_CLASS_HID_fa0b] = 776,
+	[BNXT_ULP_CLASS_HID_ad3f] = 777,
+	[BNXT_ULP_CLASS_HID_afff] = 778,
+	[BNXT_ULP_CLASS_HID_f2bf] = 779,
+	[BNXT_ULP_CLASS_HID_f57f] = 780,
+	[BNXT_ULP_CLASS_HID_1c33f] = 781,
+	[BNXT_ULP_CLASS_HID_1e5ff] = 782,
+	[BNXT_ULP_CLASS_HID_1c8bf] = 783,
+	[BNXT_ULP_CLASS_HID_1eb7f] = 784,
+	[BNXT_ULP_CLASS_HID_1c7cb] = 785,
+	[BNXT_ULP_CLASS_HID_1ea8b] = 786,
+	[BNXT_ULP_CLASS_HID_1cd4b] = 787,
+	[BNXT_ULP_CLASS_HID_1f00b] = 788,
+	[BNXT_ULP_CLASS_HID_9117] = 789,
+	[BNXT_ULP_CLASS_HID_b3d7] = 790,
+	[BNXT_ULP_CLASS_HID_d697] = 791,
+	[BNXT_ULP_CLASS_HID_f957] = 792,
+	[BNXT_ULP_CLASS_HID_8c5b] = 793,
+	[BNXT_ULP_CLASS_HID_af1b] = 794,
+	[BNXT_ULP_CLASS_HID_d1db] = 795,
+	[BNXT_ULP_CLASS_HID_f49b] = 796,
+	[BNXT_ULP_CLASS_HID_1a25b] = 797,
+	[BNXT_ULP_CLASS_HID_1a51b] = 798,
+	[BNXT_ULP_CLASS_HID_1e7db] = 799,
+	[BNXT_ULP_CLASS_HID_1ea9b] = 800,
+	[BNXT_ULP_CLASS_HID_1a717] = 801,
+	[BNXT_ULP_CLASS_HID_1a9d7] = 802,
+	[BNXT_ULP_CLASS_HID_1ec97] = 803,
+	[BNXT_ULP_CLASS_HID_1ef57] = 804,
+	[BNXT_ULP_CLASS_HID_b4fb] = 805,
+	[BNXT_ULP_CLASS_HID_b7bb] = 806,
+	[BNXT_ULP_CLASS_HID_fa7b] = 807,
+	[BNXT_ULP_CLASS_HID_fd3b] = 808,
+	[BNXT_ULP_CLASS_HID_b02f] = 809,
+	[BNXT_ULP_CLASS_HID_b2ef] = 810,
+	[BNXT_ULP_CLASS_HID_f5af] = 811,
+	[BNXT_ULP_CLASS_HID_f86f] = 812,
+	[BNXT_ULP_CLASS_HID_1c62f] = 813,
+	[BNXT_ULP_CLASS_HID_1e8ef] = 814,
+	[BNXT_ULP_CLASS_HID_1cbaf] = 815,
+	[BNXT_ULP_CLASS_HID_1ee6f] = 816,
+	[BNXT_ULP_CLASS_HID_1cafb] = 817,
+	[BNXT_ULP_CLASS_HID_1edbb] = 818,
+	[BNXT_ULP_CLASS_HID_1d07b] = 819,
+	[BNXT_ULP_CLASS_HID_1f33b] = 820,
+	[BNXT_ULP_CLASS_HID_8b2b] = 821,
+	[BNXT_ULP_CLASS_HID_adeb] = 822,
+	[BNXT_ULP_CLASS_HID_d0ab] = 823,
+	[BNXT_ULP_CLASS_HID_f36b] = 824,
+	[BNXT_ULP_CLASS_HID_861f] = 825,
+	[BNXT_ULP_CLASS_HID_a8df] = 826,
+	[BNXT_ULP_CLASS_HID_cb9f] = 827,
+	[BNXT_ULP_CLASS_HID_ee5f] = 828,
+	[BNXT_ULP_CLASS_HID_19c1f] = 829,
+	[BNXT_ULP_CLASS_HID_1bedf] = 830,
+	[BNXT_ULP_CLASS_HID_1e19f] = 831,
+	[BNXT_ULP_CLASS_HID_1e45f] = 832,
+	[BNXT_ULP_CLASS_HID_1a12b] = 833,
+	[BNXT_ULP_CLASS_HID_1a3eb] = 834,
+	[BNXT_ULP_CLASS_HID_1e6ab] = 835,
+	[BNXT_ULP_CLASS_HID_1e96b] = 836,
+	[BNXT_ULP_CLASS_HID_aebf] = 837,
+	[BNXT_ULP_CLASS_HID_b17f] = 838,
+	[BNXT_ULP_CLASS_HID_f43f] = 839,
+	[BNXT_ULP_CLASS_HID_f6ff] = 840,
+	[BNXT_ULP_CLASS_HID_a9e3] = 841,
+	[BNXT_ULP_CLASS_HID_aca3] = 842,
+	[BNXT_ULP_CLASS_HID_ef63] = 843,
+	[BNXT_ULP_CLASS_HID_f223] = 844,
+	[BNXT_ULP_CLASS_HID_1bfe3] = 845,
+	[BNXT_ULP_CLASS_HID_1e2a3] = 846,
+	[BNXT_ULP_CLASS_HID_1c563] = 847,
+	[BNXT_ULP_CLASS_HID_1e823] = 848,
+	[BNXT_ULP_CLASS_HID_1c4bf] = 849,
+	[BNXT_ULP_CLASS_HID_1e77f] = 850,
+	[BNXT_ULP_CLASS_HID_1ca3f] = 851,
+	[BNXT_ULP_CLASS_HID_1ecff] = 852,
+	[BNXT_ULP_CLASS_HID_2543] = 853,
+	[BNXT_ULP_CLASS_HID_2b8f] = 854,
+	[BNXT_ULP_CLASS_HID_4f13] = 855,
+	[BNXT_ULP_CLASS_HID_162b] = 856,
+	[BNXT_ULP_CLASS_HID_39bf] = 857,
+	[BNXT_ULP_CLASS_HID_48d7] = 858,
+	[BNXT_ULP_CLASS_HID_0fef] = 859,
+	[BNXT_ULP_CLASS_HID_3373] = 860,
+	[BNXT_ULP_CLASS_HID_b6ef] = 861,
+	[BNXT_ULP_CLASS_HID_b92f] = 862,
+	[BNXT_ULP_CLASS_HID_fc6f] = 863,
+	[BNXT_ULP_CLASS_HID_feaf] = 864,
+	[BNXT_ULP_CLASS_HID_b193] = 865,
+	[BNXT_ULP_CLASS_HID_b4d3] = 866,
+	[BNXT_ULP_CLASS_HID_f713] = 867,
+	[BNXT_ULP_CLASS_HID_fa53] = 868,
+	[BNXT_ULP_CLASS_HID_1c793] = 869,
+	[BNXT_ULP_CLASS_HID_1ead3] = 870,
+	[BNXT_ULP_CLASS_HID_1cd13] = 871,
+	[BNXT_ULP_CLASS_HID_1f053] = 872,
+	[BNXT_ULP_CLASS_HID_1ccef] = 873,
+	[BNXT_ULP_CLASS_HID_1ef2f] = 874,
+	[BNXT_ULP_CLASS_HID_1d26f] = 875,
+	[BNXT_ULP_CLASS_HID_1f4af] = 876,
+	[BNXT_ULP_CLASS_HID_da73] = 877,
+	[BNXT_ULP_CLASS_HID_a067] = 878,
+	[BNXT_ULP_CLASS_HID_c2a7] = 879,
+	[BNXT_ULP_CLASS_HID_e5e7] = 880,
+	[BNXT_ULP_CLASS_HID_d527] = 881,
+	[BNXT_ULP_CLASS_HID_f867] = 882,
+	[BNXT_ULP_CLASS_HID_daa7] = 883,
+	[BNXT_ULP_CLASS_HID_e0ab] = 884,
+	[BNXT_ULP_CLASS_HID_18eeb] = 885,
+	[BNXT_ULP_CLASS_HID_1b12b] = 886,
+	[BNXT_ULP_CLASS_HID_1d46b] = 887,
+	[BNXT_ULP_CLASS_HID_1f6ab] = 888,
+	[BNXT_ULP_CLASS_HID_19327] = 889,
+	[BNXT_ULP_CLASS_HID_1b667] = 890,
+	[BNXT_ULP_CLASS_HID_1d8a7] = 891,
+	[BNXT_ULP_CLASS_HID_1fbe7] = 892,
+	[BNXT_ULP_CLASS_HID_a14b] = 893,
+	[BNXT_ULP_CLASS_HID_a38b] = 894,
+	[BNXT_ULP_CLASS_HID_e6cb] = 895,
+	[BNXT_ULP_CLASS_HID_e90b] = 896,
+	[BNXT_ULP_CLASS_HID_9c7f] = 897,
+	[BNXT_ULP_CLASS_HID_bebf] = 898,
+	[BNXT_ULP_CLASS_HID_e1ff] = 899,
+	[BNXT_ULP_CLASS_HID_e43f] = 900,
+	[BNXT_ULP_CLASS_HID_1b27f] = 901,
+	[BNXT_ULP_CLASS_HID_1b4bf] = 902,
+	[BNXT_ULP_CLASS_HID_1f7ff] = 903,
+	[BNXT_ULP_CLASS_HID_1fa3f] = 904,
+	[BNXT_ULP_CLASS_HID_1b74b] = 905,
+	[BNXT_ULP_CLASS_HID_1b98b] = 906,
+	[BNXT_ULP_CLASS_HID_1fccb] = 907,
+	[BNXT_ULP_CLASS_HID_1ff0b] = 908,
+	[BNXT_ULP_CLASS_HID_c4df] = 909,
+	[BNXT_ULP_CLASS_HID_e71f] = 910,
+	[BNXT_ULP_CLASS_HID_ca5f] = 911,
+	[BNXT_ULP_CLASS_HID_ec9f] = 912,
+	[BNXT_ULP_CLASS_HID_bf83] = 913,
+	[BNXT_ULP_CLASS_HID_e2c3] = 914,
+	[BNXT_ULP_CLASS_HID_c503] = 915,
+	[BNXT_ULP_CLASS_HID_e843] = 916,
+	[BNXT_ULP_CLASS_HID_1d583] = 917,
+	[BNXT_ULP_CLASS_HID_1f8c3] = 918,
+	[BNXT_ULP_CLASS_HID_1db03] = 919,
+	[BNXT_ULP_CLASS_HID_1e177] = 920,
+	[BNXT_ULP_CLASS_HID_1dadf] = 921,
+	[BNXT_ULP_CLASS_HID_1a0c3] = 922,
+	[BNXT_ULP_CLASS_HID_1c303] = 923,
+	[BNXT_ULP_CLASS_HID_1e643] = 924,
+	[BNXT_ULP_CLASS_HID_b023] = 925,
+	[BNXT_ULP_CLASS_HID_b363] = 926,
+	[BNXT_ULP_CLASS_HID_f5a3] = 927,
+	[BNXT_ULP_CLASS_HID_f8e3] = 928,
+	[BNXT_ULP_CLASS_HID_abd7] = 929,
+	[BNXT_ULP_CLASS_HID_ae17] = 930,
+	[BNXT_ULP_CLASS_HID_f157] = 931,
+	[BNXT_ULP_CLASS_HID_f397] = 932,
+	[BNXT_ULP_CLASS_HID_1c1d7] = 933,
+	[BNXT_ULP_CLASS_HID_1e417] = 934,
+	[BNXT_ULP_CLASS_HID_1c757] = 935,
+	[BNXT_ULP_CLASS_HID_1e997] = 936,
+	[BNXT_ULP_CLASS_HID_1c623] = 937,
+	[BNXT_ULP_CLASS_HID_1e963] = 938,
+	[BNXT_ULP_CLASS_HID_1cba3] = 939,
+	[BNXT_ULP_CLASS_HID_1eee3] = 940,
+	[BNXT_ULP_CLASS_HID_d3b7] = 941,
+	[BNXT_ULP_CLASS_HID_f6f7] = 942,
+	[BNXT_ULP_CLASS_HID_d937] = 943,
+	[BNXT_ULP_CLASS_HID_fc77] = 944,
+	[BNXT_ULP_CLASS_HID_cf7b] = 945,
+	[BNXT_ULP_CLASS_HID_f1bb] = 946,
+	[BNXT_ULP_CLASS_HID_d4fb] = 947,
+	[BNXT_ULP_CLASS_HID_f73b] = 948,
+	[BNXT_ULP_CLASS_HID_1882f] = 949,
+	[BNXT_ULP_CLASS_HID_1ab6f] = 950,
+	[BNXT_ULP_CLASS_HID_1cdaf] = 951,
+	[BNXT_ULP_CLASS_HID_1f0ef] = 952,
+	[BNXT_ULP_CLASS_HID_18d7b] = 953,
+	[BNXT_ULP_CLASS_HID_1afbb] = 954,
+	[BNXT_ULP_CLASS_HID_1d2fb] = 955,
+	[BNXT_ULP_CLASS_HID_1f53b] = 956,
+	[BNXT_ULP_CLASS_HID_9a8f] = 957,
+	[BNXT_ULP_CLASS_HID_bdcf] = 958,
+	[BNXT_ULP_CLASS_HID_e00f] = 959,
+	[BNXT_ULP_CLASS_HID_e34f] = 960,
+	[BNXT_ULP_CLASS_HID_95b3] = 961,
+	[BNXT_ULP_CLASS_HID_b8f3] = 962,
+	[BNXT_ULP_CLASS_HID_db33] = 963,
+	[BNXT_ULP_CLASS_HID_fe73] = 964,
+	[BNXT_ULP_CLASS_HID_1abb3] = 965,
+	[BNXT_ULP_CLASS_HID_1aef3] = 966,
+	[BNXT_ULP_CLASS_HID_1f133] = 967,
+	[BNXT_ULP_CLASS_HID_1f473] = 968,
+	[BNXT_ULP_CLASS_HID_1b08f] = 969,
+	[BNXT_ULP_CLASS_HID_1b3cf] = 970,
+	[BNXT_ULP_CLASS_HID_1f60f] = 971,
+	[BNXT_ULP_CLASS_HID_1f94f] = 972,
+	[BNXT_ULP_CLASS_HID_be13] = 973,
+	[BNXT_ULP_CLASS_HID_e153] = 974,
+	[BNXT_ULP_CLASS_HID_c393] = 975,
+	[BNXT_ULP_CLASS_HID_e6d3] = 976,
+	[BNXT_ULP_CLASS_HID_b9c7] = 977,
+	[BNXT_ULP_CLASS_HID_bc07] = 978,
+	[BNXT_ULP_CLASS_HID_ff47] = 979,
+	[BNXT_ULP_CLASS_HID_e187] = 980,
+	[BNXT_ULP_CLASS_HID_1cfc7] = 981,
+	[BNXT_ULP_CLASS_HID_1f207] = 982,
+	[BNXT_ULP_CLASS_HID_1d547] = 983,
+	[BNXT_ULP_CLASS_HID_1f787] = 984,
+	[BNXT_ULP_CLASS_HID_1d413] = 985,
+	[BNXT_ULP_CLASS_HID_1f753] = 986,
+	[BNXT_ULP_CLASS_HID_1d993] = 987,
+	[BNXT_ULP_CLASS_HID_1fcd3] = 988,
+	[BNXT_ULP_CLASS_HID_aa67] = 989,
+	[BNXT_ULP_CLASS_HID_aca7] = 990,
+	[BNXT_ULP_CLASS_HID_efe7] = 991,
+	[BNXT_ULP_CLASS_HID_f227] = 992,
+	[BNXT_ULP_CLASS_HID_a52b] = 993,
+	[BNXT_ULP_CLASS_HID_a86b] = 994,
+	[BNXT_ULP_CLASS_HID_eaab] = 995,
+	[BNXT_ULP_CLASS_HID_edeb] = 996,
+	[BNXT_ULP_CLASS_HID_1bb2b] = 997,
+	[BNXT_ULP_CLASS_HID_1be6b] = 998,
+	[BNXT_ULP_CLASS_HID_1c0ab] = 999,
+	[BNXT_ULP_CLASS_HID_1e3eb] = 1000,
+	[BNXT_ULP_CLASS_HID_1c067] = 1001,
+	[BNXT_ULP_CLASS_HID_1e2a7] = 1002,
+	[BNXT_ULP_CLASS_HID_1c5e7] = 1003,
+	[BNXT_ULP_CLASS_HID_1e827] = 1004,
+	[BNXT_ULP_CLASS_HID_cd8b] = 1005,
+	[BNXT_ULP_CLASS_HID_f0cb] = 1006,
+	[BNXT_ULP_CLASS_HID_d30b] = 1007,
+	[BNXT_ULP_CLASS_HID_f64b] = 1008,
+	[BNXT_ULP_CLASS_HID_c8bf] = 1009,
+	[BNXT_ULP_CLASS_HID_ebff] = 1010,
+	[BNXT_ULP_CLASS_HID_ce3f] = 1011,
+	[BNXT_ULP_CLASS_HID_f17f] = 1012,
+	[BNXT_ULP_CLASS_HID_18263] = 1013,
+	[BNXT_ULP_CLASS_HID_1a4a3] = 1014,
+	[BNXT_ULP_CLASS_HID_1c7e3] = 1015,
+	[BNXT_ULP_CLASS_HID_1ea23] = 1016,
+	[BNXT_ULP_CLASS_HID_186bf] = 1017,
+	[BNXT_ULP_CLASS_HID_1a9ff] = 1018,
+	[BNXT_ULP_CLASS_HID_1cc3f] = 1019,
+	[BNXT_ULP_CLASS_HID_1ef7f] = 1020,
+	[BNXT_ULP_CLASS_HID_94c3] = 1021,
+	[BNXT_ULP_CLASS_HID_b703] = 1022,
+	[BNXT_ULP_CLASS_HID_da43] = 1023,
+	[BNXT_ULP_CLASS_HID_fc83] = 1024,
+	[BNXT_ULP_CLASS_HID_8ff7] = 1025,
+	[BNXT_ULP_CLASS_HID_b237] = 1026,
+	[BNXT_ULP_CLASS_HID_d577] = 1027,
+	[BNXT_ULP_CLASS_HID_f7b7] = 1028,
+	[BNXT_ULP_CLASS_HID_1a5f7] = 1029,
+	[BNXT_ULP_CLASS_HID_1a837] = 1030,
+	[BNXT_ULP_CLASS_HID_1eb77] = 1031,
+	[BNXT_ULP_CLASS_HID_1edb7] = 1032,
+	[BNXT_ULP_CLASS_HID_1aac3] = 1033,
+	[BNXT_ULP_CLASS_HID_1ad03] = 1034,
+	[BNXT_ULP_CLASS_HID_1f043] = 1035,
+	[BNXT_ULP_CLASS_HID_1f283] = 1036,
+	[BNXT_ULP_CLASS_HID_b857] = 1037,
+	[BNXT_ULP_CLASS_HID_ba97] = 1038,
+	[BNXT_ULP_CLASS_HID_fdd7] = 1039,
+	[BNXT_ULP_CLASS_HID_e017] = 1040,
+	[BNXT_ULP_CLASS_HID_b31b] = 1041,
+	[BNXT_ULP_CLASS_HID_b65b] = 1042,
+	[BNXT_ULP_CLASS_HID_f89b] = 1043,
+	[BNXT_ULP_CLASS_HID_fbdb] = 1044,
+	[BNXT_ULP_CLASS_HID_1c91b] = 1045,
+	[BNXT_ULP_CLASS_HID_1ec5b] = 1046,
+	[BNXT_ULP_CLASS_HID_1ce9b] = 1047,
+	[BNXT_ULP_CLASS_HID_1f1db] = 1048,
+	[BNXT_ULP_CLASS_HID_1ce57] = 1049,
+	[BNXT_ULP_CLASS_HID_1f097] = 1050,
+	[BNXT_ULP_CLASS_HID_1d3d7] = 1051,
+	[BNXT_ULP_CLASS_HID_1f617] = 1052,
+	[BNXT_ULP_CLASS_HID_a3bb] = 1053,
+	[BNXT_ULP_CLASS_HID_a6fb] = 1054,
+	[BNXT_ULP_CLASS_HID_e93b] = 1055,
+	[BNXT_ULP_CLASS_HID_ec7b] = 1056,
+	[BNXT_ULP_CLASS_HID_9f6f] = 1057,
+	[BNXT_ULP_CLASS_HID_a1af] = 1058,
+	[BNXT_ULP_CLASS_HID_e4ef] = 1059,
+	[BNXT_ULP_CLASS_HID_e72f] = 1060,
+	[BNXT_ULP_CLASS_HID_1b56f] = 1061,
+	[BNXT_ULP_CLASS_HID_1b7af] = 1062,
+	[BNXT_ULP_CLASS_HID_1faef] = 1063,
+	[BNXT_ULP_CLASS_HID_1fd2f] = 1064,
+	[BNXT_ULP_CLASS_HID_1b9bb] = 1065,
+	[BNXT_ULP_CLASS_HID_1bcfb] = 1066,
+	[BNXT_ULP_CLASS_HID_1ff3b] = 1067,
+	[BNXT_ULP_CLASS_HID_1e27b] = 1068,
+	[BNXT_ULP_CLASS_HID_c7cf] = 1069,
+	[BNXT_ULP_CLASS_HID_ea0f] = 1070,
+	[BNXT_ULP_CLASS_HID_cd4f] = 1071,
+	[BNXT_ULP_CLASS_HID_ef8f] = 1072,
+	[BNXT_ULP_CLASS_HID_c2f3] = 1073,
+	[BNXT_ULP_CLASS_HID_e533] = 1074,
+	[BNXT_ULP_CLASS_HID_c873] = 1075,
+	[BNXT_ULP_CLASS_HID_eab3] = 1076,
+	[BNXT_ULP_CLASS_HID_1d8f3] = 1077,
+	[BNXT_ULP_CLASS_HID_1fb33] = 1078,
+	[BNXT_ULP_CLASS_HID_1c127] = 1079,
+	[BNXT_ULP_CLASS_HID_1e467] = 1080,
+	[BNXT_ULP_CLASS_HID_180f3] = 1081,
+	[BNXT_ULP_CLASS_HID_1a333] = 1082,
+	[BNXT_ULP_CLASS_HID_1c673] = 1083,
+	[BNXT_ULP_CLASS_HID_1e8b3] = 1084,
+	[BNXT_ULP_CLASS_HID_8e07] = 1085,
+	[BNXT_ULP_CLASS_HID_b147] = 1086,
+	[BNXT_ULP_CLASS_HID_d387] = 1087,
+	[BNXT_ULP_CLASS_HID_f6c7] = 1088,
+	[BNXT_ULP_CLASS_HID_89cb] = 1089,
+	[BNXT_ULP_CLASS_HID_ac0b] = 1090,
+	[BNXT_ULP_CLASS_HID_cf4b] = 1091,
+	[BNXT_ULP_CLASS_HID_f18b] = 1092,
+	[BNXT_ULP_CLASS_HID_19fcb] = 1093,
+	[BNXT_ULP_CLASS_HID_1a20b] = 1094,
+	[BNXT_ULP_CLASS_HID_1e54b] = 1095,
+	[BNXT_ULP_CLASS_HID_1e78b] = 1096,
+	[BNXT_ULP_CLASS_HID_1a407] = 1097,
+	[BNXT_ULP_CLASS_HID_1a747] = 1098,
+	[BNXT_ULP_CLASS_HID_1e987] = 1099,
+	[BNXT_ULP_CLASS_HID_1ecc7] = 1100,
+	[BNXT_ULP_CLASS_HID_b1ab] = 1101,
+	[BNXT_ULP_CLASS_HID_b4eb] = 1102,
+	[BNXT_ULP_CLASS_HID_f72b] = 1103,
+	[BNXT_ULP_CLASS_HID_fa6b] = 1104,
+	[BNXT_ULP_CLASS_HID_ad5f] = 1105,
+	[BNXT_ULP_CLASS_HID_af9f] = 1106,
+	[BNXT_ULP_CLASS_HID_f2df] = 1107,
+	[BNXT_ULP_CLASS_HID_f51f] = 1108,
+	[BNXT_ULP_CLASS_HID_1c35f] = 1109,
+	[BNXT_ULP_CLASS_HID_1e59f] = 1110,
+	[BNXT_ULP_CLASS_HID_1c8df] = 1111,
+	[BNXT_ULP_CLASS_HID_1eb1f] = 1112,
+	[BNXT_ULP_CLASS_HID_1c7ab] = 1113,
+	[BNXT_ULP_CLASS_HID_1eaeb] = 1114,
+	[BNXT_ULP_CLASS_HID_1cd2b] = 1115,
+	[BNXT_ULP_CLASS_HID_1f06b] = 1116,
+	[BNXT_ULP_CLASS_HID_9177] = 1117,
+	[BNXT_ULP_CLASS_HID_b3b7] = 1118,
+	[BNXT_ULP_CLASS_HID_d6f7] = 1119,
+	[BNXT_ULP_CLASS_HID_f937] = 1120,
+	[BNXT_ULP_CLASS_HID_8c3b] = 1121,
+	[BNXT_ULP_CLASS_HID_af7b] = 1122,
+	[BNXT_ULP_CLASS_HID_d1bb] = 1123,
+	[BNXT_ULP_CLASS_HID_f4fb] = 1124,
+	[BNXT_ULP_CLASS_HID_1a23b] = 1125,
+	[BNXT_ULP_CLASS_HID_1a57b] = 1126,
+	[BNXT_ULP_CLASS_HID_1e7bb] = 1127,
+	[BNXT_ULP_CLASS_HID_1eafb] = 1128,
+	[BNXT_ULP_CLASS_HID_1a777] = 1129,
+	[BNXT_ULP_CLASS_HID_1a9b7] = 1130,
+	[BNXT_ULP_CLASS_HID_1ecf7] = 1131,
+	[BNXT_ULP_CLASS_HID_1ef37] = 1132,
+	[BNXT_ULP_CLASS_HID_b49b] = 1133,
+	[BNXT_ULP_CLASS_HID_b7db] = 1134,
+	[BNXT_ULP_CLASS_HID_fa1b] = 1135,
+	[BNXT_ULP_CLASS_HID_fd5b] = 1136,
+	[BNXT_ULP_CLASS_HID_b04f] = 1137,
+	[BNXT_ULP_CLASS_HID_b28f] = 1138,
+	[BNXT_ULP_CLASS_HID_f5cf] = 1139,
+	[BNXT_ULP_CLASS_HID_f80f] = 1140,
+	[BNXT_ULP_CLASS_HID_1c64f] = 1141,
+	[BNXT_ULP_CLASS_HID_1e88f] = 1142,
+	[BNXT_ULP_CLASS_HID_1cbcf] = 1143,
+	[BNXT_ULP_CLASS_HID_1ee0f] = 1144,
+	[BNXT_ULP_CLASS_HID_1ca9b] = 1145,
+	[BNXT_ULP_CLASS_HID_1eddb] = 1146,
+	[BNXT_ULP_CLASS_HID_1d01b] = 1147,
+	[BNXT_ULP_CLASS_HID_1f35b] = 1148,
+	[BNXT_ULP_CLASS_HID_8b4b] = 1149,
+	[BNXT_ULP_CLASS_HID_ad8b] = 1150,
+	[BNXT_ULP_CLASS_HID_d0cb] = 1151,
+	[BNXT_ULP_CLASS_HID_f30b] = 1152,
+	[BNXT_ULP_CLASS_HID_867f] = 1153,
+	[BNXT_ULP_CLASS_HID_a8bf] = 1154,
+	[BNXT_ULP_CLASS_HID_cbff] = 1155,
+	[BNXT_ULP_CLASS_HID_ee3f] = 1156,
+	[BNXT_ULP_CLASS_HID_19c7f] = 1157,
+	[BNXT_ULP_CLASS_HID_1bebf] = 1158,
+	[BNXT_ULP_CLASS_HID_1e1ff] = 1159,
+	[BNXT_ULP_CLASS_HID_1e43f] = 1160,
+	[BNXT_ULP_CLASS_HID_1a14b] = 1161,
+	[BNXT_ULP_CLASS_HID_1a38b] = 1162,
+	[BNXT_ULP_CLASS_HID_1e6cb] = 1163,
+	[BNXT_ULP_CLASS_HID_1e90b] = 1164,
+	[BNXT_ULP_CLASS_HID_aedf] = 1165,
+	[BNXT_ULP_CLASS_HID_b11f] = 1166,
+	[BNXT_ULP_CLASS_HID_f45f] = 1167,
+	[BNXT_ULP_CLASS_HID_f69f] = 1168,
+	[BNXT_ULP_CLASS_HID_a983] = 1169,
+	[BNXT_ULP_CLASS_HID_acc3] = 1170,
+	[BNXT_ULP_CLASS_HID_ef03] = 1171,
+	[BNXT_ULP_CLASS_HID_f243] = 1172,
+	[BNXT_ULP_CLASS_HID_1bf83] = 1173,
+	[BNXT_ULP_CLASS_HID_1e2c3] = 1174,
+	[BNXT_ULP_CLASS_HID_1c503] = 1175,
+	[BNXT_ULP_CLASS_HID_1e843] = 1176,
+	[BNXT_ULP_CLASS_HID_1c4df] = 1177,
+	[BNXT_ULP_CLASS_HID_1e71f] = 1178,
+	[BNXT_ULP_CLASS_HID_1ca5f] = 1179,
+	[BNXT_ULP_CLASS_HID_1ec9f] = 1180,
+	[BNXT_ULP_CLASS_HID_2523] = 1181,
+	[BNXT_ULP_CLASS_HID_2bef] = 1182,
+	[BNXT_ULP_CLASS_HID_4f73] = 1183,
+	[BNXT_ULP_CLASS_HID_164b] = 1184,
+	[BNXT_ULP_CLASS_HID_39df] = 1185,
+	[BNXT_ULP_CLASS_HID_48b7] = 1186,
+	[BNXT_ULP_CLASS_HID_0f8f] = 1187,
+	[BNXT_ULP_CLASS_HID_3313] = 1188,
+	[BNXT_ULP_CLASS_HID_257b7] = 1189,
+	[BNXT_ULP_CLASS_HID_24467] = 1190,
+	[BNXT_ULP_CLASS_HID_23fbb] = 1191,
+	[BNXT_ULP_CLASS_HID_252cb] = 1192,
+	[BNXT_ULP_CLASS_HID_21e7f] = 1193,
+	[BNXT_ULP_CLASS_HID_20b2f] = 1194,
+	[BNXT_ULP_CLASS_HID_20663] = 1195,
+	[BNXT_ULP_CLASS_HID_219b3] = 1196,
+	[BNXT_ULP_CLASS_HID_24213] = 1197,
+	[BNXT_ULP_CLASS_HID_22ec3] = 1198,
+	[BNXT_ULP_CLASS_HID_22a17] = 1199,
+	[BNXT_ULP_CLASS_HID_23d27] = 1200,
+	[BNXT_ULP_CLASS_HID_208db] = 1201,
+	[BNXT_ULP_CLASS_HID_25277] = 1202,
+	[BNXT_ULP_CLASS_HID_24d8b] = 1203,
+	[BNXT_ULP_CLASS_HID_203ef] = 1204,
+	[BNXT_ULP_CLASS_HID_2517b] = 1205,
+	[BNXT_ULP_CLASS_HID_23e2b] = 1206,
+	[BNXT_ULP_CLASS_HID_2397f] = 1207,
+	[BNXT_ULP_CLASS_HID_24c8f] = 1208,
+	[BNXT_ULP_CLASS_HID_21823] = 1209,
+	[BNXT_ULP_CLASS_HID_20513] = 1210,
+	[BNXT_ULP_CLASS_HID_20027] = 1211,
+	[BNXT_ULP_CLASS_HID_21377] = 1212,
+	[BNXT_ULP_CLASS_HID_23bd7] = 1213,
+	[BNXT_ULP_CLASS_HID_22887] = 1214,
+	[BNXT_ULP_CLASS_HID_223db] = 1215,
+	[BNXT_ULP_CLASS_HID_236eb] = 1216,
+	[BNXT_ULP_CLASS_HID_2029f] = 1217,
+	[BNXT_ULP_CLASS_HID_24c3b] = 1218,
+	[BNXT_ULP_CLASS_HID_2474f] = 1219,
+	[BNXT_ULP_CLASS_HID_25a9f] = 1220,
+	[BNXT_ULP_CLASS_HID_24b3f] = 1221,
+	[BNXT_ULP_CLASS_HID_237ef] = 1222,
+	[BNXT_ULP_CLASS_HID_23323] = 1223,
+	[BNXT_ULP_CLASS_HID_24673] = 1224,
+	[BNXT_ULP_CLASS_HID_211e7] = 1225,
+	[BNXT_ULP_CLASS_HID_25b83] = 1226,
+	[BNXT_ULP_CLASS_HID_256d7] = 1227,
+	[BNXT_ULP_CLASS_HID_20d3b] = 1228,
+	[BNXT_ULP_CLASS_HID_2359b] = 1229,
+	[BNXT_ULP_CLASS_HID_2224b] = 1230,
+	[BNXT_ULP_CLASS_HID_21d9f] = 1231,
+	[BNXT_ULP_CLASS_HID_230af] = 1232,
+	[BNXT_ULP_CLASS_HID_2590f] = 1233,
+	[BNXT_ULP_CLASS_HID_245ff] = 1234,
+	[BNXT_ULP_CLASS_HID_24133] = 1235,
+	[BNXT_ULP_CLASS_HID_25443] = 1236,
+	[BNXT_ULP_CLASS_HID_244e3] = 1237,
+	[BNXT_ULP_CLASS_HID_231d3] = 1238,
+	[BNXT_ULP_CLASS_HID_22ce7] = 1239,
+	[BNXT_ULP_CLASS_HID_24037] = 1240,
+	[BNXT_ULP_CLASS_HID_20bab] = 1241,
+	[BNXT_ULP_CLASS_HID_25547] = 1242,
+	[BNXT_ULP_CLASS_HID_2509b] = 1243,
+	[BNXT_ULP_CLASS_HID_206ff] = 1244,
+	[BNXT_ULP_CLASS_HID_22f5f] = 1245,
+	[BNXT_ULP_CLASS_HID_21c0f] = 1246,
+	[BNXT_ULP_CLASS_HID_21743] = 1247,
+	[BNXT_ULP_CLASS_HID_22a93] = 1248,
+	[BNXT_ULP_CLASS_HID_252f3] = 1249,
+	[BNXT_ULP_CLASS_HID_23fa3] = 1250,
+	[BNXT_ULP_CLASS_HID_23af7] = 1251,
+	[BNXT_ULP_CLASS_HID_24e07] = 1252,
+	[BNXT_ULP_CLASS_HID_2322f] = 1253,
+	[BNXT_ULP_CLASS_HID_21f1f] = 1254,
+	[BNXT_ULP_CLASS_HID_21a53] = 1255,
+	[BNXT_ULP_CLASS_HID_22d63] = 1256,
+	[BNXT_ULP_CLASS_HID_255c3] = 1257,
+	[BNXT_ULP_CLASS_HID_242b3] = 1258,
+	[BNXT_ULP_CLASS_HID_23dc7] = 1259,
+	[BNXT_ULP_CLASS_HID_25117] = 1260,
+	[BNXT_ULP_CLASS_HID_22c13] = 1261,
+	[BNXT_ULP_CLASS_HID_218c3] = 1262,
+	[BNXT_ULP_CLASS_HID_21417] = 1263,
+	[BNXT_ULP_CLASS_HID_22727] = 1264,
+	[BNXT_ULP_CLASS_HID_24f87] = 1265,
+	[BNXT_ULP_CLASS_HID_23c77] = 1266,
+	[BNXT_ULP_CLASS_HID_2378b] = 1267,
+	[BNXT_ULP_CLASS_HID_24adb] = 1268,
+	[BNXT_ULP_CLASS_HID_257b] = 1269,
+	[BNXT_ULP_CLASS_HID_2bb7] = 1270,
+	[BNXT_ULP_CLASS_HID_4f2b] = 1271,
+	[BNXT_ULP_CLASS_HID_1613] = 1272,
+	[BNXT_ULP_CLASS_HID_3987] = 1273,
+	[BNXT_ULP_CLASS_HID_48ef] = 1274,
+	[BNXT_ULP_CLASS_HID_0fd7] = 1275,
+	[BNXT_ULP_CLASS_HID_334b] = 1276,
+	[BNXT_ULP_CLASS_HID_25797] = 1277,
+	[BNXT_ULP_CLASS_HID_285eb] = 1278,
+	[BNXT_ULP_CLASS_HID_310eb] = 1279,
+	[BNXT_ULP_CLASS_HID_39beb] = 1280,
+	[BNXT_ULP_CLASS_HID_24447] = 1281,
+	[BNXT_ULP_CLASS_HID_2cf47] = 1282,
+	[BNXT_ULP_CLASS_HID_35a47] = 1283,
+	[BNXT_ULP_CLASS_HID_3889b] = 1284,
+	[BNXT_ULP_CLASS_HID_23f9b] = 1285,
+	[BNXT_ULP_CLASS_HID_2ca9b] = 1286,
+	[BNXT_ULP_CLASS_HID_3559b] = 1287,
+	[BNXT_ULP_CLASS_HID_383ef] = 1288,
+	[BNXT_ULP_CLASS_HID_252eb] = 1289,
+	[BNXT_ULP_CLASS_HID_2813f] = 1290,
+	[BNXT_ULP_CLASS_HID_30c3f] = 1291,
+	[BNXT_ULP_CLASS_HID_3973f] = 1292,
+	[BNXT_ULP_CLASS_HID_21e5f] = 1293,
+	[BNXT_ULP_CLASS_HID_2a95f] = 1294,
+	[BNXT_ULP_CLASS_HID_3345f] = 1295,
+	[BNXT_ULP_CLASS_HID_3bf5f] = 1296,
+	[BNXT_ULP_CLASS_HID_20b0f] = 1297,
+	[BNXT_ULP_CLASS_HID_2960f] = 1298,
+	[BNXT_ULP_CLASS_HID_3210f] = 1299,
+	[BNXT_ULP_CLASS_HID_3ac0f] = 1300,
+	[BNXT_ULP_CLASS_HID_20643] = 1301,
+	[BNXT_ULP_CLASS_HID_29143] = 1302,
+	[BNXT_ULP_CLASS_HID_31c43] = 1303,
+	[BNXT_ULP_CLASS_HID_3a743] = 1304,
+	[BNXT_ULP_CLASS_HID_21993] = 1305,
+	[BNXT_ULP_CLASS_HID_2a493] = 1306,
+	[BNXT_ULP_CLASS_HID_32f93] = 1307,
+	[BNXT_ULP_CLASS_HID_3ba93] = 1308,
+	[BNXT_ULP_CLASS_HID_24233] = 1309,
+	[BNXT_ULP_CLASS_HID_2cd33] = 1310,
+	[BNXT_ULP_CLASS_HID_35833] = 1311,
+	[BNXT_ULP_CLASS_HID_38607] = 1312,
+	[BNXT_ULP_CLASS_HID_22ee3] = 1313,
+	[BNXT_ULP_CLASS_HID_2b9e3] = 1314,
+	[BNXT_ULP_CLASS_HID_344e3] = 1315,
+	[BNXT_ULP_CLASS_HID_3cfe3] = 1316,
+	[BNXT_ULP_CLASS_HID_22a37] = 1317,
+	[BNXT_ULP_CLASS_HID_2b537] = 1318,
+	[BNXT_ULP_CLASS_HID_34037] = 1319,
+	[BNXT_ULP_CLASS_HID_3cb37] = 1320,
+	[BNXT_ULP_CLASS_HID_23d07] = 1321,
+	[BNXT_ULP_CLASS_HID_2c807] = 1322,
+	[BNXT_ULP_CLASS_HID_35307] = 1323,
+	[BNXT_ULP_CLASS_HID_3815b] = 1324,
+	[BNXT_ULP_CLASS_HID_208fb] = 1325,
+	[BNXT_ULP_CLASS_HID_293fb] = 1326,
+	[BNXT_ULP_CLASS_HID_31efb] = 1327,
+	[BNXT_ULP_CLASS_HID_3a9fb] = 1328,
+	[BNXT_ULP_CLASS_HID_25257] = 1329,
+	[BNXT_ULP_CLASS_HID_280ab] = 1330,
+	[BNXT_ULP_CLASS_HID_30bab] = 1331,
+	[BNXT_ULP_CLASS_HID_396ab] = 1332,
+	[BNXT_ULP_CLASS_HID_24dab] = 1333,
+	[BNXT_ULP_CLASS_HID_2d8ab] = 1334,
+	[BNXT_ULP_CLASS_HID_306ff] = 1335,
+	[BNXT_ULP_CLASS_HID_391ff] = 1336,
+	[BNXT_ULP_CLASS_HID_203cf] = 1337,
+	[BNXT_ULP_CLASS_HID_28ecf] = 1338,
+	[BNXT_ULP_CLASS_HID_319cf] = 1339,
+	[BNXT_ULP_CLASS_HID_3a4cf] = 1340,
+	[BNXT_ULP_CLASS_HID_2515b] = 1341,
+	[BNXT_ULP_CLASS_HID_2dc5b] = 1342,
+	[BNXT_ULP_CLASS_HID_30aaf] = 1343,
+	[BNXT_ULP_CLASS_HID_395af] = 1344,
+	[BNXT_ULP_CLASS_HID_23e0b] = 1345,
+	[BNXT_ULP_CLASS_HID_2c90b] = 1346,
+	[BNXT_ULP_CLASS_HID_3540b] = 1347,
+	[BNXT_ULP_CLASS_HID_3825f] = 1348,
+	[BNXT_ULP_CLASS_HID_2395f] = 1349,
+	[BNXT_ULP_CLASS_HID_2c45f] = 1350,
+	[BNXT_ULP_CLASS_HID_34f5f] = 1351,
+	[BNXT_ULP_CLASS_HID_3da5f] = 1352,
+	[BNXT_ULP_CLASS_HID_24caf] = 1353,
+	[BNXT_ULP_CLASS_HID_2d7af] = 1354,
+	[BNXT_ULP_CLASS_HID_305e3] = 1355,
+	[BNXT_ULP_CLASS_HID_390e3] = 1356,
+	[BNXT_ULP_CLASS_HID_21803] = 1357,
+	[BNXT_ULP_CLASS_HID_2a303] = 1358,
+	[BNXT_ULP_CLASS_HID_32e03] = 1359,
+	[BNXT_ULP_CLASS_HID_3b903] = 1360,
+	[BNXT_ULP_CLASS_HID_20533] = 1361,
+	[BNXT_ULP_CLASS_HID_29033] = 1362,
+	[BNXT_ULP_CLASS_HID_31b33] = 1363,
+	[BNXT_ULP_CLASS_HID_3a633] = 1364,
+	[BNXT_ULP_CLASS_HID_20007] = 1365,
+	[BNXT_ULP_CLASS_HID_28b07] = 1366,
+	[BNXT_ULP_CLASS_HID_31607] = 1367,
+	[BNXT_ULP_CLASS_HID_3a107] = 1368,
+	[BNXT_ULP_CLASS_HID_21357] = 1369,
+	[BNXT_ULP_CLASS_HID_29e57] = 1370,
+	[BNXT_ULP_CLASS_HID_32957] = 1371,
+	[BNXT_ULP_CLASS_HID_3b457] = 1372,
+	[BNXT_ULP_CLASS_HID_23bf7] = 1373,
+	[BNXT_ULP_CLASS_HID_2c6f7] = 1374,
+	[BNXT_ULP_CLASS_HID_351f7] = 1375,
+	[BNXT_ULP_CLASS_HID_3dcf7] = 1376,
+	[BNXT_ULP_CLASS_HID_228a7] = 1377,
+	[BNXT_ULP_CLASS_HID_2b3a7] = 1378,
+	[BNXT_ULP_CLASS_HID_33ea7] = 1379,
+	[BNXT_ULP_CLASS_HID_3c9a7] = 1380,
+	[BNXT_ULP_CLASS_HID_223fb] = 1381,
+	[BNXT_ULP_CLASS_HID_2aefb] = 1382,
+	[BNXT_ULP_CLASS_HID_339fb] = 1383,
+	[BNXT_ULP_CLASS_HID_3c4fb] = 1384,
+	[BNXT_ULP_CLASS_HID_236cb] = 1385,
+	[BNXT_ULP_CLASS_HID_2c1cb] = 1386,
+	[BNXT_ULP_CLASS_HID_34ccb] = 1387,
+	[BNXT_ULP_CLASS_HID_3d7cb] = 1388,
+	[BNXT_ULP_CLASS_HID_202bf] = 1389,
+	[BNXT_ULP_CLASS_HID_28dbf] = 1390,
+	[BNXT_ULP_CLASS_HID_318bf] = 1391,
+	[BNXT_ULP_CLASS_HID_3a3bf] = 1392,
+	[BNXT_ULP_CLASS_HID_24c1b] = 1393,
+	[BNXT_ULP_CLASS_HID_2d71b] = 1394,
+	[BNXT_ULP_CLASS_HID_3056f] = 1395,
+	[BNXT_ULP_CLASS_HID_3906f] = 1396,
+	[BNXT_ULP_CLASS_HID_2476f] = 1397,
+	[BNXT_ULP_CLASS_HID_2d26f] = 1398,
+	[BNXT_ULP_CLASS_HID_300a3] = 1399,
+	[BNXT_ULP_CLASS_HID_38ba3] = 1400,
+	[BNXT_ULP_CLASS_HID_25abf] = 1401,
+	[BNXT_ULP_CLASS_HID_288f3] = 1402,
+	[BNXT_ULP_CLASS_HID_313f3] = 1403,
+	[BNXT_ULP_CLASS_HID_39ef3] = 1404,
+	[BNXT_ULP_CLASS_HID_24b1f] = 1405,
+	[BNXT_ULP_CLASS_HID_2d61f] = 1406,
+	[BNXT_ULP_CLASS_HID_30453] = 1407,
+	[BNXT_ULP_CLASS_HID_38f53] = 1408,
+	[BNXT_ULP_CLASS_HID_237cf] = 1409,
+	[BNXT_ULP_CLASS_HID_2c2cf] = 1410,
+	[BNXT_ULP_CLASS_HID_34dcf] = 1411,
+	[BNXT_ULP_CLASS_HID_3d8cf] = 1412,
+	[BNXT_ULP_CLASS_HID_23303] = 1413,
+	[BNXT_ULP_CLASS_HID_2be03] = 1414,
+	[BNXT_ULP_CLASS_HID_34903] = 1415,
+	[BNXT_ULP_CLASS_HID_3d403] = 1416,
+	[BNXT_ULP_CLASS_HID_24653] = 1417,
+	[BNXT_ULP_CLASS_HID_2d153] = 1418,
+	[BNXT_ULP_CLASS_HID_35c53] = 1419,
+	[BNXT_ULP_CLASS_HID_38aa7] = 1420,
+	[BNXT_ULP_CLASS_HID_211c7] = 1421,
+	[BNXT_ULP_CLASS_HID_29cc7] = 1422,
+	[BNXT_ULP_CLASS_HID_327c7] = 1423,
+	[BNXT_ULP_CLASS_HID_3b2c7] = 1424,
+	[BNXT_ULP_CLASS_HID_25ba3] = 1425,
+	[BNXT_ULP_CLASS_HID_289f7] = 1426,
+	[BNXT_ULP_CLASS_HID_314f7] = 1427,
+	[BNXT_ULP_CLASS_HID_39ff7] = 1428,
+	[BNXT_ULP_CLASS_HID_256f7] = 1429,
+	[BNXT_ULP_CLASS_HID_284cb] = 1430,
+	[BNXT_ULP_CLASS_HID_30fcb] = 1431,
+	[BNXT_ULP_CLASS_HID_39acb] = 1432,
+	[BNXT_ULP_CLASS_HID_20d1b] = 1433,
+	[BNXT_ULP_CLASS_HID_2981b] = 1434,
+	[BNXT_ULP_CLASS_HID_3231b] = 1435,
+	[BNXT_ULP_CLASS_HID_3ae1b] = 1436,
+	[BNXT_ULP_CLASS_HID_235bb] = 1437,
+	[BNXT_ULP_CLASS_HID_2c0bb] = 1438,
+	[BNXT_ULP_CLASS_HID_34bbb] = 1439,
+	[BNXT_ULP_CLASS_HID_3d6bb] = 1440,
+	[BNXT_ULP_CLASS_HID_2226b] = 1441,
+	[BNXT_ULP_CLASS_HID_2ad6b] = 1442,
+	[BNXT_ULP_CLASS_HID_3386b] = 1443,
+	[BNXT_ULP_CLASS_HID_3c36b] = 1444,
+	[BNXT_ULP_CLASS_HID_21dbf] = 1445,
+	[BNXT_ULP_CLASS_HID_2a8bf] = 1446,
+	[BNXT_ULP_CLASS_HID_333bf] = 1447,
+	[BNXT_ULP_CLASS_HID_3bebf] = 1448,
+	[BNXT_ULP_CLASS_HID_2308f] = 1449,
+	[BNXT_ULP_CLASS_HID_2bb8f] = 1450,
+	[BNXT_ULP_CLASS_HID_3468f] = 1451,
+	[BNXT_ULP_CLASS_HID_3d18f] = 1452,
+	[BNXT_ULP_CLASS_HID_2592f] = 1453,
+	[BNXT_ULP_CLASS_HID_28763] = 1454,
+	[BNXT_ULP_CLASS_HID_31263] = 1455,
+	[BNXT_ULP_CLASS_HID_39d63] = 1456,
+	[BNXT_ULP_CLASS_HID_245df] = 1457,
+	[BNXT_ULP_CLASS_HID_2d0df] = 1458,
+	[BNXT_ULP_CLASS_HID_35bdf] = 1459,
+	[BNXT_ULP_CLASS_HID_38a13] = 1460,
+	[BNXT_ULP_CLASS_HID_24113] = 1461,
+	[BNXT_ULP_CLASS_HID_2cc13] = 1462,
+	[BNXT_ULP_CLASS_HID_35713] = 1463,
+	[BNXT_ULP_CLASS_HID_38567] = 1464,
+	[BNXT_ULP_CLASS_HID_25463] = 1465,
+	[BNXT_ULP_CLASS_HID_282b7] = 1466,
+	[BNXT_ULP_CLASS_HID_30db7] = 1467,
+	[BNXT_ULP_CLASS_HID_398b7] = 1468,
+	[BNXT_ULP_CLASS_HID_244c3] = 1469,
+	[BNXT_ULP_CLASS_HID_2cfc3] = 1470,
+	[BNXT_ULP_CLASS_HID_35ac3] = 1471,
+	[BNXT_ULP_CLASS_HID_38917] = 1472,
+	[BNXT_ULP_CLASS_HID_231f3] = 1473,
+	[BNXT_ULP_CLASS_HID_2bcf3] = 1474,
+	[BNXT_ULP_CLASS_HID_347f3] = 1475,
+	[BNXT_ULP_CLASS_HID_3d2f3] = 1476,
+	[BNXT_ULP_CLASS_HID_22cc7] = 1477,
+	[BNXT_ULP_CLASS_HID_2b7c7] = 1478,
+	[BNXT_ULP_CLASS_HID_342c7] = 1479,
+	[BNXT_ULP_CLASS_HID_3cdc7] = 1480,
+	[BNXT_ULP_CLASS_HID_24017] = 1481,
+	[BNXT_ULP_CLASS_HID_2cb17] = 1482,
+	[BNXT_ULP_CLASS_HID_35617] = 1483,
+	[BNXT_ULP_CLASS_HID_3846b] = 1484,
+	[BNXT_ULP_CLASS_HID_20b8b] = 1485,
+	[BNXT_ULP_CLASS_HID_2968b] = 1486,
+	[BNXT_ULP_CLASS_HID_3218b] = 1487,
+	[BNXT_ULP_CLASS_HID_3ac8b] = 1488,
+	[BNXT_ULP_CLASS_HID_25567] = 1489,
+	[BNXT_ULP_CLASS_HID_283bb] = 1490,
+	[BNXT_ULP_CLASS_HID_30ebb] = 1491,
+	[BNXT_ULP_CLASS_HID_399bb] = 1492,
+	[BNXT_ULP_CLASS_HID_250bb] = 1493,
+	[BNXT_ULP_CLASS_HID_2dbbb] = 1494,
+	[BNXT_ULP_CLASS_HID_3098f] = 1495,
+	[BNXT_ULP_CLASS_HID_3948f] = 1496,
+	[BNXT_ULP_CLASS_HID_206df] = 1497,
+	[BNXT_ULP_CLASS_HID_291df] = 1498,
+	[BNXT_ULP_CLASS_HID_31cdf] = 1499,
+	[BNXT_ULP_CLASS_HID_3a7df] = 1500,
+	[BNXT_ULP_CLASS_HID_22f7f] = 1501,
+	[BNXT_ULP_CLASS_HID_2ba7f] = 1502,
+	[BNXT_ULP_CLASS_HID_3457f] = 1503,
+	[BNXT_ULP_CLASS_HID_3d07f] = 1504,
+	[BNXT_ULP_CLASS_HID_21c2f] = 1505,
+	[BNXT_ULP_CLASS_HID_2a72f] = 1506,
+	[BNXT_ULP_CLASS_HID_3322f] = 1507,
+	[BNXT_ULP_CLASS_HID_3bd2f] = 1508,
+	[BNXT_ULP_CLASS_HID_21763] = 1509,
+	[BNXT_ULP_CLASS_HID_2a263] = 1510,
+	[BNXT_ULP_CLASS_HID_32d63] = 1511,
+	[BNXT_ULP_CLASS_HID_3b863] = 1512,
+	[BNXT_ULP_CLASS_HID_22ab3] = 1513,
+	[BNXT_ULP_CLASS_HID_2b5b3] = 1514,
+	[BNXT_ULP_CLASS_HID_340b3] = 1515,
+	[BNXT_ULP_CLASS_HID_3cbb3] = 1516,
+	[BNXT_ULP_CLASS_HID_252d3] = 1517,
+	[BNXT_ULP_CLASS_HID_28127] = 1518,
+	[BNXT_ULP_CLASS_HID_30c27] = 1519,
+	[BNXT_ULP_CLASS_HID_39727] = 1520,
+	[BNXT_ULP_CLASS_HID_23f83] = 1521,
+	[BNXT_ULP_CLASS_HID_2ca83] = 1522,
+	[BNXT_ULP_CLASS_HID_35583] = 1523,
+	[BNXT_ULP_CLASS_HID_383d7] = 1524,
+	[BNXT_ULP_CLASS_HID_23ad7] = 1525,
+	[BNXT_ULP_CLASS_HID_2c5d7] = 1526,
+	[BNXT_ULP_CLASS_HID_350d7] = 1527,
+	[BNXT_ULP_CLASS_HID_3dbd7] = 1528,
+	[BNXT_ULP_CLASS_HID_24e27] = 1529,
+	[BNXT_ULP_CLASS_HID_2d927] = 1530,
+	[BNXT_ULP_CLASS_HID_3077b] = 1531,
+	[BNXT_ULP_CLASS_HID_3927b] = 1532,
+	[BNXT_ULP_CLASS_HID_2320f] = 1533,
+	[BNXT_ULP_CLASS_HID_2bd0f] = 1534,
+	[BNXT_ULP_CLASS_HID_3480f] = 1535,
+	[BNXT_ULP_CLASS_HID_3d30f] = 1536,
+	[BNXT_ULP_CLASS_HID_21f3f] = 1537,
+	[BNXT_ULP_CLASS_HID_2aa3f] = 1538,
+	[BNXT_ULP_CLASS_HID_3353f] = 1539,
+	[BNXT_ULP_CLASS_HID_3c03f] = 1540,
+	[BNXT_ULP_CLASS_HID_21a73] = 1541,
+	[BNXT_ULP_CLASS_HID_2a573] = 1542,
+	[BNXT_ULP_CLASS_HID_33073] = 1543,
+	[BNXT_ULP_CLASS_HID_3bb73] = 1544,
+	[BNXT_ULP_CLASS_HID_22d43] = 1545,
+	[BNXT_ULP_CLASS_HID_2b843] = 1546,
+	[BNXT_ULP_CLASS_HID_34343] = 1547,
+	[BNXT_ULP_CLASS_HID_3ce43] = 1548,
+	[BNXT_ULP_CLASS_HID_255e3] = 1549,
+	[BNXT_ULP_CLASS_HID_28437] = 1550,
+	[BNXT_ULP_CLASS_HID_30f37] = 1551,
+	[BNXT_ULP_CLASS_HID_39a37] = 1552,
+	[BNXT_ULP_CLASS_HID_24293] = 1553,
+	[BNXT_ULP_CLASS_HID_2cd93] = 1554,
+	[BNXT_ULP_CLASS_HID_35893] = 1555,
+	[BNXT_ULP_CLASS_HID_386e7] = 1556,
+	[BNXT_ULP_CLASS_HID_23de7] = 1557,
+	[BNXT_ULP_CLASS_HID_2c8e7] = 1558,
+	[BNXT_ULP_CLASS_HID_353e7] = 1559,
+	[BNXT_ULP_CLASS_HID_3823b] = 1560,
+	[BNXT_ULP_CLASS_HID_25137] = 1561,
+	[BNXT_ULP_CLASS_HID_2dc37] = 1562,
+	[BNXT_ULP_CLASS_HID_30a0b] = 1563,
+	[BNXT_ULP_CLASS_HID_3950b] = 1564,
+	[BNXT_ULP_CLASS_HID_22c33] = 1565,
+	[BNXT_ULP_CLASS_HID_2b733] = 1566,
+	[BNXT_ULP_CLASS_HID_34233] = 1567,
+	[BNXT_ULP_CLASS_HID_3cd33] = 1568,
+	[BNXT_ULP_CLASS_HID_218e3] = 1569,
+	[BNXT_ULP_CLASS_HID_2a3e3] = 1570,
+	[BNXT_ULP_CLASS_HID_32ee3] = 1571,
+	[BNXT_ULP_CLASS_HID_3b9e3] = 1572,
+	[BNXT_ULP_CLASS_HID_21437] = 1573,
+	[BNXT_ULP_CLASS_HID_29f37] = 1574,
+	[BNXT_ULP_CLASS_HID_32a37] = 1575,
+	[BNXT_ULP_CLASS_HID_3b537] = 1576,
+	[BNXT_ULP_CLASS_HID_22707] = 1577,
+	[BNXT_ULP_CLASS_HID_2b207] = 1578,
+	[BNXT_ULP_CLASS_HID_33d07] = 1579,
+	[BNXT_ULP_CLASS_HID_3c807] = 1580,
+	[BNXT_ULP_CLASS_HID_24fa7] = 1581,
+	[BNXT_ULP_CLASS_HID_2daa7] = 1582,
+	[BNXT_ULP_CLASS_HID_308fb] = 1583,
+	[BNXT_ULP_CLASS_HID_393fb] = 1584,
+	[BNXT_ULP_CLASS_HID_23c57] = 1585,
+	[BNXT_ULP_CLASS_HID_2c757] = 1586,
+	[BNXT_ULP_CLASS_HID_35257] = 1587,
+	[BNXT_ULP_CLASS_HID_380ab] = 1588,
+	[BNXT_ULP_CLASS_HID_237ab] = 1589,
+	[BNXT_ULP_CLASS_HID_2c2ab] = 1590,
+	[BNXT_ULP_CLASS_HID_34dab] = 1591,
+	[BNXT_ULP_CLASS_HID_3d8ab] = 1592,
+	[BNXT_ULP_CLASS_HID_24afb] = 1593,
+	[BNXT_ULP_CLASS_HID_2d5fb] = 1594,
+	[BNXT_ULP_CLASS_HID_303cf] = 1595,
+	[BNXT_ULP_CLASS_HID_38ecf] = 1596,
+	[BNXT_ULP_CLASS_HID_255b] = 1597,
+	[BNXT_ULP_CLASS_HID_2b97] = 1598,
+	[BNXT_ULP_CLASS_HID_4f0b] = 1599,
+	[BNXT_ULP_CLASS_HID_1633] = 1600,
+	[BNXT_ULP_CLASS_HID_39a7] = 1601,
+	[BNXT_ULP_CLASS_HID_48cf] = 1602,
+	[BNXT_ULP_CLASS_HID_0ff7] = 1603,
+	[BNXT_ULP_CLASS_HID_336b] = 1604,
+	[BNXT_ULP_CLASS_HID_257f7] = 1605,
+	[BNXT_ULP_CLASS_HID_2858b] = 1606,
+	[BNXT_ULP_CLASS_HID_3108b] = 1607,
+	[BNXT_ULP_CLASS_HID_39b8b] = 1608,
+	[BNXT_ULP_CLASS_HID_24427] = 1609,
+	[BNXT_ULP_CLASS_HID_2cf27] = 1610,
+	[BNXT_ULP_CLASS_HID_35a27] = 1611,
+	[BNXT_ULP_CLASS_HID_388fb] = 1612,
+	[BNXT_ULP_CLASS_HID_23ffb] = 1613,
+	[BNXT_ULP_CLASS_HID_2cafb] = 1614,
+	[BNXT_ULP_CLASS_HID_355fb] = 1615,
+	[BNXT_ULP_CLASS_HID_3838f] = 1616,
+	[BNXT_ULP_CLASS_HID_2528b] = 1617,
+	[BNXT_ULP_CLASS_HID_2815f] = 1618,
+	[BNXT_ULP_CLASS_HID_30c5f] = 1619,
+	[BNXT_ULP_CLASS_HID_3975f] = 1620,
+	[BNXT_ULP_CLASS_HID_21e3f] = 1621,
+	[BNXT_ULP_CLASS_HID_2a93f] = 1622,
+	[BNXT_ULP_CLASS_HID_3343f] = 1623,
+	[BNXT_ULP_CLASS_HID_3bf3f] = 1624,
+	[BNXT_ULP_CLASS_HID_20b6f] = 1625,
+	[BNXT_ULP_CLASS_HID_2966f] = 1626,
+	[BNXT_ULP_CLASS_HID_3216f] = 1627,
+	[BNXT_ULP_CLASS_HID_3ac6f] = 1628,
+	[BNXT_ULP_CLASS_HID_20623] = 1629,
+	[BNXT_ULP_CLASS_HID_29123] = 1630,
+	[BNXT_ULP_CLASS_HID_31c23] = 1631,
+	[BNXT_ULP_CLASS_HID_3a723] = 1632,
+	[BNXT_ULP_CLASS_HID_219f3] = 1633,
+	[BNXT_ULP_CLASS_HID_2a4f3] = 1634,
+	[BNXT_ULP_CLASS_HID_32ff3] = 1635,
+	[BNXT_ULP_CLASS_HID_3baf3] = 1636,
+	[BNXT_ULP_CLASS_HID_24253] = 1637,
+	[BNXT_ULP_CLASS_HID_2cd53] = 1638,
+	[BNXT_ULP_CLASS_HID_35853] = 1639,
+	[BNXT_ULP_CLASS_HID_38667] = 1640,
+	[BNXT_ULP_CLASS_HID_22e83] = 1641,
+	[BNXT_ULP_CLASS_HID_2b983] = 1642,
+	[BNXT_ULP_CLASS_HID_34483] = 1643,
+	[BNXT_ULP_CLASS_HID_3cf83] = 1644,
+	[BNXT_ULP_CLASS_HID_22a57] = 1645,
+	[BNXT_ULP_CLASS_HID_2b557] = 1646,
+	[BNXT_ULP_CLASS_HID_34057] = 1647,
+	[BNXT_ULP_CLASS_HID_3cb57] = 1648,
+	[BNXT_ULP_CLASS_HID_23d67] = 1649,
+	[BNXT_ULP_CLASS_HID_2c867] = 1650,
+	[BNXT_ULP_CLASS_HID_35367] = 1651,
+	[BNXT_ULP_CLASS_HID_3813b] = 1652,
+	[BNXT_ULP_CLASS_HID_2089b] = 1653,
+	[BNXT_ULP_CLASS_HID_2939b] = 1654,
+	[BNXT_ULP_CLASS_HID_31e9b] = 1655,
+	[BNXT_ULP_CLASS_HID_3a99b] = 1656,
+	[BNXT_ULP_CLASS_HID_25237] = 1657,
+	[BNXT_ULP_CLASS_HID_280cb] = 1658,
+	[BNXT_ULP_CLASS_HID_30bcb] = 1659,
+	[BNXT_ULP_CLASS_HID_396cb] = 1660,
+	[BNXT_ULP_CLASS_HID_24dcb] = 1661,
+	[BNXT_ULP_CLASS_HID_2d8cb] = 1662,
+	[BNXT_ULP_CLASS_HID_3069f] = 1663,
+	[BNXT_ULP_CLASS_HID_3919f] = 1664,
+	[BNXT_ULP_CLASS_HID_203af] = 1665,
+	[BNXT_ULP_CLASS_HID_28eaf] = 1666,
+	[BNXT_ULP_CLASS_HID_319af] = 1667,
+	[BNXT_ULP_CLASS_HID_3a4af] = 1668,
+	[BNXT_ULP_CLASS_HID_2513b] = 1669,
+	[BNXT_ULP_CLASS_HID_2dc3b] = 1670,
+	[BNXT_ULP_CLASS_HID_30acf] = 1671,
+	[BNXT_ULP_CLASS_HID_395cf] = 1672,
+	[BNXT_ULP_CLASS_HID_23e6b] = 1673,
+	[BNXT_ULP_CLASS_HID_2c96b] = 1674,
+	[BNXT_ULP_CLASS_HID_3546b] = 1675,
+	[BNXT_ULP_CLASS_HID_3823f] = 1676,
+	[BNXT_ULP_CLASS_HID_2393f] = 1677,
+	[BNXT_ULP_CLASS_HID_2c43f] = 1678,
+	[BNXT_ULP_CLASS_HID_34f3f] = 1679,
+	[BNXT_ULP_CLASS_HID_3da3f] = 1680,
+	[BNXT_ULP_CLASS_HID_24ccf] = 1681,
+	[BNXT_ULP_CLASS_HID_2d7cf] = 1682,
+	[BNXT_ULP_CLASS_HID_30583] = 1683,
+	[BNXT_ULP_CLASS_HID_39083] = 1684,
+	[BNXT_ULP_CLASS_HID_21863] = 1685,
+	[BNXT_ULP_CLASS_HID_2a363] = 1686,
+	[BNXT_ULP_CLASS_HID_32e63] = 1687,
+	[BNXT_ULP_CLASS_HID_3b963] = 1688,
+	[BNXT_ULP_CLASS_HID_20553] = 1689,
+	[BNXT_ULP_CLASS_HID_29053] = 1690,
+	[BNXT_ULP_CLASS_HID_31b53] = 1691,
+	[BNXT_ULP_CLASS_HID_3a653] = 1692,
+	[BNXT_ULP_CLASS_HID_20067] = 1693,
+	[BNXT_ULP_CLASS_HID_28b67] = 1694,
+	[BNXT_ULP_CLASS_HID_31667] = 1695,
+	[BNXT_ULP_CLASS_HID_3a167] = 1696,
+	[BNXT_ULP_CLASS_HID_21337] = 1697,
+	[BNXT_ULP_CLASS_HID_29e37] = 1698,
+	[BNXT_ULP_CLASS_HID_32937] = 1699,
+	[BNXT_ULP_CLASS_HID_3b437] = 1700,
+	[BNXT_ULP_CLASS_HID_23b97] = 1701,
+	[BNXT_ULP_CLASS_HID_2c697] = 1702,
+	[BNXT_ULP_CLASS_HID_35197] = 1703,
+	[BNXT_ULP_CLASS_HID_3dc97] = 1704,
+	[BNXT_ULP_CLASS_HID_228c7] = 1705,
+	[BNXT_ULP_CLASS_HID_2b3c7] = 1706,
+	[BNXT_ULP_CLASS_HID_33ec7] = 1707,
+	[BNXT_ULP_CLASS_HID_3c9c7] = 1708,
+	[BNXT_ULP_CLASS_HID_2239b] = 1709,
+	[BNXT_ULP_CLASS_HID_2ae9b] = 1710,
+	[BNXT_ULP_CLASS_HID_3399b] = 1711,
+	[BNXT_ULP_CLASS_HID_3c49b] = 1712,
+	[BNXT_ULP_CLASS_HID_236ab] = 1713,
+	[BNXT_ULP_CLASS_HID_2c1ab] = 1714,
+	[BNXT_ULP_CLASS_HID_34cab] = 1715,
+	[BNXT_ULP_CLASS_HID_3d7ab] = 1716,
+	[BNXT_ULP_CLASS_HID_202df] = 1717,
+	[BNXT_ULP_CLASS_HID_28ddf] = 1718,
+	[BNXT_ULP_CLASS_HID_318df] = 1719,
+	[BNXT_ULP_CLASS_HID_3a3df] = 1720,
+	[BNXT_ULP_CLASS_HID_24c7b] = 1721,
+	[BNXT_ULP_CLASS_HID_2d77b] = 1722,
+	[BNXT_ULP_CLASS_HID_3050f] = 1723,
+	[BNXT_ULP_CLASS_HID_3900f] = 1724,
+	[BNXT_ULP_CLASS_HID_2470f] = 1725,
+	[BNXT_ULP_CLASS_HID_2d20f] = 1726,
+	[BNXT_ULP_CLASS_HID_300c3] = 1727,
+	[BNXT_ULP_CLASS_HID_38bc3] = 1728,
+	[BNXT_ULP_CLASS_HID_25adf] = 1729,
+	[BNXT_ULP_CLASS_HID_28893] = 1730,
+	[BNXT_ULP_CLASS_HID_31393] = 1731,
+	[BNXT_ULP_CLASS_HID_39e93] = 1732,
+	[BNXT_ULP_CLASS_HID_24b7f] = 1733,
+	[BNXT_ULP_CLASS_HID_2d67f] = 1734,
+	[BNXT_ULP_CLASS_HID_30433] = 1735,
+	[BNXT_ULP_CLASS_HID_38f33] = 1736,
+	[BNXT_ULP_CLASS_HID_237af] = 1737,
+	[BNXT_ULP_CLASS_HID_2c2af] = 1738,
+	[BNXT_ULP_CLASS_HID_34daf] = 1739,
+	[BNXT_ULP_CLASS_HID_3d8af] = 1740,
+	[BNXT_ULP_CLASS_HID_23363] = 1741,
+	[BNXT_ULP_CLASS_HID_2be63] = 1742,
+	[BNXT_ULP_CLASS_HID_34963] = 1743,
+	[BNXT_ULP_CLASS_HID_3d463] = 1744,
+	[BNXT_ULP_CLASS_HID_24633] = 1745,
+	[BNXT_ULP_CLASS_HID_2d133] = 1746,
+	[BNXT_ULP_CLASS_HID_35c33] = 1747,
+	[BNXT_ULP_CLASS_HID_38ac7] = 1748,
+	[BNXT_ULP_CLASS_HID_211a7] = 1749,
+	[BNXT_ULP_CLASS_HID_29ca7] = 1750,
+	[BNXT_ULP_CLASS_HID_327a7] = 1751,
+	[BNXT_ULP_CLASS_HID_3b2a7] = 1752,
+	[BNXT_ULP_CLASS_HID_25bc3] = 1753,
+	[BNXT_ULP_CLASS_HID_28997] = 1754,
+	[BNXT_ULP_CLASS_HID_31497] = 1755,
+	[BNXT_ULP_CLASS_HID_39f97] = 1756,
+	[BNXT_ULP_CLASS_HID_25697] = 1757,
+	[BNXT_ULP_CLASS_HID_284ab] = 1758,
+	[BNXT_ULP_CLASS_HID_30fab] = 1759,
+	[BNXT_ULP_CLASS_HID_39aab] = 1760,
+	[BNXT_ULP_CLASS_HID_20d7b] = 1761,
+	[BNXT_ULP_CLASS_HID_2987b] = 1762,
+	[BNXT_ULP_CLASS_HID_3237b] = 1763,
+	[BNXT_ULP_CLASS_HID_3ae7b] = 1764,
+	[BNXT_ULP_CLASS_HID_235db] = 1765,
+	[BNXT_ULP_CLASS_HID_2c0db] = 1766,
+	[BNXT_ULP_CLASS_HID_34bdb] = 1767,
+	[BNXT_ULP_CLASS_HID_3d6db] = 1768,
+	[BNXT_ULP_CLASS_HID_2220b] = 1769,
+	[BNXT_ULP_CLASS_HID_2ad0b] = 1770,
+	[BNXT_ULP_CLASS_HID_3380b] = 1771,
+	[BNXT_ULP_CLASS_HID_3c30b] = 1772,
+	[BNXT_ULP_CLASS_HID_21ddf] = 1773,
+	[BNXT_ULP_CLASS_HID_2a8df] = 1774,
+	[BNXT_ULP_CLASS_HID_333df] = 1775,
+	[BNXT_ULP_CLASS_HID_3bedf] = 1776,
+	[BNXT_ULP_CLASS_HID_230ef] = 1777,
+	[BNXT_ULP_CLASS_HID_2bbef] = 1778,
+	[BNXT_ULP_CLASS_HID_346ef] = 1779,
+	[BNXT_ULP_CLASS_HID_3d1ef] = 1780,
+	[BNXT_ULP_CLASS_HID_2594f] = 1781,
+	[BNXT_ULP_CLASS_HID_28703] = 1782,
+	[BNXT_ULP_CLASS_HID_31203] = 1783,
+	[BNXT_ULP_CLASS_HID_39d03] = 1784,
+	[BNXT_ULP_CLASS_HID_245bf] = 1785,
+	[BNXT_ULP_CLASS_HID_2d0bf] = 1786,
+	[BNXT_ULP_CLASS_HID_35bbf] = 1787,
+	[BNXT_ULP_CLASS_HID_38a73] = 1788,
+	[BNXT_ULP_CLASS_HID_24173] = 1789,
+	[BNXT_ULP_CLASS_HID_2cc73] = 1790,
+	[BNXT_ULP_CLASS_HID_35773] = 1791,
+	[BNXT_ULP_CLASS_HID_38507] = 1792,
+	[BNXT_ULP_CLASS_HID_25403] = 1793,
+	[BNXT_ULP_CLASS_HID_282d7] = 1794,
+	[BNXT_ULP_CLASS_HID_30dd7] = 1795,
+	[BNXT_ULP_CLASS_HID_398d7] = 1796,
+	[BNXT_ULP_CLASS_HID_244a3] = 1797,
+	[BNXT_ULP_CLASS_HID_2cfa3] = 1798,
+	[BNXT_ULP_CLASS_HID_35aa3] = 1799,
+	[BNXT_ULP_CLASS_HID_38977] = 1800,
+	[BNXT_ULP_CLASS_HID_23193] = 1801,
+	[BNXT_ULP_CLASS_HID_2bc93] = 1802,
+	[BNXT_ULP_CLASS_HID_34793] = 1803,
+	[BNXT_ULP_CLASS_HID_3d293] = 1804,
+	[BNXT_ULP_CLASS_HID_22ca7] = 1805,
+	[BNXT_ULP_CLASS_HID_2b7a7] = 1806,
+	[BNXT_ULP_CLASS_HID_342a7] = 1807,
+	[BNXT_ULP_CLASS_HID_3cda7] = 1808,
+	[BNXT_ULP_CLASS_HID_24077] = 1809,
+	[BNXT_ULP_CLASS_HID_2cb77] = 1810,
+	[BNXT_ULP_CLASS_HID_35677] = 1811,
+	[BNXT_ULP_CLASS_HID_3840b] = 1812,
+	[BNXT_ULP_CLASS_HID_20beb] = 1813,
+	[BNXT_ULP_CLASS_HID_296eb] = 1814,
+	[BNXT_ULP_CLASS_HID_321eb] = 1815,
+	[BNXT_ULP_CLASS_HID_3aceb] = 1816,
+	[BNXT_ULP_CLASS_HID_25507] = 1817,
+	[BNXT_ULP_CLASS_HID_283db] = 1818,
+	[BNXT_ULP_CLASS_HID_30edb] = 1819,
+	[BNXT_ULP_CLASS_HID_399db] = 1820,
+	[BNXT_ULP_CLASS_HID_250db] = 1821,
+	[BNXT_ULP_CLASS_HID_2dbdb] = 1822,
+	[BNXT_ULP_CLASS_HID_309ef] = 1823,
+	[BNXT_ULP_CLASS_HID_394ef] = 1824,
+	[BNXT_ULP_CLASS_HID_206bf] = 1825,
+	[BNXT_ULP_CLASS_HID_291bf] = 1826,
+	[BNXT_ULP_CLASS_HID_31cbf] = 1827,
+	[BNXT_ULP_CLASS_HID_3a7bf] = 1828,
+	[BNXT_ULP_CLASS_HID_22f1f] = 1829,
+	[BNXT_ULP_CLASS_HID_2ba1f] = 1830,
+	[BNXT_ULP_CLASS_HID_3451f] = 1831,
+	[BNXT_ULP_CLASS_HID_3d01f] = 1832,
+	[BNXT_ULP_CLASS_HID_21c4f] = 1833,
+	[BNXT_ULP_CLASS_HID_2a74f] = 1834,
+	[BNXT_ULP_CLASS_HID_3324f] = 1835,
+	[BNXT_ULP_CLASS_HID_3bd4f] = 1836,
+	[BNXT_ULP_CLASS_HID_21703] = 1837,
+	[BNXT_ULP_CLASS_HID_2a203] = 1838,
+	[BNXT_ULP_CLASS_HID_32d03] = 1839,
+	[BNXT_ULP_CLASS_HID_3b803] = 1840,
+	[BNXT_ULP_CLASS_HID_22ad3] = 1841,
+	[BNXT_ULP_CLASS_HID_2b5d3] = 1842,
+	[BNXT_ULP_CLASS_HID_340d3] = 1843,
+	[BNXT_ULP_CLASS_HID_3cbd3] = 1844,
+	[BNXT_ULP_CLASS_HID_252b3] = 1845,
+	[BNXT_ULP_CLASS_HID_28147] = 1846,
+	[BNXT_ULP_CLASS_HID_30c47] = 1847,
+	[BNXT_ULP_CLASS_HID_39747] = 1848,
+	[BNXT_ULP_CLASS_HID_23fe3] = 1849,
+	[BNXT_ULP_CLASS_HID_2cae3] = 1850,
+	[BNXT_ULP_CLASS_HID_355e3] = 1851,
+	[BNXT_ULP_CLASS_HID_383b7] = 1852,
+	[BNXT_ULP_CLASS_HID_23ab7] = 1853,
+	[BNXT_ULP_CLASS_HID_2c5b7] = 1854,
+	[BNXT_ULP_CLASS_HID_350b7] = 1855,
+	[BNXT_ULP_CLASS_HID_3dbb7] = 1856,
+	[BNXT_ULP_CLASS_HID_24e47] = 1857,
+	[BNXT_ULP_CLASS_HID_2d947] = 1858,
+	[BNXT_ULP_CLASS_HID_3071b] = 1859,
+	[BNXT_ULP_CLASS_HID_3921b] = 1860,
+	[BNXT_ULP_CLASS_HID_2326f] = 1861,
+	[BNXT_ULP_CLASS_HID_2bd6f] = 1862,
+	[BNXT_ULP_CLASS_HID_3486f] = 1863,
+	[BNXT_ULP_CLASS_HID_3d36f] = 1864,
+	[BNXT_ULP_CLASS_HID_21f5f] = 1865,
+	[BNXT_ULP_CLASS_HID_2aa5f] = 1866,
+	[BNXT_ULP_CLASS_HID_3355f] = 1867,
+	[BNXT_ULP_CLASS_HID_3c05f] = 1868,
+	[BNXT_ULP_CLASS_HID_21a13] = 1869,
+	[BNXT_ULP_CLASS_HID_2a513] = 1870,
+	[BNXT_ULP_CLASS_HID_33013] = 1871,
+	[BNXT_ULP_CLASS_HID_3bb13] = 1872,
+	[BNXT_ULP_CLASS_HID_22d23] = 1873,
+	[BNXT_ULP_CLASS_HID_2b823] = 1874,
+	[BNXT_ULP_CLASS_HID_34323] = 1875,
+	[BNXT_ULP_CLASS_HID_3ce23] = 1876,
+	[BNXT_ULP_CLASS_HID_25583] = 1877,
+	[BNXT_ULP_CLASS_HID_28457] = 1878,
+	[BNXT_ULP_CLASS_HID_30f57] = 1879,
+	[BNXT_ULP_CLASS_HID_39a57] = 1880,
+	[BNXT_ULP_CLASS_HID_242f3] = 1881,
+	[BNXT_ULP_CLASS_HID_2cdf3] = 1882,
+	[BNXT_ULP_CLASS_HID_358f3] = 1883,
+	[BNXT_ULP_CLASS_HID_38687] = 1884,
+	[BNXT_ULP_CLASS_HID_23d87] = 1885,
+	[BNXT_ULP_CLASS_HID_2c887] = 1886,
+	[BNXT_ULP_CLASS_HID_35387] = 1887,
+	[BNXT_ULP_CLASS_HID_3825b] = 1888,
+	[BNXT_ULP_CLASS_HID_25157] = 1889,
+	[BNXT_ULP_CLASS_HID_2dc57] = 1890,
+	[BNXT_ULP_CLASS_HID_30a6b] = 1891,
+	[BNXT_ULP_CLASS_HID_3956b] = 1892,
+	[BNXT_ULP_CLASS_HID_22c53] = 1893,
+	[BNXT_ULP_CLASS_HID_2b753] = 1894,
+	[BNXT_ULP_CLASS_HID_34253] = 1895,
+	[BNXT_ULP_CLASS_HID_3cd53] = 1896,
+	[BNXT_ULP_CLASS_HID_21883] = 1897,
+	[BNXT_ULP_CLASS_HID_2a383] = 1898,
+	[BNXT_ULP_CLASS_HID_32e83] = 1899,
+	[BNXT_ULP_CLASS_HID_3b983] = 1900,
+	[BNXT_ULP_CLASS_HID_21457] = 1901,
+	[BNXT_ULP_CLASS_HID_29f57] = 1902,
+	[BNXT_ULP_CLASS_HID_32a57] = 1903,
+	[BNXT_ULP_CLASS_HID_3b557] = 1904,
+	[BNXT_ULP_CLASS_HID_22767] = 1905,
+	[BNXT_ULP_CLASS_HID_2b267] = 1906,
+	[BNXT_ULP_CLASS_HID_33d67] = 1907,
+	[BNXT_ULP_CLASS_HID_3c867] = 1908,
+	[BNXT_ULP_CLASS_HID_24fc7] = 1909,
+	[BNXT_ULP_CLASS_HID_2dac7] = 1910,
+	[BNXT_ULP_CLASS_HID_3089b] = 1911,
+	[BNXT_ULP_CLASS_HID_3939b] = 1912,
+	[BNXT_ULP_CLASS_HID_23c37] = 1913,
+	[BNXT_ULP_CLASS_HID_2c737] = 1914,
+	[BNXT_ULP_CLASS_HID_35237] = 1915,
+	[BNXT_ULP_CLASS_HID_380cb] = 1916,
+	[BNXT_ULP_CLASS_HID_237cb] = 1917,
+	[BNXT_ULP_CLASS_HID_2c2cb] = 1918,
+	[BNXT_ULP_CLASS_HID_34dcb] = 1919,
+	[BNXT_ULP_CLASS_HID_3d8cb] = 1920,
+	[BNXT_ULP_CLASS_HID_24a9b] = 1921,
+	[BNXT_ULP_CLASS_HID_2d59b] = 1922,
+	[BNXT_ULP_CLASS_HID_303af] = 1923,
+	[BNXT_ULP_CLASS_HID_38eaf] = 1924,
+	[BNXT_ULP_CLASS_HID_253b] = 1925,
+	[BNXT_ULP_CLASS_HID_2bf7] = 1926,
+	[BNXT_ULP_CLASS_HID_4f6b] = 1927,
+	[BNXT_ULP_CLASS_HID_1653] = 1928,
+	[BNXT_ULP_CLASS_HID_39c7] = 1929,
+	[BNXT_ULP_CLASS_HID_48af] = 1930,
+	[BNXT_ULP_CLASS_HID_0f97] = 1931,
+	[BNXT_ULP_CLASS_HID_330b] = 1932,
+	[BNXT_ULP_CLASS_HID_374e] = 1933,
+	[BNXT_ULP_CLASS_HID_11ee] = 1934,
+	[BNXT_ULP_CLASS_HID_423a] = 1935,
+	[BNXT_ULP_CLASS_HID_0cd6] = 1936,
+	[BNXT_ULP_CLASS_HID_310a] = 1937,
+	[BNXT_ULP_CLASS_HID_469e] = 1938,
+	[BNXT_ULP_CLASS_HID_5ce6] = 1939,
+	[BNXT_ULP_CLASS_HID_0692] = 1940,
+	[BNXT_ULP_CLASS_HID_1c7e] = 1941,
+	[BNXT_ULP_CLASS_HID_55c2] = 1942,
+	[BNXT_ULP_CLASS_HID_2b2a] = 1943,
+	[BNXT_ULP_CLASS_HID_15c6] = 1944,
+	[BNXT_ULP_CLASS_HID_163a] = 1945,
+	[BNXT_ULP_CLASS_HID_2f8e] = 1946,
+	[BNXT_ULP_CLASS_HID_2516] = 1947,
+	[BNXT_ULP_CLASS_HID_4b76] = 1948,
+	[BNXT_ULP_CLASS_HID_10e6] = 1949,
+	[BNXT_ULP_CLASS_HID_264a] = 1950,
+	[BNXT_ULP_CLASS_HID_3fd2] = 1951,
+	[BNXT_ULP_CLASS_HID_4532] = 1952,
+	[BNXT_ULP_CLASS_HID_4996] = 1953,
+	[BNXT_ULP_CLASS_HID_2036] = 1954,
+	[BNXT_ULP_CLASS_HID_399e] = 1955,
+	[BNXT_ULP_CLASS_HID_5ffe] = 1956,
+	[BNXT_ULP_CLASS_HID_34fe] = 1957,
+	[BNXT_ULP_CLASS_HID_3a32] = 1958,
+	[BNXT_ULP_CLASS_HID_376e] = 1959,
+	[BNXT_ULP_CLASS_HID_12d6e] = 1960,
+	[BNXT_ULP_CLASS_HID_2436e] = 1961,
+	[BNXT_ULP_CLASS_HID_31dba] = 1962,
+	[BNXT_ULP_CLASS_HID_11ce] = 1963,
+	[BNXT_ULP_CLASS_HID_107ce] = 1964,
+	[BNXT_ULP_CLASS_HID_23dce] = 1965,
+	[BNXT_ULP_CLASS_HID_353ce] = 1966,
+	[BNXT_ULP_CLASS_HID_421a] = 1967,
+	[BNXT_ULP_CLASS_HID_11d56] = 1968,
+	[BNXT_ULP_CLASS_HID_23356] = 1969,
+	[BNXT_ULP_CLASS_HID_32956] = 1970,
+	[BNXT_ULP_CLASS_HID_0cf6] = 1971,
+	[BNXT_ULP_CLASS_HID_122f6] = 1972,
+	[BNXT_ULP_CLASS_HID_258f6] = 1973,
+	[BNXT_ULP_CLASS_HID_313c2] = 1974,
+	[BNXT_ULP_CLASS_HID_312a] = 1975,
+	[BNXT_ULP_CLASS_HID_1272a] = 1976,
+	[BNXT_ULP_CLASS_HID_25d2a] = 1977,
+	[BNXT_ULP_CLASS_HID_31466] = 1978,
+	[BNXT_ULP_CLASS_HID_46be] = 1979,
+	[BNXT_ULP_CLASS_HID_1018a] = 1980,
+	[BNXT_ULP_CLASS_HID_2378a] = 1981,
+	[BNXT_ULP_CLASS_HID_32d8a] = 1982,
+	[BNXT_ULP_CLASS_HID_5cc6] = 1983,
+	[BNXT_ULP_CLASS_HID_11712] = 1984,
+	[BNXT_ULP_CLASS_HID_20d12] = 1985,
+	[BNXT_ULP_CLASS_HID_32312] = 1986,
+	[BNXT_ULP_CLASS_HID_06b2] = 1987,
+	[BNXT_ULP_CLASS_HID_13cb2] = 1988,
+	[BNXT_ULP_CLASS_HID_252b2] = 1989,
+	[BNXT_ULP_CLASS_HID_348b2] = 1990,
+	[BNXT_ULP_CLASS_HID_1c5e] = 1991,
+	[BNXT_ULP_CLASS_HID_1325e] = 1992,
+	[BNXT_ULP_CLASS_HID_2285e] = 1993,
+	[BNXT_ULP_CLASS_HID_35e5e] = 1994,
+	[BNXT_ULP_CLASS_HID_55e2] = 1995,
+	[BNXT_ULP_CLASS_HID_14be2] = 1996,
+	[BNXT_ULP_CLASS_HID_2023e] = 1997,
+	[BNXT_ULP_CLASS_HID_3383e] = 1998,
+	[BNXT_ULP_CLASS_HID_2b0a] = 1999,
+	[BNXT_ULP_CLASS_HID_1410a] = 2000,
+	[BNXT_ULP_CLASS_HID_21846] = 2001,
+	[BNXT_ULP_CLASS_HID_30e46] = 2002,
+	[BNXT_ULP_CLASS_HID_15e6] = 2003,
+	[BNXT_ULP_CLASS_HID_10be6] = 2004,
+	[BNXT_ULP_CLASS_HID_221e6] = 2005,
+	[BNXT_ULP_CLASS_HID_357e6] = 2006,
+	[BNXT_ULP_CLASS_HID_161a] = 2007,
+	[BNXT_ULP_CLASS_HID_10c1a] = 2008,
+	[BNXT_ULP_CLASS_HID_2221a] = 2009,
+	[BNXT_ULP_CLASS_HID_3581a] = 2010,
+	[BNXT_ULP_CLASS_HID_2fae] = 2011,
+	[BNXT_ULP_CLASS_HID_145ae] = 2012,
+	[BNXT_ULP_CLASS_HID_21cfa] = 2013,
+	[BNXT_ULP_CLASS_HID_332fa] = 2014,
+	[BNXT_ULP_CLASS_HID_2536] = 2015,
+	[BNXT_ULP_CLASS_HID_15b36] = 2016,
+	[BNXT_ULP_CLASS_HID_21202] = 2017,
+	[BNXT_ULP_CLASS_HID_30802] = 2018,
+	[BNXT_ULP_CLASS_HID_4b56] = 2019,
+	[BNXT_ULP_CLASS_HID_105a2] = 2020,
+	[BNXT_ULP_CLASS_HID_23ba2] = 2021,
+	[BNXT_ULP_CLASS_HID_351a2] = 2022,
+	[BNXT_ULP_CLASS_HID_10c6] = 2023,
+	[BNXT_ULP_CLASS_HID_106c6] = 2024,
+	[BNXT_ULP_CLASS_HID_23cc6] = 2025,
+	[BNXT_ULP_CLASS_HID_352c6] = 2026,
+	[BNXT_ULP_CLASS_HID_266a] = 2027,
+	[BNXT_ULP_CLASS_HID_15c6a] = 2028,
+	[BNXT_ULP_CLASS_HID_216a6] = 2029,
+	[BNXT_ULP_CLASS_HID_30ca6] = 2030,
+	[BNXT_ULP_CLASS_HID_3ff2] = 2031,
+	[BNXT_ULP_CLASS_HID_155f2] = 2032,
+	[BNXT_ULP_CLASS_HID_24bf2] = 2033,
+	[BNXT_ULP_CLASS_HID_302ce] = 2034,
+	[BNXT_ULP_CLASS_HID_4512] = 2035,
+	[BNXT_ULP_CLASS_HID_11c6e] = 2036,
+	[BNXT_ULP_CLASS_HID_2326e] = 2037,
+	[BNXT_ULP_CLASS_HID_3286e] = 2038,
+	[BNXT_ULP_CLASS_HID_49b6] = 2039,
+	[BNXT_ULP_CLASS_HID_10082] = 2040,
+	[BNXT_ULP_CLASS_HID_23682] = 2041,
+	[BNXT_ULP_CLASS_HID_32c82] = 2042,
+	[BNXT_ULP_CLASS_HID_2016] = 2043,
+	[BNXT_ULP_CLASS_HID_15616] = 2044,
+	[BNXT_ULP_CLASS_HID_21162] = 2045,
+	[BNXT_ULP_CLASS_HID_30762] = 2046,
+	[BNXT_ULP_CLASS_HID_39be] = 2047,
+	[BNXT_ULP_CLASS_HID_12fbe] = 2048,
+	[BNXT_ULP_CLASS_HID_245be] = 2049,
+	[BNXT_ULP_CLASS_HID_31c8a] = 2050,
+	[BNXT_ULP_CLASS_HID_5fde] = 2051,
+	[BNXT_ULP_CLASS_HID_1162a] = 2052,
+	[BNXT_ULP_CLASS_HID_20c2a] = 2053,
+	[BNXT_ULP_CLASS_HID_3222a] = 2054,
+	[BNXT_ULP_CLASS_HID_34de] = 2055,
+	[BNXT_ULP_CLASS_HID_3a12] = 2056,
+	[BNXT_ULP_CLASS_HID_370e] = 2057,
+	[BNXT_ULP_CLASS_HID_12d0e] = 2058,
+	[BNXT_ULP_CLASS_HID_2430e] = 2059,
+	[BNXT_ULP_CLASS_HID_31dda] = 2060,
+	[BNXT_ULP_CLASS_HID_11ae] = 2061,
+	[BNXT_ULP_CLASS_HID_107ae] = 2062,
+	[BNXT_ULP_CLASS_HID_23dae] = 2063,
+	[BNXT_ULP_CLASS_HID_353ae] = 2064,
+	[BNXT_ULP_CLASS_HID_427a] = 2065,
+	[BNXT_ULP_CLASS_HID_11d36] = 2066,
+	[BNXT_ULP_CLASS_HID_23336] = 2067,
+	[BNXT_ULP_CLASS_HID_32936] = 2068,
+	[BNXT_ULP_CLASS_HID_0c96] = 2069,
+	[BNXT_ULP_CLASS_HID_12296] = 2070,
+	[BNXT_ULP_CLASS_HID_25896] = 2071,
+	[BNXT_ULP_CLASS_HID_313a2] = 2072,
+	[BNXT_ULP_CLASS_HID_314a] = 2073,
+	[BNXT_ULP_CLASS_HID_1274a] = 2074,
+	[BNXT_ULP_CLASS_HID_25d4a] = 2075,
+	[BNXT_ULP_CLASS_HID_31406] = 2076,
+	[BNXT_ULP_CLASS_HID_46de] = 2077,
+	[BNXT_ULP_CLASS_HID_101ea] = 2078,
+	[BNXT_ULP_CLASS_HID_237ea] = 2079,
+	[BNXT_ULP_CLASS_HID_32dea] = 2080,
+	[BNXT_ULP_CLASS_HID_5ca6] = 2081,
+	[BNXT_ULP_CLASS_HID_11772] = 2082,
+	[BNXT_ULP_CLASS_HID_20d72] = 2083,
+	[BNXT_ULP_CLASS_HID_32372] = 2084,
+	[BNXT_ULP_CLASS_HID_06d2] = 2085,
+	[BNXT_ULP_CLASS_HID_13cd2] = 2086,
+	[BNXT_ULP_CLASS_HID_252d2] = 2087,
+	[BNXT_ULP_CLASS_HID_348d2] = 2088,
+	[BNXT_ULP_CLASS_HID_1c3e] = 2089,
+	[BNXT_ULP_CLASS_HID_1323e] = 2090,
+	[BNXT_ULP_CLASS_HID_2283e] = 2091,
+	[BNXT_ULP_CLASS_HID_35e3e] = 2092,
+	[BNXT_ULP_CLASS_HID_5582] = 2093,
+	[BNXT_ULP_CLASS_HID_14b82] = 2094,
+	[BNXT_ULP_CLASS_HID_2025e] = 2095,
+	[BNXT_ULP_CLASS_HID_3385e] = 2096,
+	[BNXT_ULP_CLASS_HID_2b6a] = 2097,
+	[BNXT_ULP_CLASS_HID_1416a] = 2098,
+	[BNXT_ULP_CLASS_HID_21826] = 2099,
+	[BNXT_ULP_CLASS_HID_30e26] = 2100,
+	[BNXT_ULP_CLASS_HID_1586] = 2101,
+	[BNXT_ULP_CLASS_HID_10b86] = 2102,
+	[BNXT_ULP_CLASS_HID_22186] = 2103,
+	[BNXT_ULP_CLASS_HID_35786] = 2104,
+	[BNXT_ULP_CLASS_HID_167a] = 2105,
+	[BNXT_ULP_CLASS_HID_10c7a] = 2106,
+	[BNXT_ULP_CLASS_HID_2227a] = 2107,
+	[BNXT_ULP_CLASS_HID_3587a] = 2108,
+	[BNXT_ULP_CLASS_HID_2fce] = 2109,
+	[BNXT_ULP_CLASS_HID_145ce] = 2110,
+	[BNXT_ULP_CLASS_HID_21c9a] = 2111,
+	[BNXT_ULP_CLASS_HID_3329a] = 2112,
+	[BNXT_ULP_CLASS_HID_2556] = 2113,
+	[BNXT_ULP_CLASS_HID_15b56] = 2114,
+	[BNXT_ULP_CLASS_HID_21262] = 2115,
+	[BNXT_ULP_CLASS_HID_30862] = 2116,
+	[BNXT_ULP_CLASS_HID_4b36] = 2117,
+	[BNXT_ULP_CLASS_HID_105c2] = 2118,
+	[BNXT_ULP_CLASS_HID_23bc2] = 2119,
+	[BNXT_ULP_CLASS_HID_351c2] = 2120,
+	[BNXT_ULP_CLASS_HID_10a6] = 2121,
+	[BNXT_ULP_CLASS_HID_106a6] = 2122,
+	[BNXT_ULP_CLASS_HID_23ca6] = 2123,
+	[BNXT_ULP_CLASS_HID_352a6] = 2124,
+	[BNXT_ULP_CLASS_HID_260a] = 2125,
+	[BNXT_ULP_CLASS_HID_15c0a] = 2126,
+	[BNXT_ULP_CLASS_HID_216c6] = 2127,
+	[BNXT_ULP_CLASS_HID_30cc6] = 2128,
+	[BNXT_ULP_CLASS_HID_3f92] = 2129,
+	[BNXT_ULP_CLASS_HID_15592] = 2130,
+	[BNXT_ULP_CLASS_HID_24b92] = 2131,
+	[BNXT_ULP_CLASS_HID_302ae] = 2132,
+	[BNXT_ULP_CLASS_HID_4572] = 2133,
+	[BNXT_ULP_CLASS_HID_11c0e] = 2134,
+	[BNXT_ULP_CLASS_HID_2320e] = 2135,
+	[BNXT_ULP_CLASS_HID_3280e] = 2136,
+	[BNXT_ULP_CLASS_HID_49d6] = 2137,
+	[BNXT_ULP_CLASS_HID_100e2] = 2138,
+	[BNXT_ULP_CLASS_HID_236e2] = 2139,
+	[BNXT_ULP_CLASS_HID_32ce2] = 2140,
+	[BNXT_ULP_CLASS_HID_2076] = 2141,
+	[BNXT_ULP_CLASS_HID_15676] = 2142,
+	[BNXT_ULP_CLASS_HID_21102] = 2143,
+	[BNXT_ULP_CLASS_HID_30702] = 2144,
+	[BNXT_ULP_CLASS_HID_39de] = 2145,
+	[BNXT_ULP_CLASS_HID_12fde] = 2146,
+	[BNXT_ULP_CLASS_HID_245de] = 2147,
+	[BNXT_ULP_CLASS_HID_31cea] = 2148,
+	[BNXT_ULP_CLASS_HID_5fbe] = 2149,
+	[BNXT_ULP_CLASS_HID_1164a] = 2150,
+	[BNXT_ULP_CLASS_HID_20c4a] = 2151,
+	[BNXT_ULP_CLASS_HID_3224a] = 2152,
+	[BNXT_ULP_CLASS_HID_34be] = 2153,
+	[BNXT_ULP_CLASS_HID_3a72] = 2154,
+	[BNXT_ULP_CLASS_HID_09ea] = 2155,
+	[BNXT_ULP_CLASS_HID_2912] = 2156,
+	[BNXT_ULP_CLASS_HID_03b2] = 2157,
+	[BNXT_ULP_CLASS_HID_5f7e] = 2158,
+	[BNXT_ULP_CLASS_HID_03a6] = 2159,
+	[BNXT_ULP_CLASS_HID_23ce] = 2160,
+	[BNXT_ULP_CLASS_HID_1a6e] = 2161,
+	[BNXT_ULP_CLASS_HID_593a] = 2162,
+	[BNXT_ULP_CLASS_HID_4dce] = 2163,
+	[BNXT_ULP_CLASS_HID_0e02] = 2164,
+	[BNXT_ULP_CLASS_HID_4796] = 2165,
+	[BNXT_ULP_CLASS_HID_246e] = 2166,
+	[BNXT_ULP_CLASS_HID_478a] = 2167,
+	[BNXT_ULP_CLASS_HID_08fe] = 2168,
+	[BNXT_ULP_CLASS_HID_5e52] = 2169,
+	[BNXT_ULP_CLASS_HID_3e2a] = 2170,
+	[BNXT_ULP_CLASS_HID_5e46] = 2171,
+	[BNXT_ULP_CLASS_HID_02ba] = 2172,
+	[BNXT_ULP_CLASS_HID_580e] = 2173,
+	[BNXT_ULP_CLASS_HID_38e6] = 2174,
+	[BNXT_ULP_CLASS_HID_5802] = 2175,
+	[BNXT_ULP_CLASS_HID_1d76] = 2176,
+	[BNXT_ULP_CLASS_HID_52ca] = 2177,
+	[BNXT_ULP_CLASS_HID_32a2] = 2178,
+	[BNXT_ULP_CLASS_HID_34f6] = 2179,
+	[BNXT_ULP_CLASS_HID_3a3a] = 2180,
+	[BNXT_ULP_CLASS_HID_09ca] = 2181,
+	[BNXT_ULP_CLASS_HID_0216] = 2182,
+	[BNXT_ULP_CLASS_HID_1f62] = 2183,
+	[BNXT_ULP_CLASS_HID_1bae] = 2184,
+	[BNXT_ULP_CLASS_HID_2932] = 2185,
+	[BNXT_ULP_CLASS_HID_227e] = 2186,
+	[BNXT_ULP_CLASS_HID_3f4a] = 2187,
+	[BNXT_ULP_CLASS_HID_3b96] = 2188,
+	[BNXT_ULP_CLASS_HID_0392] = 2189,
+	[BNXT_ULP_CLASS_HID_1cde] = 2190,
+	[BNXT_ULP_CLASS_HID_192a] = 2191,
+	[BNXT_ULP_CLASS_HID_1276] = 2192,
+	[BNXT_ULP_CLASS_HID_5f5e] = 2193,
+	[BNXT_ULP_CLASS_HID_5baa] = 2194,
+	[BNXT_ULP_CLASS_HID_54f6] = 2195,
+	[BNXT_ULP_CLASS_HID_51c2] = 2196,
+	[BNXT_ULP_CLASS_HID_0386] = 2197,
+	[BNXT_ULP_CLASS_HID_1cd2] = 2198,
+	[BNXT_ULP_CLASS_HID_191e] = 2199,
+	[BNXT_ULP_CLASS_HID_126a] = 2200,
+	[BNXT_ULP_CLASS_HID_23ee] = 2201,
+	[BNXT_ULP_CLASS_HID_3c3a] = 2202,
+	[BNXT_ULP_CLASS_HID_3906] = 2203,
+	[BNXT_ULP_CLASS_HID_3252] = 2204,
+	[BNXT_ULP_CLASS_HID_1a4e] = 2205,
+	[BNXT_ULP_CLASS_HID_169a] = 2206,
+	[BNXT_ULP_CLASS_HID_13e6] = 2207,
+	[BNXT_ULP_CLASS_HID_4be6] = 2208,
+	[BNXT_ULP_CLASS_HID_591a] = 2209,
+	[BNXT_ULP_CLASS_HID_5266] = 2210,
+	[BNXT_ULP_CLASS_HID_2eb2] = 2211,
+	[BNXT_ULP_CLASS_HID_2bfe] = 2212,
+	[BNXT_ULP_CLASS_HID_4dee] = 2213,
+	[BNXT_ULP_CLASS_HID_463a] = 2214,
+	[BNXT_ULP_CLASS_HID_4306] = 2215,
+	[BNXT_ULP_CLASS_HID_5c52] = 2216,
+	[BNXT_ULP_CLASS_HID_0e22] = 2217,
+	[BNXT_ULP_CLASS_HID_0b6e] = 2218,
+	[BNXT_ULP_CLASS_HID_07ba] = 2219,
+	[BNXT_ULP_CLASS_HID_0086] = 2220,
+	[BNXT_ULP_CLASS_HID_47b6] = 2221,
+	[BNXT_ULP_CLASS_HID_4082] = 2222,
+	[BNXT_ULP_CLASS_HID_5dce] = 2223,
+	[BNXT_ULP_CLASS_HID_561a] = 2224,
+	[BNXT_ULP_CLASS_HID_244e] = 2225,
+	[BNXT_ULP_CLASS_HID_209a] = 2226,
+	[BNXT_ULP_CLASS_HID_3de6] = 2227,
+	[BNXT_ULP_CLASS_HID_3632] = 2228,
+	[BNXT_ULP_CLASS_HID_47aa] = 2229,
+	[BNXT_ULP_CLASS_HID_40f6] = 2230,
+	[BNXT_ULP_CLASS_HID_5dc2] = 2231,
+	[BNXT_ULP_CLASS_HID_560e] = 2232,
+	[BNXT_ULP_CLASS_HID_08de] = 2233,
+	[BNXT_ULP_CLASS_HID_052a] = 2234,
+	[BNXT_ULP_CLASS_HID_1e76] = 2235,
+	[BNXT_ULP_CLASS_HID_1b42] = 2236,
+	[BNXT_ULP_CLASS_HID_5e72] = 2237,
+	[BNXT_ULP_CLASS_HID_5abe] = 2238,
+	[BNXT_ULP_CLASS_HID_578a] = 2239,
+	[BNXT_ULP_CLASS_HID_50d6] = 2240,
+	[BNXT_ULP_CLASS_HID_3e0a] = 2241,
+	[BNXT_ULP_CLASS_HID_3b56] = 2242,
+	[BNXT_ULP_CLASS_HID_37a2] = 2243,
+	[BNXT_ULP_CLASS_HID_30ee] = 2244,
+	[BNXT_ULP_CLASS_HID_5e66] = 2245,
+	[BNXT_ULP_CLASS_HID_5ab2] = 2246,
+	[BNXT_ULP_CLASS_HID_57fe] = 2247,
+	[BNXT_ULP_CLASS_HID_50ca] = 2248,
+	[BNXT_ULP_CLASS_HID_029a] = 2249,
+	[BNXT_ULP_CLASS_HID_1fe6] = 2250,
+	[BNXT_ULP_CLASS_HID_1832] = 2251,
+	[BNXT_ULP_CLASS_HID_157e] = 2252,
+	[BNXT_ULP_CLASS_HID_582e] = 2253,
+	[BNXT_ULP_CLASS_HID_557a] = 2254,
+	[BNXT_ULP_CLASS_HID_2e46] = 2255,
+	[BNXT_ULP_CLASS_HID_2a92] = 2256,
+	[BNXT_ULP_CLASS_HID_38c6] = 2257,
+	[BNXT_ULP_CLASS_HID_3512] = 2258,
+	[BNXT_ULP_CLASS_HID_0e5e] = 2259,
+	[BNXT_ULP_CLASS_HID_0aaa] = 2260,
+	[BNXT_ULP_CLASS_HID_5822] = 2261,
+	[BNXT_ULP_CLASS_HID_556e] = 2262,
+	[BNXT_ULP_CLASS_HID_51ba] = 2263,
+	[BNXT_ULP_CLASS_HID_2a86] = 2264,
+	[BNXT_ULP_CLASS_HID_1d56] = 2265,
+	[BNXT_ULP_CLASS_HID_19a2] = 2266,
+	[BNXT_ULP_CLASS_HID_12ee] = 2267,
+	[BNXT_ULP_CLASS_HID_4aee] = 2268,
+	[BNXT_ULP_CLASS_HID_52ea] = 2269,
+	[BNXT_ULP_CLASS_HID_2f36] = 2270,
+	[BNXT_ULP_CLASS_HID_2802] = 2271,
+	[BNXT_ULP_CLASS_HID_254e] = 2272,
+	[BNXT_ULP_CLASS_HID_3282] = 2273,
+	[BNXT_ULP_CLASS_HID_0fce] = 2274,
+	[BNXT_ULP_CLASS_HID_081a] = 2275,
+	[BNXT_ULP_CLASS_HID_0566] = 2276,
+	[BNXT_ULP_CLASS_HID_34d6] = 2277,
+	[BNXT_ULP_CLASS_HID_3a1a] = 2278,
+	[BNXT_ULP_CLASS_HID_09aa] = 2279,
+	[BNXT_ULP_CLASS_HID_0276] = 2280,
+	[BNXT_ULP_CLASS_HID_1f02] = 2281,
+	[BNXT_ULP_CLASS_HID_1bce] = 2282,
+	[BNXT_ULP_CLASS_HID_2952] = 2283,
+	[BNXT_ULP_CLASS_HID_221e] = 2284,
+	[BNXT_ULP_CLASS_HID_3f2a] = 2285,
+	[BNXT_ULP_CLASS_HID_3bf6] = 2286,
+	[BNXT_ULP_CLASS_HID_03f2] = 2287,
+	[BNXT_ULP_CLASS_HID_1cbe] = 2288,
+	[BNXT_ULP_CLASS_HID_194a] = 2289,
+	[BNXT_ULP_CLASS_HID_1216] = 2290,
+	[BNXT_ULP_CLASS_HID_5f3e] = 2291,
+	[BNXT_ULP_CLASS_HID_5bca] = 2292,
+	[BNXT_ULP_CLASS_HID_5496] = 2293,
+	[BNXT_ULP_CLASS_HID_51a2] = 2294,
+	[BNXT_ULP_CLASS_HID_03e6] = 2295,
+	[BNXT_ULP_CLASS_HID_1cb2] = 2296,
+	[BNXT_ULP_CLASS_HID_197e] = 2297,
+	[BNXT_ULP_CLASS_HID_120a] = 2298,
+	[BNXT_ULP_CLASS_HID_238e] = 2299,
+	[BNXT_ULP_CLASS_HID_3c5a] = 2300,
+	[BNXT_ULP_CLASS_HID_3966] = 2301,
+	[BNXT_ULP_CLASS_HID_3232] = 2302,
+	[BNXT_ULP_CLASS_HID_1a2e] = 2303,
+	[BNXT_ULP_CLASS_HID_16fa] = 2304,
+	[BNXT_ULP_CLASS_HID_1386] = 2305,
+	[BNXT_ULP_CLASS_HID_4b86] = 2306,
+	[BNXT_ULP_CLASS_HID_597a] = 2307,
+	[BNXT_ULP_CLASS_HID_5206] = 2308,
+	[BNXT_ULP_CLASS_HID_2ed2] = 2309,
+	[BNXT_ULP_CLASS_HID_2b9e] = 2310,
+	[BNXT_ULP_CLASS_HID_4d8e] = 2311,
+	[BNXT_ULP_CLASS_HID_465a] = 2312,
+	[BNXT_ULP_CLASS_HID_4366] = 2313,
+	[BNXT_ULP_CLASS_HID_5c32] = 2314,
+	[BNXT_ULP_CLASS_HID_0e42] = 2315,
+	[BNXT_ULP_CLASS_HID_0b0e] = 2316,
+	[BNXT_ULP_CLASS_HID_07da] = 2317,
+	[BNXT_ULP_CLASS_HID_00e6] = 2318,
+	[BNXT_ULP_CLASS_HID_47d6] = 2319,
+	[BNXT_ULP_CLASS_HID_40e2] = 2320,
+	[BNXT_ULP_CLASS_HID_5dae] = 2321,
+	[BNXT_ULP_CLASS_HID_567a] = 2322,
+	[BNXT_ULP_CLASS_HID_242e] = 2323,
+	[BNXT_ULP_CLASS_HID_20fa] = 2324,
+	[BNXT_ULP_CLASS_HID_3d86] = 2325,
+	[BNXT_ULP_CLASS_HID_3652] = 2326,
+	[BNXT_ULP_CLASS_HID_47ca] = 2327,
+	[BNXT_ULP_CLASS_HID_4096] = 2328,
+	[BNXT_ULP_CLASS_HID_5da2] = 2329,
+	[BNXT_ULP_CLASS_HID_566e] = 2330,
+	[BNXT_ULP_CLASS_HID_08be] = 2331,
+	[BNXT_ULP_CLASS_HID_054a] = 2332,
+	[BNXT_ULP_CLASS_HID_1e16] = 2333,
+	[BNXT_ULP_CLASS_HID_1b22] = 2334,
+	[BNXT_ULP_CLASS_HID_5e12] = 2335,
+	[BNXT_ULP_CLASS_HID_5ade] = 2336,
+	[BNXT_ULP_CLASS_HID_57ea] = 2337,
+	[BNXT_ULP_CLASS_HID_50b6] = 2338,
+	[BNXT_ULP_CLASS_HID_3e6a] = 2339,
+	[BNXT_ULP_CLASS_HID_3b36] = 2340,
+	[BNXT_ULP_CLASS_HID_37c2] = 2341,
+	[BNXT_ULP_CLASS_HID_308e] = 2342,
+	[BNXT_ULP_CLASS_HID_5e06] = 2343,
+	[BNXT_ULP_CLASS_HID_5ad2] = 2344,
+	[BNXT_ULP_CLASS_HID_579e] = 2345,
+	[BNXT_ULP_CLASS_HID_50aa] = 2346,
+	[BNXT_ULP_CLASS_HID_02fa] = 2347,
+	[BNXT_ULP_CLASS_HID_1f86] = 2348,
+	[BNXT_ULP_CLASS_HID_1852] = 2349,
+	[BNXT_ULP_CLASS_HID_151e] = 2350,
+	[BNXT_ULP_CLASS_HID_584e] = 2351,
+	[BNXT_ULP_CLASS_HID_551a] = 2352,
+	[BNXT_ULP_CLASS_HID_2e26] = 2353,
+	[BNXT_ULP_CLASS_HID_2af2] = 2354,
+	[BNXT_ULP_CLASS_HID_38a6] = 2355,
+	[BNXT_ULP_CLASS_HID_3572] = 2356,
+	[BNXT_ULP_CLASS_HID_0e3e] = 2357,
+	[BNXT_ULP_CLASS_HID_0aca] = 2358,
+	[BNXT_ULP_CLASS_HID_5842] = 2359,
+	[BNXT_ULP_CLASS_HID_550e] = 2360,
+	[BNXT_ULP_CLASS_HID_51da] = 2361,
+	[BNXT_ULP_CLASS_HID_2ae6] = 2362,
+	[BNXT_ULP_CLASS_HID_1d36] = 2363,
+	[BNXT_ULP_CLASS_HID_19c2] = 2364,
+	[BNXT_ULP_CLASS_HID_128e] = 2365,
+	[BNXT_ULP_CLASS_HID_4a8e] = 2366,
+	[BNXT_ULP_CLASS_HID_528a] = 2367,
+	[BNXT_ULP_CLASS_HID_2f56] = 2368,
+	[BNXT_ULP_CLASS_HID_2862] = 2369,
+	[BNXT_ULP_CLASS_HID_252e] = 2370,
+	[BNXT_ULP_CLASS_HID_32e2] = 2371,
+	[BNXT_ULP_CLASS_HID_0fae] = 2372,
+	[BNXT_ULP_CLASS_HID_087a] = 2373,
+	[BNXT_ULP_CLASS_HID_0506] = 2374,
+	[BNXT_ULP_CLASS_HID_34b6] = 2375,
+	[BNXT_ULP_CLASS_HID_3a7a] = 2376,
+	[BNXT_ULP_CLASS_HID_a73c] = 2377,
+	[BNXT_ULP_CLASS_HID_a040] = 2378,
+	[BNXT_ULP_CLASS_HID_1d640] = 2379,
+	[BNXT_ULP_CLASS_HID_1dd3c] = 2380,
+	[BNXT_ULP_CLASS_HID_cba0] = 2381,
+	[BNXT_ULP_CLASS_HID_c4f4] = 2382,
+	[BNXT_ULP_CLASS_HID_19f38] = 2383,
+	[BNXT_ULP_CLASS_HID_182f4] = 2384,
+	[BNXT_ULP_CLASS_HID_b098] = 2385,
+	[BNXT_ULP_CLASS_HID_8dac] = 2386,
+	[BNXT_ULP_CLASS_HID_1a3ac] = 2387,
+	[BNXT_ULP_CLASS_HID_1a698] = 2388,
+	[BNXT_ULP_CLASS_HID_d50c] = 2389,
+	[BNXT_ULP_CLASS_HID_ae50] = 2390,
+	[BNXT_ULP_CLASS_HID_1c450] = 2391,
+	[BNXT_ULP_CLASS_HID_1cb0c] = 2392,
+	[BNXT_ULP_CLASS_HID_a1f0] = 2393,
+	[BNXT_ULP_CLASS_HID_ba04] = 2394,
+	[BNXT_ULP_CLASS_HID_1d004] = 2395,
+	[BNXT_ULP_CLASS_HID_1d7f0] = 2396,
+	[BNXT_ULP_CLASS_HID_c264] = 2397,
+	[BNXT_ULP_CLASS_HID_dea8] = 2398,
+	[BNXT_ULP_CLASS_HID_199fc] = 2399,
+	[BNXT_ULP_CLASS_HID_19ca8] = 2400,
+	[BNXT_ULP_CLASS_HID_8b5c] = 2401,
+	[BNXT_ULP_CLASS_HID_8460] = 2402,
+	[BNXT_ULP_CLASS_HID_1ba60] = 2403,
+	[BNXT_ULP_CLASS_HID_1a15c] = 2404,
+	[BNXT_ULP_CLASS_HID_afc0] = 2405,
+	[BNXT_ULP_CLASS_HID_a814] = 2406,
+	[BNXT_ULP_CLASS_HID_1de14] = 2407,
+	[BNXT_ULP_CLASS_HID_1c5c0] = 2408,
+	[BNXT_ULP_CLASS_HID_8c2c] = 2409,
+	[BNXT_ULP_CLASS_HID_8970] = 2410,
+	[BNXT_ULP_CLASS_HID_1bf70] = 2411,
+	[BNXT_ULP_CLASS_HID_1a22c] = 2412,
+	[BNXT_ULP_CLASS_HID_d0d0] = 2413,
+	[BNXT_ULP_CLASS_HID_ade4] = 2414,
+	[BNXT_ULP_CLASS_HID_1c3e4] = 2415,
+	[BNXT_ULP_CLASS_HID_1c6d0] = 2416,
+	[BNXT_ULP_CLASS_HID_9988] = 2417,
+	[BNXT_ULP_CLASS_HID_92dc] = 2418,
+	[BNXT_ULP_CLASS_HID_188dc] = 2419,
+	[BNXT_ULP_CLASS_HID_18f88] = 2420,
+	[BNXT_ULP_CLASS_HID_ba3c] = 2421,
+	[BNXT_ULP_CLASS_HID_b740] = 2422,
+	[BNXT_ULP_CLASS_HID_1ad40] = 2423,
+	[BNXT_ULP_CLASS_HID_1d03c] = 2424,
+	[BNXT_ULP_CLASS_HID_86e0] = 2425,
+	[BNXT_ULP_CLASS_HID_8334] = 2426,
+	[BNXT_ULP_CLASS_HID_1b934] = 2427,
+	[BNXT_ULP_CLASS_HID_1bce0] = 2428,
+	[BNXT_ULP_CLASS_HID_aa94] = 2429,
+	[BNXT_ULP_CLASS_HID_a7d8] = 2430,
+	[BNXT_ULP_CLASS_HID_1ddd8] = 2431,
+	[BNXT_ULP_CLASS_HID_1c094] = 2432,
+	[BNXT_ULP_CLASS_HID_904c] = 2433,
+	[BNXT_ULP_CLASS_HID_c84c] = 2434,
+	[BNXT_ULP_CLASS_HID_18290] = 2435,
+	[BNXT_ULP_CLASS_HID_1864c] = 2436,
+	[BNXT_ULP_CLASS_HID_b4f0] = 2437,
+	[BNXT_ULP_CLASS_HID_b104] = 2438,
+	[BNXT_ULP_CLASS_HID_1a704] = 2439,
+	[BNXT_ULP_CLASS_HID_1aaf0] = 2440,
+	[BNXT_ULP_CLASS_HID_80a4] = 2441,
+	[BNXT_ULP_CLASS_HID_9de8] = 2442,
+	[BNXT_ULP_CLASS_HID_1b3e8] = 2443,
+	[BNXT_ULP_CLASS_HID_1b6a4] = 2444,
+	[BNXT_ULP_CLASS_HID_a548] = 2445,
+	[BNXT_ULP_CLASS_HID_a19c] = 2446,
+	[BNXT_ULP_CLASS_HID_1d79c] = 2447,
+	[BNXT_ULP_CLASS_HID_1db48] = 2448,
+	[BNXT_ULP_CLASS_HID_9a98] = 2449,
+	[BNXT_ULP_CLASS_HID_97ac] = 2450,
+	[BNXT_ULP_CLASS_HID_18dac] = 2451,
+	[BNXT_ULP_CLASS_HID_1b098] = 2452,
+	[BNXT_ULP_CLASS_HID_bf0c] = 2453,
+	[BNXT_ULP_CLASS_HID_b850] = 2454,
+	[BNXT_ULP_CLASS_HID_1ae50] = 2455,
+	[BNXT_ULP_CLASS_HID_1d50c] = 2456,
+	[BNXT_ULP_CLASS_HID_34f0] = 2457,
+	[BNXT_ULP_CLASS_HID_3a3c] = 2458,
+	[BNXT_ULP_CLASS_HID_5ea0] = 2459,
+	[BNXT_ULP_CLASS_HID_0798] = 2460,
+	[BNXT_ULP_CLASS_HID_280c] = 2461,
+	[BNXT_ULP_CLASS_HID_5964] = 2462,
+	[BNXT_ULP_CLASS_HID_1e5c] = 2463,
+	[BNXT_ULP_CLASS_HID_22c0] = 2464,
+	[BNXT_ULP_CLASS_HID_a71c] = 2465,
+	[BNXT_ULP_CLASS_HID_a8dc] = 2466,
+	[BNXT_ULP_CLASS_HID_ed9c] = 2467,
+	[BNXT_ULP_CLASS_HID_ef5c] = 2468,
+	[BNXT_ULP_CLASS_HID_a060] = 2469,
+	[BNXT_ULP_CLASS_HID_a520] = 2470,
+	[BNXT_ULP_CLASS_HID_e6e0] = 2471,
+	[BNXT_ULP_CLASS_HID_eba0] = 2472,
+	[BNXT_ULP_CLASS_HID_1d660] = 2473,
+	[BNXT_ULP_CLASS_HID_1fb20] = 2474,
+	[BNXT_ULP_CLASS_HID_1dce0] = 2475,
+	[BNXT_ULP_CLASS_HID_1e1a0] = 2476,
+	[BNXT_ULP_CLASS_HID_1dd1c] = 2477,
+	[BNXT_ULP_CLASS_HID_1fedc] = 2478,
+	[BNXT_ULP_CLASS_HID_1c39c] = 2479,
+	[BNXT_ULP_CLASS_HID_1e55c] = 2480,
+	[BNXT_ULP_CLASS_HID_cb80] = 2481,
+	[BNXT_ULP_CLASS_HID_b194] = 2482,
+	[BNXT_ULP_CLASS_HID_d354] = 2483,
+	[BNXT_ULP_CLASS_HID_f414] = 2484,
+	[BNXT_ULP_CLASS_HID_c4d4] = 2485,
+	[BNXT_ULP_CLASS_HID_e994] = 2486,
+	[BNXT_ULP_CLASS_HID_cb54] = 2487,
+	[BNXT_ULP_CLASS_HID_f158] = 2488,
+	[BNXT_ULP_CLASS_HID_19f18] = 2489,
+	[BNXT_ULP_CLASS_HID_1a0d8] = 2490,
+	[BNXT_ULP_CLASS_HID_1c598] = 2491,
+	[BNXT_ULP_CLASS_HID_1e758] = 2492,
+	[BNXT_ULP_CLASS_HID_182d4] = 2493,
+	[BNXT_ULP_CLASS_HID_1a794] = 2494,
+	[BNXT_ULP_CLASS_HID_1c954] = 2495,
+	[BNXT_ULP_CLASS_HID_1ea14] = 2496,
+	[BNXT_ULP_CLASS_HID_b0b8] = 2497,
+	[BNXT_ULP_CLASS_HID_b278] = 2498,
+	[BNXT_ULP_CLASS_HID_f738] = 2499,
+	[BNXT_ULP_CLASS_HID_f8f8] = 2500,
+	[BNXT_ULP_CLASS_HID_8d8c] = 2501,
+	[BNXT_ULP_CLASS_HID_af4c] = 2502,
+	[BNXT_ULP_CLASS_HID_f00c] = 2503,
+	[BNXT_ULP_CLASS_HID_f5cc] = 2504,
+	[BNXT_ULP_CLASS_HID_1a38c] = 2505,
+	[BNXT_ULP_CLASS_HID_1a54c] = 2506,
+	[BNXT_ULP_CLASS_HID_1e60c] = 2507,
+	[BNXT_ULP_CLASS_HID_1ebcc] = 2508,
+	[BNXT_ULP_CLASS_HID_1a6b8] = 2509,
+	[BNXT_ULP_CLASS_HID_1a878] = 2510,
+	[BNXT_ULP_CLASS_HID_1ed38] = 2511,
+	[BNXT_ULP_CLASS_HID_1eef8] = 2512,
+	[BNXT_ULP_CLASS_HID_d52c] = 2513,
+	[BNXT_ULP_CLASS_HID_f6ec] = 2514,
+	[BNXT_ULP_CLASS_HID_dbac] = 2515,
+	[BNXT_ULP_CLASS_HID_fd6c] = 2516,
+	[BNXT_ULP_CLASS_HID_ae70] = 2517,
+	[BNXT_ULP_CLASS_HID_f330] = 2518,
+	[BNXT_ULP_CLASS_HID_d4f0] = 2519,
+	[BNXT_ULP_CLASS_HID_f9b0] = 2520,
+	[BNXT_ULP_CLASS_HID_1c470] = 2521,
+	[BNXT_ULP_CLASS_HID_1e930] = 2522,
+	[BNXT_ULP_CLASS_HID_1caf0] = 2523,
+	[BNXT_ULP_CLASS_HID_1f084] = 2524,
+	[BNXT_ULP_CLASS_HID_1cb2c] = 2525,
+	[BNXT_ULP_CLASS_HID_1b130] = 2526,
+	[BNXT_ULP_CLASS_HID_1d2f0] = 2527,
+	[BNXT_ULP_CLASS_HID_1f7b0] = 2528,
+	[BNXT_ULP_CLASS_HID_a1d0] = 2529,
+	[BNXT_ULP_CLASS_HID_a290] = 2530,
+	[BNXT_ULP_CLASS_HID_e450] = 2531,
+	[BNXT_ULP_CLASS_HID_e910] = 2532,
+	[BNXT_ULP_CLASS_HID_ba24] = 2533,
+	[BNXT_ULP_CLASS_HID_bfe4] = 2534,
+	[BNXT_ULP_CLASS_HID_e0a4] = 2535,
+	[BNXT_ULP_CLASS_HID_e264] = 2536,
+	[BNXT_ULP_CLASS_HID_1d024] = 2537,
+	[BNXT_ULP_CLASS_HID_1f5e4] = 2538,
+	[BNXT_ULP_CLASS_HID_1d6a4] = 2539,
+	[BNXT_ULP_CLASS_HID_1f864] = 2540,
+	[BNXT_ULP_CLASS_HID_1d7d0] = 2541,
+	[BNXT_ULP_CLASS_HID_1f890] = 2542,
+	[BNXT_ULP_CLASS_HID_1da50] = 2543,
+	[BNXT_ULP_CLASS_HID_1ff10] = 2544,
+	[BNXT_ULP_CLASS_HID_c244] = 2545,
+	[BNXT_ULP_CLASS_HID_e704] = 2546,
+	[BNXT_ULP_CLASS_HID_c8c4] = 2547,
+	[BNXT_ULP_CLASS_HID_ed84] = 2548,
+	[BNXT_ULP_CLASS_HID_de88] = 2549,
+	[BNXT_ULP_CLASS_HID_e048] = 2550,
+	[BNXT_ULP_CLASS_HID_c508] = 2551,
+	[BNXT_ULP_CLASS_HID_e6c8] = 2552,
+	[BNXT_ULP_CLASS_HID_199dc] = 2553,
+	[BNXT_ULP_CLASS_HID_1ba9c] = 2554,
+	[BNXT_ULP_CLASS_HID_1dc5c] = 2555,
+	[BNXT_ULP_CLASS_HID_1e11c] = 2556,
+	[BNXT_ULP_CLASS_HID_19c88] = 2557,
+	[BNXT_ULP_CLASS_HID_1be48] = 2558,
+	[BNXT_ULP_CLASS_HID_1c308] = 2559,
+	[BNXT_ULP_CLASS_HID_1e4c8] = 2560,
+	[BNXT_ULP_CLASS_HID_8b7c] = 2561,
+	[BNXT_ULP_CLASS_HID_ac3c] = 2562,
+	[BNXT_ULP_CLASS_HID_f1fc] = 2563,
+	[BNXT_ULP_CLASS_HID_f2bc] = 2564,
+	[BNXT_ULP_CLASS_HID_8440] = 2565,
+	[BNXT_ULP_CLASS_HID_a900] = 2566,
+	[BNXT_ULP_CLASS_HID_cac0] = 2567,
+	[BNXT_ULP_CLASS_HID_ef80] = 2568,
+	[BNXT_ULP_CLASS_HID_1ba40] = 2569,
+	[BNXT_ULP_CLASS_HID_1bf00] = 2570,
+	[BNXT_ULP_CLASS_HID_1e0c0] = 2571,
+	[BNXT_ULP_CLASS_HID_1e580] = 2572,
+	[BNXT_ULP_CLASS_HID_1a17c] = 2573,
+	[BNXT_ULP_CLASS_HID_1a23c] = 2574,
+	[BNXT_ULP_CLASS_HID_1e7fc] = 2575,
+	[BNXT_ULP_CLASS_HID_1e8bc] = 2576,
+	[BNXT_ULP_CLASS_HID_afe0] = 2577,
+	[BNXT_ULP_CLASS_HID_f0a0] = 2578,
+	[BNXT_ULP_CLASS_HID_d260] = 2579,
+	[BNXT_ULP_CLASS_HID_f720] = 2580,
+	[BNXT_ULP_CLASS_HID_a834] = 2581,
+	[BNXT_ULP_CLASS_HID_adf4] = 2582,
+	[BNXT_ULP_CLASS_HID_eeb4] = 2583,
+	[BNXT_ULP_CLASS_HID_f074] = 2584,
+	[BNXT_ULP_CLASS_HID_1de34] = 2585,
+	[BNXT_ULP_CLASS_HID_1e3f4] = 2586,
+	[BNXT_ULP_CLASS_HID_1c4b4] = 2587,
+	[BNXT_ULP_CLASS_HID_1e674] = 2588,
+	[BNXT_ULP_CLASS_HID_1c5e0] = 2589,
+	[BNXT_ULP_CLASS_HID_1e6a0] = 2590,
+	[BNXT_ULP_CLASS_HID_1c860] = 2591,
+	[BNXT_ULP_CLASS_HID_1ed20] = 2592,
+	[BNXT_ULP_CLASS_HID_8c0c] = 2593,
+	[BNXT_ULP_CLASS_HID_b1cc] = 2594,
+	[BNXT_ULP_CLASS_HID_f28c] = 2595,
+	[BNXT_ULP_CLASS_HID_f44c] = 2596,
+	[BNXT_ULP_CLASS_HID_8950] = 2597,
+	[BNXT_ULP_CLASS_HID_aa10] = 2598,
+	[BNXT_ULP_CLASS_HID_cfd0] = 2599,
+	[BNXT_ULP_CLASS_HID_f090] = 2600,
+	[BNXT_ULP_CLASS_HID_1bf50] = 2601,
+	[BNXT_ULP_CLASS_HID_1a010] = 2602,
+	[BNXT_ULP_CLASS_HID_1e5d0] = 2603,
+	[BNXT_ULP_CLASS_HID_1e690] = 2604,
+	[BNXT_ULP_CLASS_HID_1a20c] = 2605,
+	[BNXT_ULP_CLASS_HID_1a7cc] = 2606,
+	[BNXT_ULP_CLASS_HID_1e88c] = 2607,
+	[BNXT_ULP_CLASS_HID_1ea4c] = 2608,
+	[BNXT_ULP_CLASS_HID_d0f0] = 2609,
+	[BNXT_ULP_CLASS_HID_f5b0] = 2610,
+	[BNXT_ULP_CLASS_HID_d770] = 2611,
+	[BNXT_ULP_CLASS_HID_f830] = 2612,
+	[BNXT_ULP_CLASS_HID_adc4] = 2613,
+	[BNXT_ULP_CLASS_HID_ae84] = 2614,
+	[BNXT_ULP_CLASS_HID_d044] = 2615,
+	[BNXT_ULP_CLASS_HID_f504] = 2616,
+	[BNXT_ULP_CLASS_HID_1c3c4] = 2617,
+	[BNXT_ULP_CLASS_HID_1e484] = 2618,
+	[BNXT_ULP_CLASS_HID_1c644] = 2619,
+	[BNXT_ULP_CLASS_HID_1eb04] = 2620,
+	[BNXT_ULP_CLASS_HID_1c6f0] = 2621,
+	[BNXT_ULP_CLASS_HID_1ebb0] = 2622,
+	[BNXT_ULP_CLASS_HID_1cd70] = 2623,
+	[BNXT_ULP_CLASS_HID_1f304] = 2624,
+	[BNXT_ULP_CLASS_HID_99a8] = 2625,
+	[BNXT_ULP_CLASS_HID_bb68] = 2626,
+	[BNXT_ULP_CLASS_HID_dc28] = 2627,
+	[BNXT_ULP_CLASS_HID_e1e8] = 2628,
+	[BNXT_ULP_CLASS_HID_92fc] = 2629,
+	[BNXT_ULP_CLASS_HID_b7bc] = 2630,
+	[BNXT_ULP_CLASS_HID_d97c] = 2631,
+	[BNXT_ULP_CLASS_HID_fa3c] = 2632,
+	[BNXT_ULP_CLASS_HID_188fc] = 2633,
+	[BNXT_ULP_CLASS_HID_1adbc] = 2634,
+	[BNXT_ULP_CLASS_HID_1cf7c] = 2635,
+	[BNXT_ULP_CLASS_HID_1f03c] = 2636,
+	[BNXT_ULP_CLASS_HID_18fa8] = 2637,
+	[BNXT_ULP_CLASS_HID_1b168] = 2638,
+	[BNXT_ULP_CLASS_HID_1f228] = 2639,
+	[BNXT_ULP_CLASS_HID_1f7e8] = 2640,
+	[BNXT_ULP_CLASS_HID_ba1c] = 2641,
+	[BNXT_ULP_CLASS_HID_bfdc] = 2642,
+	[BNXT_ULP_CLASS_HID_e09c] = 2643,
+	[BNXT_ULP_CLASS_HID_e25c] = 2644,
+	[BNXT_ULP_CLASS_HID_b760] = 2645,
+	[BNXT_ULP_CLASS_HID_b820] = 2646,
+	[BNXT_ULP_CLASS_HID_fde0] = 2647,
+	[BNXT_ULP_CLASS_HID_fea0] = 2648,
+	[BNXT_ULP_CLASS_HID_1ad60] = 2649,
+	[BNXT_ULP_CLASS_HID_1ae20] = 2650,
+	[BNXT_ULP_CLASS_HID_1d3e0] = 2651,
+	[BNXT_ULP_CLASS_HID_1f4a0] = 2652,
+	[BNXT_ULP_CLASS_HID_1d01c] = 2653,
+	[BNXT_ULP_CLASS_HID_1f5dc] = 2654,
+	[BNXT_ULP_CLASS_HID_1d69c] = 2655,
+	[BNXT_ULP_CLASS_HID_1f85c] = 2656,
+	[BNXT_ULP_CLASS_HID_86c0] = 2657,
+	[BNXT_ULP_CLASS_HID_ab80] = 2658,
+	[BNXT_ULP_CLASS_HID_cd40] = 2659,
+	[BNXT_ULP_CLASS_HID_ee00] = 2660,
+	[BNXT_ULP_CLASS_HID_8314] = 2661,
+	[BNXT_ULP_CLASS_HID_a4d4] = 2662,
+	[BNXT_ULP_CLASS_HID_c994] = 2663,
+	[BNXT_ULP_CLASS_HID_eb54] = 2664,
+	[BNXT_ULP_CLASS_HID_1b914] = 2665,
+	[BNXT_ULP_CLASS_HID_1bad4] = 2666,
+	[BNXT_ULP_CLASS_HID_1ff94] = 2667,
+	[BNXT_ULP_CLASS_HID_1e154] = 2668,
+	[BNXT_ULP_CLASS_HID_1bcc0] = 2669,
+	[BNXT_ULP_CLASS_HID_1a180] = 2670,
+	[BNXT_ULP_CLASS_HID_1e340] = 2671,
+	[BNXT_ULP_CLASS_HID_1e400] = 2672,
+	[BNXT_ULP_CLASS_HID_aab4] = 2673,
+	[BNXT_ULP_CLASS_HID_ac74] = 2674,
+	[BNXT_ULP_CLASS_HID_d134] = 2675,
+	[BNXT_ULP_CLASS_HID_f2f4] = 2676,
+	[BNXT_ULP_CLASS_HID_a7f8] = 2677,
+	[BNXT_ULP_CLASS_HID_a8b8] = 2678,
+	[BNXT_ULP_CLASS_HID_ea78] = 2679,
+	[BNXT_ULP_CLASS_HID_ef38] = 2680,
+	[BNXT_ULP_CLASS_HID_1ddf8] = 2681,
+	[BNXT_ULP_CLASS_HID_1feb8] = 2682,
+	[BNXT_ULP_CLASS_HID_1c078] = 2683,
+	[BNXT_ULP_CLASS_HID_1e538] = 2684,
+	[BNXT_ULP_CLASS_HID_1c0b4] = 2685,
+	[BNXT_ULP_CLASS_HID_1e274] = 2686,
+	[BNXT_ULP_CLASS_HID_1c734] = 2687,
+	[BNXT_ULP_CLASS_HID_1e8f4] = 2688,
+	[BNXT_ULP_CLASS_HID_906c] = 2689,
+	[BNXT_ULP_CLASS_HID_b52c] = 2690,
+	[BNXT_ULP_CLASS_HID_d6ec] = 2691,
+	[BNXT_ULP_CLASS_HID_fbac] = 2692,
+	[BNXT_ULP_CLASS_HID_c86c] = 2693,
+	[BNXT_ULP_CLASS_HID_ed2c] = 2694,
+	[BNXT_ULP_CLASS_HID_d330] = 2695,
+	[BNXT_ULP_CLASS_HID_f4f0] = 2696,
+	[BNXT_ULP_CLASS_HID_182b0] = 2697,
+	[BNXT_ULP_CLASS_HID_1a470] = 2698,
+	[BNXT_ULP_CLASS_HID_1c930] = 2699,
+	[BNXT_ULP_CLASS_HID_1eaf0] = 2700,
+	[BNXT_ULP_CLASS_HID_1866c] = 2701,
+	[BNXT_ULP_CLASS_HID_1ab2c] = 2702,
+	[BNXT_ULP_CLASS_HID_1ccec] = 2703,
+	[BNXT_ULP_CLASS_HID_1f1ac] = 2704,
+	[BNXT_ULP_CLASS_HID_b4d0] = 2705,
+	[BNXT_ULP_CLASS_HID_b990] = 2706,
+	[BNXT_ULP_CLASS_HID_fb50] = 2707,
+	[BNXT_ULP_CLASS_HID_fc10] = 2708,
+	[BNXT_ULP_CLASS_HID_b124] = 2709,
+	[BNXT_ULP_CLASS_HID_b2e4] = 2710,
+	[BNXT_ULP_CLASS_HID_f7a4] = 2711,
+	[BNXT_ULP_CLASS_HID_f964] = 2712,
+	[BNXT_ULP_CLASS_HID_1a724] = 2713,
+	[BNXT_ULP_CLASS_HID_1a8e4] = 2714,
+	[BNXT_ULP_CLASS_HID_1eda4] = 2715,
+	[BNXT_ULP_CLASS_HID_1ef64] = 2716,
+	[BNXT_ULP_CLASS_HID_1aad0] = 2717,
+	[BNXT_ULP_CLASS_HID_1af90] = 2718,
+	[BNXT_ULP_CLASS_HID_1d150] = 2719,
+	[BNXT_ULP_CLASS_HID_1f210] = 2720,
+	[BNXT_ULP_CLASS_HID_8084] = 2721,
+	[BNXT_ULP_CLASS_HID_a244] = 2722,
+	[BNXT_ULP_CLASS_HID_c704] = 2723,
+	[BNXT_ULP_CLASS_HID_e8c4] = 2724,
+	[BNXT_ULP_CLASS_HID_9dc8] = 2725,
+	[BNXT_ULP_CLASS_HID_be88] = 2726,
+	[BNXT_ULP_CLASS_HID_c048] = 2727,
+	[BNXT_ULP_CLASS_HID_e508] = 2728,
+	[BNXT_ULP_CLASS_HID_1b3c8] = 2729,
+	[BNXT_ULP_CLASS_HID_1b488] = 2730,
+	[BNXT_ULP_CLASS_HID_1f648] = 2731,
+	[BNXT_ULP_CLASS_HID_1fb08] = 2732,
+	[BNXT_ULP_CLASS_HID_1b684] = 2733,
+	[BNXT_ULP_CLASS_HID_1b844] = 2734,
+	[BNXT_ULP_CLASS_HID_1fd04] = 2735,
+	[BNXT_ULP_CLASS_HID_1fec4] = 2736,
+	[BNXT_ULP_CLASS_HID_a568] = 2737,
+	[BNXT_ULP_CLASS_HID_a628] = 2738,
+	[BNXT_ULP_CLASS_HID_ebe8] = 2739,
+	[BNXT_ULP_CLASS_HID_eca8] = 2740,
+	[BNXT_ULP_CLASS_HID_a1bc] = 2741,
+	[BNXT_ULP_CLASS_HID_a37c] = 2742,
+	[BNXT_ULP_CLASS_HID_e43c] = 2743,
+	[BNXT_ULP_CLASS_HID_e9fc] = 2744,
+	[BNXT_ULP_CLASS_HID_1d7bc] = 2745,
+	[BNXT_ULP_CLASS_HID_1f97c] = 2746,
+	[BNXT_ULP_CLASS_HID_1da3c] = 2747,
+	[BNXT_ULP_CLASS_HID_1fffc] = 2748,
+	[BNXT_ULP_CLASS_HID_1db68] = 2749,
+	[BNXT_ULP_CLASS_HID_1fc28] = 2750,
+	[BNXT_ULP_CLASS_HID_1c1e8] = 2751,
+	[BNXT_ULP_CLASS_HID_1e2a8] = 2752,
+	[BNXT_ULP_CLASS_HID_9ab8] = 2753,
+	[BNXT_ULP_CLASS_HID_bc78] = 2754,
+	[BNXT_ULP_CLASS_HID_c138] = 2755,
+	[BNXT_ULP_CLASS_HID_e2f8] = 2756,
+	[BNXT_ULP_CLASS_HID_978c] = 2757,
+	[BNXT_ULP_CLASS_HID_b94c] = 2758,
+	[BNXT_ULP_CLASS_HID_da0c] = 2759,
+	[BNXT_ULP_CLASS_HID_ffcc] = 2760,
+	[BNXT_ULP_CLASS_HID_18d8c] = 2761,
+	[BNXT_ULP_CLASS_HID_1af4c] = 2762,
+	[BNXT_ULP_CLASS_HID_1f00c] = 2763,
+	[BNXT_ULP_CLASS_HID_1f5cc] = 2764,
+	[BNXT_ULP_CLASS_HID_1b0b8] = 2765,
+	[BNXT_ULP_CLASS_HID_1b278] = 2766,
+	[BNXT_ULP_CLASS_HID_1f738] = 2767,
+	[BNXT_ULP_CLASS_HID_1f8f8] = 2768,
+	[BNXT_ULP_CLASS_HID_bf2c] = 2769,
+	[BNXT_ULP_CLASS_HID_a0ec] = 2770,
+	[BNXT_ULP_CLASS_HID_e5ac] = 2771,
+	[BNXT_ULP_CLASS_HID_e76c] = 2772,
+	[BNXT_ULP_CLASS_HID_b870] = 2773,
+	[BNXT_ULP_CLASS_HID_bd30] = 2774,
+	[BNXT_ULP_CLASS_HID_fef0] = 2775,
+	[BNXT_ULP_CLASS_HID_e3b0] = 2776,
+	[BNXT_ULP_CLASS_HID_1ae70] = 2777,
+	[BNXT_ULP_CLASS_HID_1f330] = 2778,
+	[BNXT_ULP_CLASS_HID_1d4f0] = 2779,
+	[BNXT_ULP_CLASS_HID_1f9b0] = 2780,
+	[BNXT_ULP_CLASS_HID_1d52c] = 2781,
+	[BNXT_ULP_CLASS_HID_1f6ec] = 2782,
+	[BNXT_ULP_CLASS_HID_1dbac] = 2783,
+	[BNXT_ULP_CLASS_HID_1fd6c] = 2784,
+	[BNXT_ULP_CLASS_HID_34d0] = 2785,
+	[BNXT_ULP_CLASS_HID_3a1c] = 2786,
+	[BNXT_ULP_CLASS_HID_5e80] = 2787,
+	[BNXT_ULP_CLASS_HID_07b8] = 2788,
+	[BNXT_ULP_CLASS_HID_282c] = 2789,
+	[BNXT_ULP_CLASS_HID_5944] = 2790,
+	[BNXT_ULP_CLASS_HID_1e7c] = 2791,
+	[BNXT_ULP_CLASS_HID_22e0] = 2792,
+	[BNXT_ULP_CLASS_HID_a77c] = 2793,
+	[BNXT_ULP_CLASS_HID_a8bc] = 2794,
+	[BNXT_ULP_CLASS_HID_edfc] = 2795,
+	[BNXT_ULP_CLASS_HID_ef3c] = 2796,
+	[BNXT_ULP_CLASS_HID_a000] = 2797,
+	[BNXT_ULP_CLASS_HID_a540] = 2798,
+	[BNXT_ULP_CLASS_HID_e680] = 2799,
+	[BNXT_ULP_CLASS_HID_ebc0] = 2800,
+	[BNXT_ULP_CLASS_HID_1d600] = 2801,
+	[BNXT_ULP_CLASS_HID_1fb40] = 2802,
+	[BNXT_ULP_CLASS_HID_1dc80] = 2803,
+	[BNXT_ULP_CLASS_HID_1e1c0] = 2804,
+	[BNXT_ULP_CLASS_HID_1dd7c] = 2805,
+	[BNXT_ULP_CLASS_HID_1febc] = 2806,
+	[BNXT_ULP_CLASS_HID_1c3fc] = 2807,
+	[BNXT_ULP_CLASS_HID_1e53c] = 2808,
+	[BNXT_ULP_CLASS_HID_cbe0] = 2809,
+	[BNXT_ULP_CLASS_HID_b1f4] = 2810,
+	[BNXT_ULP_CLASS_HID_d334] = 2811,
+	[BNXT_ULP_CLASS_HID_f474] = 2812,
+	[BNXT_ULP_CLASS_HID_c4b4] = 2813,
+	[BNXT_ULP_CLASS_HID_e9f4] = 2814,
+	[BNXT_ULP_CLASS_HID_cb34] = 2815,
+	[BNXT_ULP_CLASS_HID_f138] = 2816,
+	[BNXT_ULP_CLASS_HID_19f78] = 2817,
+	[BNXT_ULP_CLASS_HID_1a0b8] = 2818,
+	[BNXT_ULP_CLASS_HID_1c5f8] = 2819,
+	[BNXT_ULP_CLASS_HID_1e738] = 2820,
+	[BNXT_ULP_CLASS_HID_182b4] = 2821,
+	[BNXT_ULP_CLASS_HID_1a7f4] = 2822,
+	[BNXT_ULP_CLASS_HID_1c934] = 2823,
+	[BNXT_ULP_CLASS_HID_1ea74] = 2824,
+	[BNXT_ULP_CLASS_HID_b0d8] = 2825,
+	[BNXT_ULP_CLASS_HID_b218] = 2826,
+	[BNXT_ULP_CLASS_HID_f758] = 2827,
+	[BNXT_ULP_CLASS_HID_f898] = 2828,
+	[BNXT_ULP_CLASS_HID_8dec] = 2829,
+	[BNXT_ULP_CLASS_HID_af2c] = 2830,
+	[BNXT_ULP_CLASS_HID_f06c] = 2831,
+	[BNXT_ULP_CLASS_HID_f5ac] = 2832,
+	[BNXT_ULP_CLASS_HID_1a3ec] = 2833,
+	[BNXT_ULP_CLASS_HID_1a52c] = 2834,
+	[BNXT_ULP_CLASS_HID_1e66c] = 2835,
+	[BNXT_ULP_CLASS_HID_1ebac] = 2836,
+	[BNXT_ULP_CLASS_HID_1a6d8] = 2837,
+	[BNXT_ULP_CLASS_HID_1a818] = 2838,
+	[BNXT_ULP_CLASS_HID_1ed58] = 2839,
+	[BNXT_ULP_CLASS_HID_1ee98] = 2840,
+	[BNXT_ULP_CLASS_HID_d54c] = 2841,
+	[BNXT_ULP_CLASS_HID_f68c] = 2842,
+	[BNXT_ULP_CLASS_HID_dbcc] = 2843,
+	[BNXT_ULP_CLASS_HID_fd0c] = 2844,
+	[BNXT_ULP_CLASS_HID_ae10] = 2845,
+	[BNXT_ULP_CLASS_HID_f350] = 2846,
+	[BNXT_ULP_CLASS_HID_d490] = 2847,
+	[BNXT_ULP_CLASS_HID_f9d0] = 2848,
+	[BNXT_ULP_CLASS_HID_1c410] = 2849,
+	[BNXT_ULP_CLASS_HID_1e950] = 2850,
+	[BNXT_ULP_CLASS_HID_1ca90] = 2851,
+	[BNXT_ULP_CLASS_HID_1f0e4] = 2852,
+	[BNXT_ULP_CLASS_HID_1cb4c] = 2853,
+	[BNXT_ULP_CLASS_HID_1b150] = 2854,
+	[BNXT_ULP_CLASS_HID_1d290] = 2855,
+	[BNXT_ULP_CLASS_HID_1f7d0] = 2856,
+	[BNXT_ULP_CLASS_HID_a1b0] = 2857,
+	[BNXT_ULP_CLASS_HID_a2f0] = 2858,
+	[BNXT_ULP_CLASS_HID_e430] = 2859,
+	[BNXT_ULP_CLASS_HID_e970] = 2860,
+	[BNXT_ULP_CLASS_HID_ba44] = 2861,
+	[BNXT_ULP_CLASS_HID_bf84] = 2862,
+	[BNXT_ULP_CLASS_HID_e0c4] = 2863,
+	[BNXT_ULP_CLASS_HID_e204] = 2864,
+	[BNXT_ULP_CLASS_HID_1d044] = 2865,
+	[BNXT_ULP_CLASS_HID_1f584] = 2866,
+	[BNXT_ULP_CLASS_HID_1d6c4] = 2867,
+	[BNXT_ULP_CLASS_HID_1f804] = 2868,
+	[BNXT_ULP_CLASS_HID_1d7b0] = 2869,
+	[BNXT_ULP_CLASS_HID_1f8f0] = 2870,
+	[BNXT_ULP_CLASS_HID_1da30] = 2871,
+	[BNXT_ULP_CLASS_HID_1ff70] = 2872,
+	[BNXT_ULP_CLASS_HID_c224] = 2873,
+	[BNXT_ULP_CLASS_HID_e764] = 2874,
+	[BNXT_ULP_CLASS_HID_c8a4] = 2875,
+	[BNXT_ULP_CLASS_HID_ede4] = 2876,
+	[BNXT_ULP_CLASS_HID_dee8] = 2877,
+	[BNXT_ULP_CLASS_HID_e028] = 2878,
+	[BNXT_ULP_CLASS_HID_c568] = 2879,
+	[BNXT_ULP_CLASS_HID_e6a8] = 2880,
+	[BNXT_ULP_CLASS_HID_199bc] = 2881,
+	[BNXT_ULP_CLASS_HID_1bafc] = 2882,
+	[BNXT_ULP_CLASS_HID_1dc3c] = 2883,
+	[BNXT_ULP_CLASS_HID_1e17c] = 2884,
+	[BNXT_ULP_CLASS_HID_19ce8] = 2885,
+	[BNXT_ULP_CLASS_HID_1be28] = 2886,
+	[BNXT_ULP_CLASS_HID_1c368] = 2887,
+	[BNXT_ULP_CLASS_HID_1e4a8] = 2888,
+	[BNXT_ULP_CLASS_HID_8b1c] = 2889,
+	[BNXT_ULP_CLASS_HID_ac5c] = 2890,
+	[BNXT_ULP_CLASS_HID_f19c] = 2891,
+	[BNXT_ULP_CLASS_HID_f2dc] = 2892,
+	[BNXT_ULP_CLASS_HID_8420] = 2893,
+	[BNXT_ULP_CLASS_HID_a960] = 2894,
+	[BNXT_ULP_CLASS_HID_caa0] = 2895,
+	[BNXT_ULP_CLASS_HID_efe0] = 2896,
+	[BNXT_ULP_CLASS_HID_1ba20] = 2897,
+	[BNXT_ULP_CLASS_HID_1bf60] = 2898,
+	[BNXT_ULP_CLASS_HID_1e0a0] = 2899,
+	[BNXT_ULP_CLASS_HID_1e5e0] = 2900,
+	[BNXT_ULP_CLASS_HID_1a11c] = 2901,
+	[BNXT_ULP_CLASS_HID_1a25c] = 2902,
+	[BNXT_ULP_CLASS_HID_1e79c] = 2903,
+	[BNXT_ULP_CLASS_HID_1e8dc] = 2904,
+	[BNXT_ULP_CLASS_HID_af80] = 2905,
+	[BNXT_ULP_CLASS_HID_f0c0] = 2906,
+	[BNXT_ULP_CLASS_HID_d200] = 2907,
+	[BNXT_ULP_CLASS_HID_f740] = 2908,
+	[BNXT_ULP_CLASS_HID_a854] = 2909,
+	[BNXT_ULP_CLASS_HID_ad94] = 2910,
+	[BNXT_ULP_CLASS_HID_eed4] = 2911,
+	[BNXT_ULP_CLASS_HID_f014] = 2912,
+	[BNXT_ULP_CLASS_HID_1de54] = 2913,
+	[BNXT_ULP_CLASS_HID_1e394] = 2914,
+	[BNXT_ULP_CLASS_HID_1c4d4] = 2915,
+	[BNXT_ULP_CLASS_HID_1e614] = 2916,
+	[BNXT_ULP_CLASS_HID_1c580] = 2917,
+	[BNXT_ULP_CLASS_HID_1e6c0] = 2918,
+	[BNXT_ULP_CLASS_HID_1c800] = 2919,
+	[BNXT_ULP_CLASS_HID_1ed40] = 2920,
+	[BNXT_ULP_CLASS_HID_8c6c] = 2921,
+	[BNXT_ULP_CLASS_HID_b1ac] = 2922,
+	[BNXT_ULP_CLASS_HID_f2ec] = 2923,
+	[BNXT_ULP_CLASS_HID_f42c] = 2924,
+	[BNXT_ULP_CLASS_HID_8930] = 2925,
+	[BNXT_ULP_CLASS_HID_aa70] = 2926,
+	[BNXT_ULP_CLASS_HID_cfb0] = 2927,
+	[BNXT_ULP_CLASS_HID_f0f0] = 2928,
+	[BNXT_ULP_CLASS_HID_1bf30] = 2929,
+	[BNXT_ULP_CLASS_HID_1a070] = 2930,
+	[BNXT_ULP_CLASS_HID_1e5b0] = 2931,
+	[BNXT_ULP_CLASS_HID_1e6f0] = 2932,
+	[BNXT_ULP_CLASS_HID_1a26c] = 2933,
+	[BNXT_ULP_CLASS_HID_1a7ac] = 2934,
+	[BNXT_ULP_CLASS_HID_1e8ec] = 2935,
+	[BNXT_ULP_CLASS_HID_1ea2c] = 2936,
+	[BNXT_ULP_CLASS_HID_d090] = 2937,
+	[BNXT_ULP_CLASS_HID_f5d0] = 2938,
+	[BNXT_ULP_CLASS_HID_d710] = 2939,
+	[BNXT_ULP_CLASS_HID_f850] = 2940,
+	[BNXT_ULP_CLASS_HID_ada4] = 2941,
+	[BNXT_ULP_CLASS_HID_aee4] = 2942,
+	[BNXT_ULP_CLASS_HID_d024] = 2943,
+	[BNXT_ULP_CLASS_HID_f564] = 2944,
+	[BNXT_ULP_CLASS_HID_1c3a4] = 2945,
+	[BNXT_ULP_CLASS_HID_1e4e4] = 2946,
+	[BNXT_ULP_CLASS_HID_1c624] = 2947,
+	[BNXT_ULP_CLASS_HID_1eb64] = 2948,
+	[BNXT_ULP_CLASS_HID_1c690] = 2949,
+	[BNXT_ULP_CLASS_HID_1ebd0] = 2950,
+	[BNXT_ULP_CLASS_HID_1cd10] = 2951,
+	[BNXT_ULP_CLASS_HID_1f364] = 2952,
+	[BNXT_ULP_CLASS_HID_99c8] = 2953,
+	[BNXT_ULP_CLASS_HID_bb08] = 2954,
+	[BNXT_ULP_CLASS_HID_dc48] = 2955,
+	[BNXT_ULP_CLASS_HID_e188] = 2956,
+	[BNXT_ULP_CLASS_HID_929c] = 2957,
+	[BNXT_ULP_CLASS_HID_b7dc] = 2958,
+	[BNXT_ULP_CLASS_HID_d91c] = 2959,
+	[BNXT_ULP_CLASS_HID_fa5c] = 2960,
+	[BNXT_ULP_CLASS_HID_1889c] = 2961,
+	[BNXT_ULP_CLASS_HID_1addc] = 2962,
+	[BNXT_ULP_CLASS_HID_1cf1c] = 2963,
+	[BNXT_ULP_CLASS_HID_1f05c] = 2964,
+	[BNXT_ULP_CLASS_HID_18fc8] = 2965,
+	[BNXT_ULP_CLASS_HID_1b108] = 2966,
+	[BNXT_ULP_CLASS_HID_1f248] = 2967,
+	[BNXT_ULP_CLASS_HID_1f788] = 2968,
+	[BNXT_ULP_CLASS_HID_ba7c] = 2969,
+	[BNXT_ULP_CLASS_HID_bfbc] = 2970,
+	[BNXT_ULP_CLASS_HID_e0fc] = 2971,
+	[BNXT_ULP_CLASS_HID_e23c] = 2972,
+	[BNXT_ULP_CLASS_HID_b700] = 2973,
+	[BNXT_ULP_CLASS_HID_b840] = 2974,
+	[BNXT_ULP_CLASS_HID_fd80] = 2975,
+	[BNXT_ULP_CLASS_HID_fec0] = 2976,
+	[BNXT_ULP_CLASS_HID_1ad00] = 2977,
+	[BNXT_ULP_CLASS_HID_1ae40] = 2978,
+	[BNXT_ULP_CLASS_HID_1d380] = 2979,
+	[BNXT_ULP_CLASS_HID_1f4c0] = 2980,
+	[BNXT_ULP_CLASS_HID_1d07c] = 2981,
+	[BNXT_ULP_CLASS_HID_1f5bc] = 2982,
+	[BNXT_ULP_CLASS_HID_1d6fc] = 2983,
+	[BNXT_ULP_CLASS_HID_1f83c] = 2984,
+	[BNXT_ULP_CLASS_HID_86a0] = 2985,
+	[BNXT_ULP_CLASS_HID_abe0] = 2986,
+	[BNXT_ULP_CLASS_HID_cd20] = 2987,
+	[BNXT_ULP_CLASS_HID_ee60] = 2988,
+	[BNXT_ULP_CLASS_HID_8374] = 2989,
+	[BNXT_ULP_CLASS_HID_a4b4] = 2990,
+	[BNXT_ULP_CLASS_HID_c9f4] = 2991,
+	[BNXT_ULP_CLASS_HID_eb34] = 2992,
+	[BNXT_ULP_CLASS_HID_1b974] = 2993,
+	[BNXT_ULP_CLASS_HID_1bab4] = 2994,
+	[BNXT_ULP_CLASS_HID_1fff4] = 2995,
+	[BNXT_ULP_CLASS_HID_1e134] = 2996,
+	[BNXT_ULP_CLASS_HID_1bca0] = 2997,
+	[BNXT_ULP_CLASS_HID_1a1e0] = 2998,
+	[BNXT_ULP_CLASS_HID_1e320] = 2999,
+	[BNXT_ULP_CLASS_HID_1e460] = 3000,
+	[BNXT_ULP_CLASS_HID_aad4] = 3001,
+	[BNXT_ULP_CLASS_HID_ac14] = 3002,
+	[BNXT_ULP_CLASS_HID_d154] = 3003,
+	[BNXT_ULP_CLASS_HID_f294] = 3004,
+	[BNXT_ULP_CLASS_HID_a798] = 3005,
+	[BNXT_ULP_CLASS_HID_a8d8] = 3006,
+	[BNXT_ULP_CLASS_HID_ea18] = 3007,
+	[BNXT_ULP_CLASS_HID_ef58] = 3008,
+	[BNXT_ULP_CLASS_HID_1dd98] = 3009,
+	[BNXT_ULP_CLASS_HID_1fed8] = 3010,
+	[BNXT_ULP_CLASS_HID_1c018] = 3011,
+	[BNXT_ULP_CLASS_HID_1e558] = 3012,
+	[BNXT_ULP_CLASS_HID_1c0d4] = 3013,
+	[BNXT_ULP_CLASS_HID_1e214] = 3014,
+	[BNXT_ULP_CLASS_HID_1c754] = 3015,
+	[BNXT_ULP_CLASS_HID_1e894] = 3016,
+	[BNXT_ULP_CLASS_HID_900c] = 3017,
+	[BNXT_ULP_CLASS_HID_b54c] = 3018,
+	[BNXT_ULP_CLASS_HID_d68c] = 3019,
+	[BNXT_ULP_CLASS_HID_fbcc] = 3020,
+	[BNXT_ULP_CLASS_HID_c80c] = 3021,
+	[BNXT_ULP_CLASS_HID_ed4c] = 3022,
+	[BNXT_ULP_CLASS_HID_d350] = 3023,
+	[BNXT_ULP_CLASS_HID_f490] = 3024,
+	[BNXT_ULP_CLASS_HID_182d0] = 3025,
+	[BNXT_ULP_CLASS_HID_1a410] = 3026,
+	[BNXT_ULP_CLASS_HID_1c950] = 3027,
+	[BNXT_ULP_CLASS_HID_1ea90] = 3028,
+	[BNXT_ULP_CLASS_HID_1860c] = 3029,
+	[BNXT_ULP_CLASS_HID_1ab4c] = 3030,
+	[BNXT_ULP_CLASS_HID_1cc8c] = 3031,
+	[BNXT_ULP_CLASS_HID_1f1cc] = 3032,
+	[BNXT_ULP_CLASS_HID_b4b0] = 3033,
+	[BNXT_ULP_CLASS_HID_b9f0] = 3034,
+	[BNXT_ULP_CLASS_HID_fb30] = 3035,
+	[BNXT_ULP_CLASS_HID_fc70] = 3036,
+	[BNXT_ULP_CLASS_HID_b144] = 3037,
+	[BNXT_ULP_CLASS_HID_b284] = 3038,
+	[BNXT_ULP_CLASS_HID_f7c4] = 3039,
+	[BNXT_ULP_CLASS_HID_f904] = 3040,
+	[BNXT_ULP_CLASS_HID_1a744] = 3041,
+	[BNXT_ULP_CLASS_HID_1a884] = 3042,
+	[BNXT_ULP_CLASS_HID_1edc4] = 3043,
+	[BNXT_ULP_CLASS_HID_1ef04] = 3044,
+	[BNXT_ULP_CLASS_HID_1aab0] = 3045,
+	[BNXT_ULP_CLASS_HID_1aff0] = 3046,
+	[BNXT_ULP_CLASS_HID_1d130] = 3047,
+	[BNXT_ULP_CLASS_HID_1f270] = 3048,
+	[BNXT_ULP_CLASS_HID_80e4] = 3049,
+	[BNXT_ULP_CLASS_HID_a224] = 3050,
+	[BNXT_ULP_CLASS_HID_c764] = 3051,
+	[BNXT_ULP_CLASS_HID_e8a4] = 3052,
+	[BNXT_ULP_CLASS_HID_9da8] = 3053,
+	[BNXT_ULP_CLASS_HID_bee8] = 3054,
+	[BNXT_ULP_CLASS_HID_c028] = 3055,
+	[BNXT_ULP_CLASS_HID_e568] = 3056,
+	[BNXT_ULP_CLASS_HID_1b3a8] = 3057,
+	[BNXT_ULP_CLASS_HID_1b4e8] = 3058,
+	[BNXT_ULP_CLASS_HID_1f628] = 3059,
+	[BNXT_ULP_CLASS_HID_1fb68] = 3060,
+	[BNXT_ULP_CLASS_HID_1b6e4] = 3061,
+	[BNXT_ULP_CLASS_HID_1b824] = 3062,
+	[BNXT_ULP_CLASS_HID_1fd64] = 3063,
+	[BNXT_ULP_CLASS_HID_1fea4] = 3064,
+	[BNXT_ULP_CLASS_HID_a508] = 3065,
+	[BNXT_ULP_CLASS_HID_a648] = 3066,
+	[BNXT_ULP_CLASS_HID_eb88] = 3067,
+	[BNXT_ULP_CLASS_HID_ecc8] = 3068,
+	[BNXT_ULP_CLASS_HID_a1dc] = 3069,
+	[BNXT_ULP_CLASS_HID_a31c] = 3070,
+	[BNXT_ULP_CLASS_HID_e45c] = 3071,
+	[BNXT_ULP_CLASS_HID_e99c] = 3072,
+	[BNXT_ULP_CLASS_HID_1d7dc] = 3073,
+	[BNXT_ULP_CLASS_HID_1f91c] = 3074,
+	[BNXT_ULP_CLASS_HID_1da5c] = 3075,
+	[BNXT_ULP_CLASS_HID_1ff9c] = 3076,
+	[BNXT_ULP_CLASS_HID_1db08] = 3077,
+	[BNXT_ULP_CLASS_HID_1fc48] = 3078,
+	[BNXT_ULP_CLASS_HID_1c188] = 3079,
+	[BNXT_ULP_CLASS_HID_1e2c8] = 3080,
+	[BNXT_ULP_CLASS_HID_9ad8] = 3081,
+	[BNXT_ULP_CLASS_HID_bc18] = 3082,
+	[BNXT_ULP_CLASS_HID_c158] = 3083,
+	[BNXT_ULP_CLASS_HID_e298] = 3084,
+	[BNXT_ULP_CLASS_HID_97ec] = 3085,
+	[BNXT_ULP_CLASS_HID_b92c] = 3086,
+	[BNXT_ULP_CLASS_HID_da6c] = 3087,
+	[BNXT_ULP_CLASS_HID_ffac] = 3088,
+	[BNXT_ULP_CLASS_HID_18dec] = 3089,
+	[BNXT_ULP_CLASS_HID_1af2c] = 3090,
+	[BNXT_ULP_CLASS_HID_1f06c] = 3091,
+	[BNXT_ULP_CLASS_HID_1f5ac] = 3092,
+	[BNXT_ULP_CLASS_HID_1b0d8] = 3093,
+	[BNXT_ULP_CLASS_HID_1b218] = 3094,
+	[BNXT_ULP_CLASS_HID_1f758] = 3095,
+	[BNXT_ULP_CLASS_HID_1f898] = 3096,
+	[BNXT_ULP_CLASS_HID_bf4c] = 3097,
+	[BNXT_ULP_CLASS_HID_a08c] = 3098,
+	[BNXT_ULP_CLASS_HID_e5cc] = 3099,
+	[BNXT_ULP_CLASS_HID_e70c] = 3100,
+	[BNXT_ULP_CLASS_HID_b810] = 3101,
+	[BNXT_ULP_CLASS_HID_bd50] = 3102,
+	[BNXT_ULP_CLASS_HID_fe90] = 3103,
+	[BNXT_ULP_CLASS_HID_e3d0] = 3104,
+	[BNXT_ULP_CLASS_HID_1ae10] = 3105,
+	[BNXT_ULP_CLASS_HID_1f350] = 3106,
+	[BNXT_ULP_CLASS_HID_1d490] = 3107,
+	[BNXT_ULP_CLASS_HID_1f9d0] = 3108,
+	[BNXT_ULP_CLASS_HID_1d54c] = 3109,
+	[BNXT_ULP_CLASS_HID_1f68c] = 3110,
+	[BNXT_ULP_CLASS_HID_1dbcc] = 3111,
+	[BNXT_ULP_CLASS_HID_1fd0c] = 3112,
+	[BNXT_ULP_CLASS_HID_34b0] = 3113,
+	[BNXT_ULP_CLASS_HID_3a7c] = 3114,
+	[BNXT_ULP_CLASS_HID_5ee0] = 3115,
+	[BNXT_ULP_CLASS_HID_07d8] = 3116,
+	[BNXT_ULP_CLASS_HID_284c] = 3117,
+	[BNXT_ULP_CLASS_HID_5924] = 3118,
+	[BNXT_ULP_CLASS_HID_1e1c] = 3119,
+	[BNXT_ULP_CLASS_HID_2280] = 3120,
+	[BNXT_ULP_CLASS_HID_24604] = 3121,
+	[BNXT_ULP_CLASS_HID_255d4] = 3122,
+	[BNXT_ULP_CLASS_HID_22e08] = 3123,
+	[BNXT_ULP_CLASS_HID_24378] = 3124,
+	[BNXT_ULP_CLASS_HID_20fcc] = 3125,
+	[BNXT_ULP_CLASS_HID_21a9c] = 3126,
+	[BNXT_ULP_CLASS_HID_217d0] = 3127,
+	[BNXT_ULP_CLASS_HID_20800] = 3128,
+	[BNXT_ULP_CLASS_HID_253a0] = 3129,
+	[BNXT_ULP_CLASS_HID_23f70] = 3130,
+	[BNXT_ULP_CLASS_HID_23ba4] = 3131,
+	[BNXT_ULP_CLASS_HID_22c94] = 3132,
+	[BNXT_ULP_CLASS_HID_21968] = 3133,
+	[BNXT_ULP_CLASS_HID_243c4] = 3134,
+	[BNXT_ULP_CLASS_HID_25c38] = 3135,
+	[BNXT_ULP_CLASS_HID_2125c] = 3136,
+	[BNXT_ULP_CLASS_HID_240c8] = 3137,
+	[BNXT_ULP_CLASS_HID_22f98] = 3138,
+	[BNXT_ULP_CLASS_HID_228cc] = 3139,
+	[BNXT_ULP_CLASS_HID_25d3c] = 3140,
+	[BNXT_ULP_CLASS_HID_20990] = 3141,
+	[BNXT_ULP_CLASS_HID_214a0] = 3142,
+	[BNXT_ULP_CLASS_HID_21194] = 3143,
+	[BNXT_ULP_CLASS_HID_202c4] = 3144,
+	[BNXT_ULP_CLASS_HID_22a64] = 3145,
+	[BNXT_ULP_CLASS_HID_23934] = 3146,
+	[BNXT_ULP_CLASS_HID_23268] = 3147,
+	[BNXT_ULP_CLASS_HID_22758] = 3148,
+	[BNXT_ULP_CLASS_HID_2132c] = 3149,
+	[BNXT_ULP_CLASS_HID_25d88] = 3150,
+	[BNXT_ULP_CLASS_HID_256fc] = 3151,
+	[BNXT_ULP_CLASS_HID_24b2c] = 3152,
+	[BNXT_ULP_CLASS_HID_22f14] = 3153,
+	[BNXT_ULP_CLASS_HID_23a24] = 3154,
+	[BNXT_ULP_CLASS_HID_23718] = 3155,
+	[BNXT_ULP_CLASS_HID_22848] = 3156,
+	[BNXT_ULP_CLASS_HID_214dc] = 3157,
+	[BNXT_ULP_CLASS_HID_25eb8] = 3158,
+	[BNXT_ULP_CLASS_HID_25bec] = 3159,
+	[BNXT_ULP_CLASS_HID_21110] = 3160,
+	[BNXT_ULP_CLASS_HID_238b0] = 3161,
+	[BNXT_ULP_CLASS_HID_20440] = 3162,
+	[BNXT_ULP_CLASS_HID_200b4] = 3163,
+	[BNXT_ULP_CLASS_HID_235e4] = 3164,
+	[BNXT_ULP_CLASS_HID_25d04] = 3165,
+	[BNXT_ULP_CLASS_HID_228d4] = 3166,
+	[BNXT_ULP_CLASS_HID_22508] = 3167,
+	[BNXT_ULP_CLASS_HID_25678] = 3168,
+	[BNXT_ULP_CLASS_HID_229d8] = 3169,
+	[BNXT_ULP_CLASS_HID_234e8] = 3170,
+	[BNXT_ULP_CLASS_HID_231dc] = 3171,
+	[BNXT_ULP_CLASS_HID_2220c] = 3172,
+	[BNXT_ULP_CLASS_HID_24dac] = 3173,
+	[BNXT_ULP_CLASS_HID_2597c] = 3174,
+	[BNXT_ULP_CLASS_HID_255b0] = 3175,
+	[BNXT_ULP_CLASS_HID_246e0] = 3176,
+	[BNXT_ULP_CLASS_HID_23374] = 3177,
+	[BNXT_ULP_CLASS_HID_21e04] = 3178,
+	[BNXT_ULP_CLASS_HID_21b78] = 3179,
+	[BNXT_ULP_CLASS_HID_20fa8] = 3180,
+	[BNXT_ULP_CLASS_HID_257c8] = 3181,
+	[BNXT_ULP_CLASS_HID_22298] = 3182,
+	[BNXT_ULP_CLASS_HID_23fcc] = 3183,
+	[BNXT_ULP_CLASS_HID_2503c] = 3184,
+	[BNXT_ULP_CLASS_HID_2239c] = 3185,
+	[BNXT_ULP_CLASS_HID_20eac] = 3186,
+	[BNXT_ULP_CLASS_HID_20be0] = 3187,
+	[BNXT_ULP_CLASS_HID_23cd0] = 3188,
+	[BNXT_ULP_CLASS_HID_24470] = 3189,
+	[BNXT_ULP_CLASS_HID_25300] = 3190,
+	[BNXT_ULP_CLASS_HID_22c74] = 3191,
+	[BNXT_ULP_CLASS_HID_240a4] = 3192,
+	[BNXT_ULP_CLASS_HID_23da0] = 3193,
+	[BNXT_ULP_CLASS_HID_20970] = 3194,
+	[BNXT_ULP_CLASS_HID_205a4] = 3195,
+	[BNXT_ULP_CLASS_HID_23694] = 3196,
+	[BNXT_ULP_CLASS_HID_25e34] = 3197,
+	[BNXT_ULP_CLASS_HID_22dc4] = 3198,
+	[BNXT_ULP_CLASS_HID_22638] = 3199,
+	[BNXT_ULP_CLASS_HID_25b68] = 3200,
+	[BNXT_ULP_CLASS_HID_34c8] = 3201,
+	[BNXT_ULP_CLASS_HID_3a04] = 3202,
+	[BNXT_ULP_CLASS_HID_5e98] = 3203,
+	[BNXT_ULP_CLASS_HID_07a0] = 3204,
+	[BNXT_ULP_CLASS_HID_2834] = 3205,
+	[BNXT_ULP_CLASS_HID_595c] = 3206,
+	[BNXT_ULP_CLASS_HID_1e64] = 3207,
+	[BNXT_ULP_CLASS_HID_22f8] = 3208,
+	[BNXT_ULP_CLASS_HID_24664] = 3209,
+	[BNXT_ULP_CLASS_HID_29418] = 3210,
+	[BNXT_ULP_CLASS_HID_30118] = 3211,
+	[BNXT_ULP_CLASS_HID_38a18] = 3212,
+	[BNXT_ULP_CLASS_HID_255b4] = 3213,
+	[BNXT_ULP_CLASS_HID_2deb4] = 3214,
+	[BNXT_ULP_CLASS_HID_34bb4] = 3215,
+	[BNXT_ULP_CLASS_HID_39968] = 3216,
+	[BNXT_ULP_CLASS_HID_22e68] = 3217,
+	[BNXT_ULP_CLASS_HID_2db68] = 3218,
+	[BNXT_ULP_CLASS_HID_34468] = 3219,
+	[BNXT_ULP_CLASS_HID_3921c] = 3220,
+	[BNXT_ULP_CLASS_HID_24318] = 3221,
+	[BNXT_ULP_CLASS_HID_290cc] = 3222,
+	[BNXT_ULP_CLASS_HID_31dcc] = 3223,
+	[BNXT_ULP_CLASS_HID_386cc] = 3224,
+	[BNXT_ULP_CLASS_HID_20fac] = 3225,
+	[BNXT_ULP_CLASS_HID_2b8ac] = 3226,
+	[BNXT_ULP_CLASS_HID_325ac] = 3227,
+	[BNXT_ULP_CLASS_HID_3aeac] = 3228,
+	[BNXT_ULP_CLASS_HID_21afc] = 3229,
+	[BNXT_ULP_CLASS_HID_287fc] = 3230,
+	[BNXT_ULP_CLASS_HID_330fc] = 3231,
+	[BNXT_ULP_CLASS_HID_3bdfc] = 3232,
+	[BNXT_ULP_CLASS_HID_217b0] = 3233,
+	[BNXT_ULP_CLASS_HID_280b0] = 3234,
+	[BNXT_ULP_CLASS_HID_30db0] = 3235,
+	[BNXT_ULP_CLASS_HID_3b6b0] = 3236,
+	[BNXT_ULP_CLASS_HID_20860] = 3237,
+	[BNXT_ULP_CLASS_HID_2b560] = 3238,
+	[BNXT_ULP_CLASS_HID_33e60] = 3239,
+	[BNXT_ULP_CLASS_HID_3ab60] = 3240,
+	[BNXT_ULP_CLASS_HID_253c0] = 3241,
+	[BNXT_ULP_CLASS_HID_2dcc0] = 3242,
+	[BNXT_ULP_CLASS_HID_349c0] = 3243,
+	[BNXT_ULP_CLASS_HID_397f4] = 3244,
+	[BNXT_ULP_CLASS_HID_23f10] = 3245,
+	[BNXT_ULP_CLASS_HID_2a810] = 3246,
+	[BNXT_ULP_CLASS_HID_35510] = 3247,
+	[BNXT_ULP_CLASS_HID_3de10] = 3248,
+	[BNXT_ULP_CLASS_HID_23bc4] = 3249,
+	[BNXT_ULP_CLASS_HID_2a4c4] = 3250,
+	[BNXT_ULP_CLASS_HID_351c4] = 3251,
+	[BNXT_ULP_CLASS_HID_3dac4] = 3252,
+	[BNXT_ULP_CLASS_HID_22cf4] = 3253,
+	[BNXT_ULP_CLASS_HID_2d9f4] = 3254,
+	[BNXT_ULP_CLASS_HID_342f4] = 3255,
+	[BNXT_ULP_CLASS_HID_390a8] = 3256,
+	[BNXT_ULP_CLASS_HID_21908] = 3257,
+	[BNXT_ULP_CLASS_HID_28208] = 3258,
+	[BNXT_ULP_CLASS_HID_30f08] = 3259,
+	[BNXT_ULP_CLASS_HID_3b808] = 3260,
+	[BNXT_ULP_CLASS_HID_243a4] = 3261,
+	[BNXT_ULP_CLASS_HID_29158] = 3262,
+	[BNXT_ULP_CLASS_HID_31a58] = 3263,
+	[BNXT_ULP_CLASS_HID_38758] = 3264,
+	[BNXT_ULP_CLASS_HID_25c58] = 3265,
+	[BNXT_ULP_CLASS_HID_2c958] = 3266,
+	[BNXT_ULP_CLASS_HID_3170c] = 3267,
+	[BNXT_ULP_CLASS_HID_3800c] = 3268,
+	[BNXT_ULP_CLASS_HID_2123c] = 3269,
+	[BNXT_ULP_CLASS_HID_29f3c] = 3270,
+	[BNXT_ULP_CLASS_HID_3083c] = 3271,
+	[BNXT_ULP_CLASS_HID_3b53c] = 3272,
+	[BNXT_ULP_CLASS_HID_240a8] = 3273,
+	[BNXT_ULP_CLASS_HID_2cda8] = 3274,
+	[BNXT_ULP_CLASS_HID_31b5c] = 3275,
+	[BNXT_ULP_CLASS_HID_3845c] = 3276,
+	[BNXT_ULP_CLASS_HID_22ff8] = 3277,
+	[BNXT_ULP_CLASS_HID_2d8f8] = 3278,
+	[BNXT_ULP_CLASS_HID_345f8] = 3279,
+	[BNXT_ULP_CLASS_HID_393ac] = 3280,
+	[BNXT_ULP_CLASS_HID_228ac] = 3281,
+	[BNXT_ULP_CLASS_HID_2d5ac] = 3282,
+	[BNXT_ULP_CLASS_HID_35eac] = 3283,
+	[BNXT_ULP_CLASS_HID_3cbac] = 3284,
+	[BNXT_ULP_CLASS_HID_25d5c] = 3285,
+	[BNXT_ULP_CLASS_HID_2c65c] = 3286,
+	[BNXT_ULP_CLASS_HID_31410] = 3287,
+	[BNXT_ULP_CLASS_HID_38110] = 3288,
+	[BNXT_ULP_CLASS_HID_209f0] = 3289,
+	[BNXT_ULP_CLASS_HID_2b2f0] = 3290,
+	[BNXT_ULP_CLASS_HID_33ff0] = 3291,
+	[BNXT_ULP_CLASS_HID_3a8f0] = 3292,
+	[BNXT_ULP_CLASS_HID_214c0] = 3293,
+	[BNXT_ULP_CLASS_HID_281c0] = 3294,
+	[BNXT_ULP_CLASS_HID_30ac0] = 3295,
+	[BNXT_ULP_CLASS_HID_3b7c0] = 3296,
+	[BNXT_ULP_CLASS_HID_211f4] = 3297,
+	[BNXT_ULP_CLASS_HID_29af4] = 3298,
+	[BNXT_ULP_CLASS_HID_307f4] = 3299,
+	[BNXT_ULP_CLASS_HID_3b0f4] = 3300,
+	[BNXT_ULP_CLASS_HID_202a4] = 3301,
+	[BNXT_ULP_CLASS_HID_28fa4] = 3302,
+	[BNXT_ULP_CLASS_HID_338a4] = 3303,
+	[BNXT_ULP_CLASS_HID_3a5a4] = 3304,
+	[BNXT_ULP_CLASS_HID_22a04] = 3305,
+	[BNXT_ULP_CLASS_HID_2d704] = 3306,
+	[BNXT_ULP_CLASS_HID_34004] = 3307,
+	[BNXT_ULP_CLASS_HID_3cd04] = 3308,
+	[BNXT_ULP_CLASS_HID_23954] = 3309,
+	[BNXT_ULP_CLASS_HID_2a254] = 3310,
+	[BNXT_ULP_CLASS_HID_32f54] = 3311,
+	[BNXT_ULP_CLASS_HID_3d854] = 3312,
+	[BNXT_ULP_CLASS_HID_23208] = 3313,
+	[BNXT_ULP_CLASS_HID_2bf08] = 3314,
+	[BNXT_ULP_CLASS_HID_32808] = 3315,
+	[BNXT_ULP_CLASS_HID_3d508] = 3316,
+	[BNXT_ULP_CLASS_HID_22738] = 3317,
+	[BNXT_ULP_CLASS_HID_2d038] = 3318,
+	[BNXT_ULP_CLASS_HID_35d38] = 3319,
+	[BNXT_ULP_CLASS_HID_3c638] = 3320,
+	[BNXT_ULP_CLASS_HID_2134c] = 3321,
+	[BNXT_ULP_CLASS_HID_29c4c] = 3322,
+	[BNXT_ULP_CLASS_HID_3094c] = 3323,
+	[BNXT_ULP_CLASS_HID_3b24c] = 3324,
+	[BNXT_ULP_CLASS_HID_25de8] = 3325,
+	[BNXT_ULP_CLASS_HID_2c6e8] = 3326,
+	[BNXT_ULP_CLASS_HID_3149c] = 3327,
+	[BNXT_ULP_CLASS_HID_3819c] = 3328,
+	[BNXT_ULP_CLASS_HID_2569c] = 3329,
+	[BNXT_ULP_CLASS_HID_2c39c] = 3330,
+	[BNXT_ULP_CLASS_HID_31150] = 3331,
+	[BNXT_ULP_CLASS_HID_39a50] = 3332,
+	[BNXT_ULP_CLASS_HID_24b4c] = 3333,
+	[BNXT_ULP_CLASS_HID_29900] = 3334,
+	[BNXT_ULP_CLASS_HID_30200] = 3335,
+	[BNXT_ULP_CLASS_HID_38f00] = 3336,
+	[BNXT_ULP_CLASS_HID_22f74] = 3337,
+	[BNXT_ULP_CLASS_HID_2d874] = 3338,
+	[BNXT_ULP_CLASS_HID_34574] = 3339,
+	[BNXT_ULP_CLASS_HID_39328] = 3340,
+	[BNXT_ULP_CLASS_HID_23a44] = 3341,
+	[BNXT_ULP_CLASS_HID_2a744] = 3342,
+	[BNXT_ULP_CLASS_HID_35044] = 3343,
+	[BNXT_ULP_CLASS_HID_3dd44] = 3344,
+	[BNXT_ULP_CLASS_HID_23778] = 3345,
+	[BNXT_ULP_CLASS_HID_2a078] = 3346,
+	[BNXT_ULP_CLASS_HID_32d78] = 3347,
+	[BNXT_ULP_CLASS_HID_3d678] = 3348,
+	[BNXT_ULP_CLASS_HID_22828] = 3349,
+	[BNXT_ULP_CLASS_HID_2d528] = 3350,
+	[BNXT_ULP_CLASS_HID_35e28] = 3351,
+	[BNXT_ULP_CLASS_HID_3cb28] = 3352,
+	[BNXT_ULP_CLASS_HID_214bc] = 3353,
+	[BNXT_ULP_CLASS_HID_281bc] = 3354,
+	[BNXT_ULP_CLASS_HID_30abc] = 3355,
+	[BNXT_ULP_CLASS_HID_3b7bc] = 3356,
+	[BNXT_ULP_CLASS_HID_25ed8] = 3357,
+	[BNXT_ULP_CLASS_HID_2cbd8] = 3358,
+	[BNXT_ULP_CLASS_HID_3198c] = 3359,
+	[BNXT_ULP_CLASS_HID_3828c] = 3360,
+	[BNXT_ULP_CLASS_HID_25b8c] = 3361,
+	[BNXT_ULP_CLASS_HID_2c48c] = 3362,
+	[BNXT_ULP_CLASS_HID_31240] = 3363,
+	[BNXT_ULP_CLASS_HID_39f40] = 3364,
+	[BNXT_ULP_CLASS_HID_21170] = 3365,
+	[BNXT_ULP_CLASS_HID_29a70] = 3366,
+	[BNXT_ULP_CLASS_HID_30770] = 3367,
+	[BNXT_ULP_CLASS_HID_3b070] = 3368,
+	[BNXT_ULP_CLASS_HID_238d0] = 3369,
+	[BNXT_ULP_CLASS_HID_2a5d0] = 3370,
+	[BNXT_ULP_CLASS_HID_32ed0] = 3371,
+	[BNXT_ULP_CLASS_HID_3dbd0] = 3372,
+	[BNXT_ULP_CLASS_HID_20420] = 3373,
+	[BNXT_ULP_CLASS_HID_2b120] = 3374,
+	[BNXT_ULP_CLASS_HID_33a20] = 3375,
+	[BNXT_ULP_CLASS_HID_3a720] = 3376,
+	[BNXT_ULP_CLASS_HID_200d4] = 3377,
+	[BNXT_ULP_CLASS_HID_28dd4] = 3378,
+	[BNXT_ULP_CLASS_HID_336d4] = 3379,
+	[BNXT_ULP_CLASS_HID_3a3d4] = 3380,
+	[BNXT_ULP_CLASS_HID_23584] = 3381,
+	[BNXT_ULP_CLASS_HID_2be84] = 3382,
+	[BNXT_ULP_CLASS_HID_32b84] = 3383,
+	[BNXT_ULP_CLASS_HID_3d484] = 3384,
+	[BNXT_ULP_CLASS_HID_25d64] = 3385,
+	[BNXT_ULP_CLASS_HID_2c664] = 3386,
+	[BNXT_ULP_CLASS_HID_31418] = 3387,
+	[BNXT_ULP_CLASS_HID_38118] = 3388,
+	[BNXT_ULP_CLASS_HID_228b4] = 3389,
+	[BNXT_ULP_CLASS_HID_2d5b4] = 3390,
+	[BNXT_ULP_CLASS_HID_35eb4] = 3391,
+	[BNXT_ULP_CLASS_HID_3cbb4] = 3392,
+	[BNXT_ULP_CLASS_HID_22568] = 3393,
+	[BNXT_ULP_CLASS_HID_2ae68] = 3394,
+	[BNXT_ULP_CLASS_HID_35b68] = 3395,
+	[BNXT_ULP_CLASS_HID_3c468] = 3396,
+	[BNXT_ULP_CLASS_HID_25618] = 3397,
+	[BNXT_ULP_CLASS_HID_2c318] = 3398,
+	[BNXT_ULP_CLASS_HID_310cc] = 3399,
+	[BNXT_ULP_CLASS_HID_39dcc] = 3400,
+	[BNXT_ULP_CLASS_HID_229b8] = 3401,
+	[BNXT_ULP_CLASS_HID_2d2b8] = 3402,
+	[BNXT_ULP_CLASS_HID_35fb8] = 3403,
+	[BNXT_ULP_CLASS_HID_3c8b8] = 3404,
+	[BNXT_ULP_CLASS_HID_23488] = 3405,
+	[BNXT_ULP_CLASS_HID_2a188] = 3406,
+	[BNXT_ULP_CLASS_HID_32a88] = 3407,
+	[BNXT_ULP_CLASS_HID_3d788] = 3408,
+	[BNXT_ULP_CLASS_HID_231bc] = 3409,
+	[BNXT_ULP_CLASS_HID_2babc] = 3410,
+	[BNXT_ULP_CLASS_HID_327bc] = 3411,
+	[BNXT_ULP_CLASS_HID_3d0bc] = 3412,
+	[BNXT_ULP_CLASS_HID_2226c] = 3413,
+	[BNXT_ULP_CLASS_HID_2af6c] = 3414,
+	[BNXT_ULP_CLASS_HID_3586c] = 3415,
+	[BNXT_ULP_CLASS_HID_3c56c] = 3416,
+	[BNXT_ULP_CLASS_HID_24dcc] = 3417,
+	[BNXT_ULP_CLASS_HID_29b80] = 3418,
+	[BNXT_ULP_CLASS_HID_30480] = 3419,
+	[BNXT_ULP_CLASS_HID_3b180] = 3420,
+	[BNXT_ULP_CLASS_HID_2591c] = 3421,
+	[BNXT_ULP_CLASS_HID_2c21c] = 3422,
+	[BNXT_ULP_CLASS_HID_313d0] = 3423,
+	[BNXT_ULP_CLASS_HID_39cd0] = 3424,
+	[BNXT_ULP_CLASS_HID_255d0] = 3425,
+	[BNXT_ULP_CLASS_HID_2ded0] = 3426,
+	[BNXT_ULP_CLASS_HID_34bd0] = 3427,
+	[BNXT_ULP_CLASS_HID_39984] = 3428,
+	[BNXT_ULP_CLASS_HID_24680] = 3429,
+	[BNXT_ULP_CLASS_HID_294b4] = 3430,
+	[BNXT_ULP_CLASS_HID_301b4] = 3431,
+	[BNXT_ULP_CLASS_HID_38ab4] = 3432,
+	[BNXT_ULP_CLASS_HID_23314] = 3433,
+	[BNXT_ULP_CLASS_HID_2bc14] = 3434,
+	[BNXT_ULP_CLASS_HID_32914] = 3435,
+	[BNXT_ULP_CLASS_HID_3d214] = 3436,
+	[BNXT_ULP_CLASS_HID_21e64] = 3437,
+	[BNXT_ULP_CLASS_HID_28b64] = 3438,
+	[BNXT_ULP_CLASS_HID_33464] = 3439,
+	[BNXT_ULP_CLASS_HID_3a164] = 3440,
+	[BNXT_ULP_CLASS_HID_21b18] = 3441,
+	[BNXT_ULP_CLASS_HID_28418] = 3442,
+	[BNXT_ULP_CLASS_HID_33118] = 3443,
+	[BNXT_ULP_CLASS_HID_3ba18] = 3444,
+	[BNXT_ULP_CLASS_HID_20fc8] = 3445,
+	[BNXT_ULP_CLASS_HID_2b8c8] = 3446,
+	[BNXT_ULP_CLASS_HID_325c8] = 3447,
+	[BNXT_ULP_CLASS_HID_3aec8] = 3448,
+	[BNXT_ULP_CLASS_HID_257a8] = 3449,
+	[BNXT_ULP_CLASS_HID_2c0a8] = 3450,
+	[BNXT_ULP_CLASS_HID_34da8] = 3451,
+	[BNXT_ULP_CLASS_HID_39b5c] = 3452,
+	[BNXT_ULP_CLASS_HID_222f8] = 3453,
+	[BNXT_ULP_CLASS_HID_2aff8] = 3454,
+	[BNXT_ULP_CLASS_HID_358f8] = 3455,
+	[BNXT_ULP_CLASS_HID_3c5f8] = 3456,
+	[BNXT_ULP_CLASS_HID_23fac] = 3457,
+	[BNXT_ULP_CLASS_HID_2a8ac] = 3458,
+	[BNXT_ULP_CLASS_HID_355ac] = 3459,
+	[BNXT_ULP_CLASS_HID_3deac] = 3460,
+	[BNXT_ULP_CLASS_HID_2505c] = 3461,
+	[BNXT_ULP_CLASS_HID_2dd5c] = 3462,
+	[BNXT_ULP_CLASS_HID_3465c] = 3463,
+	[BNXT_ULP_CLASS_HID_39410] = 3464,
+	[BNXT_ULP_CLASS_HID_223fc] = 3465,
+	[BNXT_ULP_CLASS_HID_2acfc] = 3466,
+	[BNXT_ULP_CLASS_HID_359fc] = 3467,
+	[BNXT_ULP_CLASS_HID_3c2fc] = 3468,
+	[BNXT_ULP_CLASS_HID_20ecc] = 3469,
+	[BNXT_ULP_CLASS_HID_2bbcc] = 3470,
+	[BNXT_ULP_CLASS_HID_324cc] = 3471,
+	[BNXT_ULP_CLASS_HID_3d1cc] = 3472,
+	[BNXT_ULP_CLASS_HID_20b80] = 3473,
+	[BNXT_ULP_CLASS_HID_2b480] = 3474,
+	[BNXT_ULP_CLASS_HID_32180] = 3475,
+	[BNXT_ULP_CLASS_HID_3aa80] = 3476,
+	[BNXT_ULP_CLASS_HID_23cb0] = 3477,
+	[BNXT_ULP_CLASS_HID_2a9b0] = 3478,
+	[BNXT_ULP_CLASS_HID_352b0] = 3479,
+	[BNXT_ULP_CLASS_HID_3dfb0] = 3480,
+	[BNXT_ULP_CLASS_HID_24410] = 3481,
+	[BNXT_ULP_CLASS_HID_295c4] = 3482,
+	[BNXT_ULP_CLASS_HID_31ec4] = 3483,
+	[BNXT_ULP_CLASS_HID_38bc4] = 3484,
+	[BNXT_ULP_CLASS_HID_25360] = 3485,
+	[BNXT_ULP_CLASS_HID_2dc60] = 3486,
+	[BNXT_ULP_CLASS_HID_34960] = 3487,
+	[BNXT_ULP_CLASS_HID_39714] = 3488,
+	[BNXT_ULP_CLASS_HID_22c14] = 3489,
+	[BNXT_ULP_CLASS_HID_2d914] = 3490,
+	[BNXT_ULP_CLASS_HID_34214] = 3491,
+	[BNXT_ULP_CLASS_HID_393c8] = 3492,
+	[BNXT_ULP_CLASS_HID_240c4] = 3493,
+	[BNXT_ULP_CLASS_HID_2cdc4] = 3494,
+	[BNXT_ULP_CLASS_HID_31bf8] = 3495,
+	[BNXT_ULP_CLASS_HID_384f8] = 3496,
+	[BNXT_ULP_CLASS_HID_23dc0] = 3497,
+	[BNXT_ULP_CLASS_HID_2a6c0] = 3498,
+	[BNXT_ULP_CLASS_HID_353c0] = 3499,
+	[BNXT_ULP_CLASS_HID_3dcc0] = 3500,
+	[BNXT_ULP_CLASS_HID_20910] = 3501,
+	[BNXT_ULP_CLASS_HID_2b210] = 3502,
+	[BNXT_ULP_CLASS_HID_33f10] = 3503,
+	[BNXT_ULP_CLASS_HID_3a810] = 3504,
+	[BNXT_ULP_CLASS_HID_205c4] = 3505,
+	[BNXT_ULP_CLASS_HID_28ec4] = 3506,
+	[BNXT_ULP_CLASS_HID_33bc4] = 3507,
+	[BNXT_ULP_CLASS_HID_3a4c4] = 3508,
+	[BNXT_ULP_CLASS_HID_236f4] = 3509,
+	[BNXT_ULP_CLASS_HID_2a3f4] = 3510,
+	[BNXT_ULP_CLASS_HID_32cf4] = 3511,
+	[BNXT_ULP_CLASS_HID_3d9f4] = 3512,
+	[BNXT_ULP_CLASS_HID_25e54] = 3513,
+	[BNXT_ULP_CLASS_HID_2cb54] = 3514,
+	[BNXT_ULP_CLASS_HID_31908] = 3515,
+	[BNXT_ULP_CLASS_HID_38208] = 3516,
+	[BNXT_ULP_CLASS_HID_22da4] = 3517,
+	[BNXT_ULP_CLASS_HID_2d6a4] = 3518,
+	[BNXT_ULP_CLASS_HID_343a4] = 3519,
+	[BNXT_ULP_CLASS_HID_39158] = 3520,
+	[BNXT_ULP_CLASS_HID_22658] = 3521,
+	[BNXT_ULP_CLASS_HID_2d358] = 3522,
+	[BNXT_ULP_CLASS_HID_35c58] = 3523,
+	[BNXT_ULP_CLASS_HID_3c958] = 3524,
+	[BNXT_ULP_CLASS_HID_25b08] = 3525,
+	[BNXT_ULP_CLASS_HID_2c408] = 3526,
+	[BNXT_ULP_CLASS_HID_3123c] = 3527,
+	[BNXT_ULP_CLASS_HID_39f3c] = 3528,
+	[BNXT_ULP_CLASS_HID_34a8] = 3529,
+	[BNXT_ULP_CLASS_HID_3a64] = 3530,
+	[BNXT_ULP_CLASS_HID_5ef8] = 3531,
+	[BNXT_ULP_CLASS_HID_07c0] = 3532,
+	[BNXT_ULP_CLASS_HID_2854] = 3533,
+	[BNXT_ULP_CLASS_HID_593c] = 3534,
+	[BNXT_ULP_CLASS_HID_1e04] = 3535,
+	[BNXT_ULP_CLASS_HID_2298] = 3536,
+	[BNXT_ULP_CLASS_HID_24644] = 3537,
+	[BNXT_ULP_CLASS_HID_29438] = 3538,
+	[BNXT_ULP_CLASS_HID_30138] = 3539,
+	[BNXT_ULP_CLASS_HID_38a38] = 3540,
+	[BNXT_ULP_CLASS_HID_25594] = 3541,
+	[BNXT_ULP_CLASS_HID_2de94] = 3542,
+	[BNXT_ULP_CLASS_HID_34b94] = 3543,
+	[BNXT_ULP_CLASS_HID_39948] = 3544,
+	[BNXT_ULP_CLASS_HID_22e48] = 3545,
+	[BNXT_ULP_CLASS_HID_2db48] = 3546,
+	[BNXT_ULP_CLASS_HID_34448] = 3547,
+	[BNXT_ULP_CLASS_HID_3923c] = 3548,
+	[BNXT_ULP_CLASS_HID_24338] = 3549,
+	[BNXT_ULP_CLASS_HID_290ec] = 3550,
+	[BNXT_ULP_CLASS_HID_31dec] = 3551,
+	[BNXT_ULP_CLASS_HID_386ec] = 3552,
+	[BNXT_ULP_CLASS_HID_20f8c] = 3553,
+	[BNXT_ULP_CLASS_HID_2b88c] = 3554,
+	[BNXT_ULP_CLASS_HID_3258c] = 3555,
+	[BNXT_ULP_CLASS_HID_3ae8c] = 3556,
+	[BNXT_ULP_CLASS_HID_21adc] = 3557,
+	[BNXT_ULP_CLASS_HID_287dc] = 3558,
+	[BNXT_ULP_CLASS_HID_330dc] = 3559,
+	[BNXT_ULP_CLASS_HID_3bddc] = 3560,
+	[BNXT_ULP_CLASS_HID_21790] = 3561,
+	[BNXT_ULP_CLASS_HID_28090] = 3562,
+	[BNXT_ULP_CLASS_HID_30d90] = 3563,
+	[BNXT_ULP_CLASS_HID_3b690] = 3564,
+	[BNXT_ULP_CLASS_HID_20840] = 3565,
+	[BNXT_ULP_CLASS_HID_2b540] = 3566,
+	[BNXT_ULP_CLASS_HID_33e40] = 3567,
+	[BNXT_ULP_CLASS_HID_3ab40] = 3568,
+	[BNXT_ULP_CLASS_HID_253e0] = 3569,
+	[BNXT_ULP_CLASS_HID_2dce0] = 3570,
+	[BNXT_ULP_CLASS_HID_349e0] = 3571,
+	[BNXT_ULP_CLASS_HID_397d4] = 3572,
+	[BNXT_ULP_CLASS_HID_23f30] = 3573,
+	[BNXT_ULP_CLASS_HID_2a830] = 3574,
+	[BNXT_ULP_CLASS_HID_35530] = 3575,
+	[BNXT_ULP_CLASS_HID_3de30] = 3576,
+	[BNXT_ULP_CLASS_HID_23be4] = 3577,
+	[BNXT_ULP_CLASS_HID_2a4e4] = 3578,
+	[BNXT_ULP_CLASS_HID_351e4] = 3579,
+	[BNXT_ULP_CLASS_HID_3dae4] = 3580,
+	[BNXT_ULP_CLASS_HID_22cd4] = 3581,
+	[BNXT_ULP_CLASS_HID_2d9d4] = 3582,
+	[BNXT_ULP_CLASS_HID_342d4] = 3583,
+	[BNXT_ULP_CLASS_HID_39088] = 3584,
+	[BNXT_ULP_CLASS_HID_21928] = 3585,
+	[BNXT_ULP_CLASS_HID_28228] = 3586,
+	[BNXT_ULP_CLASS_HID_30f28] = 3587,
+	[BNXT_ULP_CLASS_HID_3b828] = 3588,
+	[BNXT_ULP_CLASS_HID_24384] = 3589,
+	[BNXT_ULP_CLASS_HID_29178] = 3590,
+	[BNXT_ULP_CLASS_HID_31a78] = 3591,
+	[BNXT_ULP_CLASS_HID_38778] = 3592,
+	[BNXT_ULP_CLASS_HID_25c78] = 3593,
+	[BNXT_ULP_CLASS_HID_2c978] = 3594,
+	[BNXT_ULP_CLASS_HID_3172c] = 3595,
+	[BNXT_ULP_CLASS_HID_3802c] = 3596,
+	[BNXT_ULP_CLASS_HID_2121c] = 3597,
+	[BNXT_ULP_CLASS_HID_29f1c] = 3598,
+	[BNXT_ULP_CLASS_HID_3081c] = 3599,
+	[BNXT_ULP_CLASS_HID_3b51c] = 3600,
+	[BNXT_ULP_CLASS_HID_24088] = 3601,
+	[BNXT_ULP_CLASS_HID_2cd88] = 3602,
+	[BNXT_ULP_CLASS_HID_31b7c] = 3603,
+	[BNXT_ULP_CLASS_HID_3847c] = 3604,
+	[BNXT_ULP_CLASS_HID_22fd8] = 3605,
+	[BNXT_ULP_CLASS_HID_2d8d8] = 3606,
+	[BNXT_ULP_CLASS_HID_345d8] = 3607,
+	[BNXT_ULP_CLASS_HID_3938c] = 3608,
+	[BNXT_ULP_CLASS_HID_2288c] = 3609,
+	[BNXT_ULP_CLASS_HID_2d58c] = 3610,
+	[BNXT_ULP_CLASS_HID_35e8c] = 3611,
+	[BNXT_ULP_CLASS_HID_3cb8c] = 3612,
+	[BNXT_ULP_CLASS_HID_25d7c] = 3613,
+	[BNXT_ULP_CLASS_HID_2c67c] = 3614,
+	[BNXT_ULP_CLASS_HID_31430] = 3615,
+	[BNXT_ULP_CLASS_HID_38130] = 3616,
+	[BNXT_ULP_CLASS_HID_209d0] = 3617,
+	[BNXT_ULP_CLASS_HID_2b2d0] = 3618,
+	[BNXT_ULP_CLASS_HID_33fd0] = 3619,
+	[BNXT_ULP_CLASS_HID_3a8d0] = 3620,
+	[BNXT_ULP_CLASS_HID_214e0] = 3621,
+	[BNXT_ULP_CLASS_HID_281e0] = 3622,
+	[BNXT_ULP_CLASS_HID_30ae0] = 3623,
+	[BNXT_ULP_CLASS_HID_3b7e0] = 3624,
+	[BNXT_ULP_CLASS_HID_211d4] = 3625,
+	[BNXT_ULP_CLASS_HID_29ad4] = 3626,
+	[BNXT_ULP_CLASS_HID_307d4] = 3627,
+	[BNXT_ULP_CLASS_HID_3b0d4] = 3628,
+	[BNXT_ULP_CLASS_HID_20284] = 3629,
+	[BNXT_ULP_CLASS_HID_28f84] = 3630,
+	[BNXT_ULP_CLASS_HID_33884] = 3631,
+	[BNXT_ULP_CLASS_HID_3a584] = 3632,
+	[BNXT_ULP_CLASS_HID_22a24] = 3633,
+	[BNXT_ULP_CLASS_HID_2d724] = 3634,
+	[BNXT_ULP_CLASS_HID_34024] = 3635,
+	[BNXT_ULP_CLASS_HID_3cd24] = 3636,
+	[BNXT_ULP_CLASS_HID_23974] = 3637,
+	[BNXT_ULP_CLASS_HID_2a274] = 3638,
+	[BNXT_ULP_CLASS_HID_32f74] = 3639,
+	[BNXT_ULP_CLASS_HID_3d874] = 3640,
+	[BNXT_ULP_CLASS_HID_23228] = 3641,
+	[BNXT_ULP_CLASS_HID_2bf28] = 3642,
+	[BNXT_ULP_CLASS_HID_32828] = 3643,
+	[BNXT_ULP_CLASS_HID_3d528] = 3644,
+	[BNXT_ULP_CLASS_HID_22718] = 3645,
+	[BNXT_ULP_CLASS_HID_2d018] = 3646,
+	[BNXT_ULP_CLASS_HID_35d18] = 3647,
+	[BNXT_ULP_CLASS_HID_3c618] = 3648,
+	[BNXT_ULP_CLASS_HID_2136c] = 3649,
+	[BNXT_ULP_CLASS_HID_29c6c] = 3650,
+	[BNXT_ULP_CLASS_HID_3096c] = 3651,
+	[BNXT_ULP_CLASS_HID_3b26c] = 3652,
+	[BNXT_ULP_CLASS_HID_25dc8] = 3653,
+	[BNXT_ULP_CLASS_HID_2c6c8] = 3654,
+	[BNXT_ULP_CLASS_HID_314bc] = 3655,
+	[BNXT_ULP_CLASS_HID_381bc] = 3656,
+	[BNXT_ULP_CLASS_HID_256bc] = 3657,
+	[BNXT_ULP_CLASS_HID_2c3bc] = 3658,
+	[BNXT_ULP_CLASS_HID_31170] = 3659,
+	[BNXT_ULP_CLASS_HID_39a70] = 3660,
+	[BNXT_ULP_CLASS_HID_24b6c] = 3661,
+	[BNXT_ULP_CLASS_HID_29920] = 3662,
+	[BNXT_ULP_CLASS_HID_30220] = 3663,
+	[BNXT_ULP_CLASS_HID_38f20] = 3664,
+	[BNXT_ULP_CLASS_HID_22f54] = 3665,
+	[BNXT_ULP_CLASS_HID_2d854] = 3666,
+	[BNXT_ULP_CLASS_HID_34554] = 3667,
+	[BNXT_ULP_CLASS_HID_39308] = 3668,
+	[BNXT_ULP_CLASS_HID_23a64] = 3669,
+	[BNXT_ULP_CLASS_HID_2a764] = 3670,
+	[BNXT_ULP_CLASS_HID_35064] = 3671,
+	[BNXT_ULP_CLASS_HID_3dd64] = 3672,
+	[BNXT_ULP_CLASS_HID_23758] = 3673,
+	[BNXT_ULP_CLASS_HID_2a058] = 3674,
+	[BNXT_ULP_CLASS_HID_32d58] = 3675,
+	[BNXT_ULP_CLASS_HID_3d658] = 3676,
+	[BNXT_ULP_CLASS_HID_22808] = 3677,
+	[BNXT_ULP_CLASS_HID_2d508] = 3678,
+	[BNXT_ULP_CLASS_HID_35e08] = 3679,
+	[BNXT_ULP_CLASS_HID_3cb08] = 3680,
+	[BNXT_ULP_CLASS_HID_2149c] = 3681,
+	[BNXT_ULP_CLASS_HID_2819c] = 3682,
+	[BNXT_ULP_CLASS_HID_30a9c] = 3683,
+	[BNXT_ULP_CLASS_HID_3b79c] = 3684,
+	[BNXT_ULP_CLASS_HID_25ef8] = 3685,
+	[BNXT_ULP_CLASS_HID_2cbf8] = 3686,
+	[BNXT_ULP_CLASS_HID_319ac] = 3687,
+	[BNXT_ULP_CLASS_HID_382ac] = 3688,
+	[BNXT_ULP_CLASS_HID_25bac] = 3689,
+	[BNXT_ULP_CLASS_HID_2c4ac] = 3690,
+	[BNXT_ULP_CLASS_HID_31260] = 3691,
+	[BNXT_ULP_CLASS_HID_39f60] = 3692,
+	[BNXT_ULP_CLASS_HID_21150] = 3693,
+	[BNXT_ULP_CLASS_HID_29a50] = 3694,
+	[BNXT_ULP_CLASS_HID_30750] = 3695,
+	[BNXT_ULP_CLASS_HID_3b050] = 3696,
+	[BNXT_ULP_CLASS_HID_238f0] = 3697,
+	[BNXT_ULP_CLASS_HID_2a5f0] = 3698,
+	[BNXT_ULP_CLASS_HID_32ef0] = 3699,
+	[BNXT_ULP_CLASS_HID_3dbf0] = 3700,
+	[BNXT_ULP_CLASS_HID_20400] = 3701,
+	[BNXT_ULP_CLASS_HID_2b100] = 3702,
+	[BNXT_ULP_CLASS_HID_33a00] = 3703,
+	[BNXT_ULP_CLASS_HID_3a700] = 3704,
+	[BNXT_ULP_CLASS_HID_200f4] = 3705,
+	[BNXT_ULP_CLASS_HID_28df4] = 3706,
+	[BNXT_ULP_CLASS_HID_336f4] = 3707,
+	[BNXT_ULP_CLASS_HID_3a3f4] = 3708,
+	[BNXT_ULP_CLASS_HID_235a4] = 3709,
+	[BNXT_ULP_CLASS_HID_2bea4] = 3710,
+	[BNXT_ULP_CLASS_HID_32ba4] = 3711,
+	[BNXT_ULP_CLASS_HID_3d4a4] = 3712,
+	[BNXT_ULP_CLASS_HID_25d44] = 3713,
+	[BNXT_ULP_CLASS_HID_2c644] = 3714,
+	[BNXT_ULP_CLASS_HID_31438] = 3715,
+	[BNXT_ULP_CLASS_HID_38138] = 3716,
+	[BNXT_ULP_CLASS_HID_22894] = 3717,
+	[BNXT_ULP_CLASS_HID_2d594] = 3718,
+	[BNXT_ULP_CLASS_HID_35e94] = 3719,
+	[BNXT_ULP_CLASS_HID_3cb94] = 3720,
+	[BNXT_ULP_CLASS_HID_22548] = 3721,
+	[BNXT_ULP_CLASS_HID_2ae48] = 3722,
+	[BNXT_ULP_CLASS_HID_35b48] = 3723,
+	[BNXT_ULP_CLASS_HID_3c448] = 3724,
+	[BNXT_ULP_CLASS_HID_25638] = 3725,
+	[BNXT_ULP_CLASS_HID_2c338] = 3726,
+	[BNXT_ULP_CLASS_HID_310ec] = 3727,
+	[BNXT_ULP_CLASS_HID_39dec] = 3728,
+	[BNXT_ULP_CLASS_HID_22998] = 3729,
+	[BNXT_ULP_CLASS_HID_2d298] = 3730,
+	[BNXT_ULP_CLASS_HID_35f98] = 3731,
+	[BNXT_ULP_CLASS_HID_3c898] = 3732,
+	[BNXT_ULP_CLASS_HID_234a8] = 3733,
+	[BNXT_ULP_CLASS_HID_2a1a8] = 3734,
+	[BNXT_ULP_CLASS_HID_32aa8] = 3735,
+	[BNXT_ULP_CLASS_HID_3d7a8] = 3736,
+	[BNXT_ULP_CLASS_HID_2319c] = 3737,
+	[BNXT_ULP_CLASS_HID_2ba9c] = 3738,
+	[BNXT_ULP_CLASS_HID_3279c] = 3739,
+	[BNXT_ULP_CLASS_HID_3d09c] = 3740,
+	[BNXT_ULP_CLASS_HID_2224c] = 3741,
+	[BNXT_ULP_CLASS_HID_2af4c] = 3742,
+	[BNXT_ULP_CLASS_HID_3584c] = 3743,
+	[BNXT_ULP_CLASS_HID_3c54c] = 3744,
+	[BNXT_ULP_CLASS_HID_24dec] = 3745,
+	[BNXT_ULP_CLASS_HID_29ba0] = 3746,
+	[BNXT_ULP_CLASS_HID_304a0] = 3747,
+	[BNXT_ULP_CLASS_HID_3b1a0] = 3748,
+	[BNXT_ULP_CLASS_HID_2593c] = 3749,
+	[BNXT_ULP_CLASS_HID_2c23c] = 3750,
+	[BNXT_ULP_CLASS_HID_313f0] = 3751,
+	[BNXT_ULP_CLASS_HID_39cf0] = 3752,
+	[BNXT_ULP_CLASS_HID_255f0] = 3753,
+	[BNXT_ULP_CLASS_HID_2def0] = 3754,
+	[BNXT_ULP_CLASS_HID_34bf0] = 3755,
+	[BNXT_ULP_CLASS_HID_399a4] = 3756,
+	[BNXT_ULP_CLASS_HID_246a0] = 3757,
+	[BNXT_ULP_CLASS_HID_29494] = 3758,
+	[BNXT_ULP_CLASS_HID_30194] = 3759,
+	[BNXT_ULP_CLASS_HID_38a94] = 3760,
+	[BNXT_ULP_CLASS_HID_23334] = 3761,
+	[BNXT_ULP_CLASS_HID_2bc34] = 3762,
+	[BNXT_ULP_CLASS_HID_32934] = 3763,
+	[BNXT_ULP_CLASS_HID_3d234] = 3764,
+	[BNXT_ULP_CLASS_HID_21e44] = 3765,
+	[BNXT_ULP_CLASS_HID_28b44] = 3766,
+	[BNXT_ULP_CLASS_HID_33444] = 3767,
+	[BNXT_ULP_CLASS_HID_3a144] = 3768,
+	[BNXT_ULP_CLASS_HID_21b38] = 3769,
+	[BNXT_ULP_CLASS_HID_28438] = 3770,
+	[BNXT_ULP_CLASS_HID_33138] = 3771,
+	[BNXT_ULP_CLASS_HID_3ba38] = 3772,
+	[BNXT_ULP_CLASS_HID_20fe8] = 3773,
+	[BNXT_ULP_CLASS_HID_2b8e8] = 3774,
+	[BNXT_ULP_CLASS_HID_325e8] = 3775,
+	[BNXT_ULP_CLASS_HID_3aee8] = 3776,
+	[BNXT_ULP_CLASS_HID_25788] = 3777,
+	[BNXT_ULP_CLASS_HID_2c088] = 3778,
+	[BNXT_ULP_CLASS_HID_34d88] = 3779,
+	[BNXT_ULP_CLASS_HID_39b7c] = 3780,
+	[BNXT_ULP_CLASS_HID_222d8] = 3781,
+	[BNXT_ULP_CLASS_HID_2afd8] = 3782,
+	[BNXT_ULP_CLASS_HID_358d8] = 3783,
+	[BNXT_ULP_CLASS_HID_3c5d8] = 3784,
+	[BNXT_ULP_CLASS_HID_23f8c] = 3785,
+	[BNXT_ULP_CLASS_HID_2a88c] = 3786,
+	[BNXT_ULP_CLASS_HID_3558c] = 3787,
+	[BNXT_ULP_CLASS_HID_3de8c] = 3788,
+	[BNXT_ULP_CLASS_HID_2507c] = 3789,
+	[BNXT_ULP_CLASS_HID_2dd7c] = 3790,
+	[BNXT_ULP_CLASS_HID_3467c] = 3791,
+	[BNXT_ULP_CLASS_HID_39430] = 3792,
+	[BNXT_ULP_CLASS_HID_223dc] = 3793,
+	[BNXT_ULP_CLASS_HID_2acdc] = 3794,
+	[BNXT_ULP_CLASS_HID_359dc] = 3795,
+	[BNXT_ULP_CLASS_HID_3c2dc] = 3796,
+	[BNXT_ULP_CLASS_HID_20eec] = 3797,
+	[BNXT_ULP_CLASS_HID_2bbec] = 3798,
+	[BNXT_ULP_CLASS_HID_324ec] = 3799,
+	[BNXT_ULP_CLASS_HID_3d1ec] = 3800,
+	[BNXT_ULP_CLASS_HID_20ba0] = 3801,
+	[BNXT_ULP_CLASS_HID_2b4a0] = 3802,
+	[BNXT_ULP_CLASS_HID_321a0] = 3803,
+	[BNXT_ULP_CLASS_HID_3aaa0] = 3804,
+	[BNXT_ULP_CLASS_HID_23c90] = 3805,
+	[BNXT_ULP_CLASS_HID_2a990] = 3806,
+	[BNXT_ULP_CLASS_HID_35290] = 3807,
+	[BNXT_ULP_CLASS_HID_3df90] = 3808,
+	[BNXT_ULP_CLASS_HID_24430] = 3809,
+	[BNXT_ULP_CLASS_HID_295e4] = 3810,
+	[BNXT_ULP_CLASS_HID_31ee4] = 3811,
+	[BNXT_ULP_CLASS_HID_38be4] = 3812,
+	[BNXT_ULP_CLASS_HID_25340] = 3813,
+	[BNXT_ULP_CLASS_HID_2dc40] = 3814,
+	[BNXT_ULP_CLASS_HID_34940] = 3815,
+	[BNXT_ULP_CLASS_HID_39734] = 3816,
+	[BNXT_ULP_CLASS_HID_22c34] = 3817,
+	[BNXT_ULP_CLASS_HID_2d934] = 3818,
+	[BNXT_ULP_CLASS_HID_34234] = 3819,
+	[BNXT_ULP_CLASS_HID_393e8] = 3820,
+	[BNXT_ULP_CLASS_HID_240e4] = 3821,
+	[BNXT_ULP_CLASS_HID_2cde4] = 3822,
+	[BNXT_ULP_CLASS_HID_31bd8] = 3823,
+	[BNXT_ULP_CLASS_HID_384d8] = 3824,
+	[BNXT_ULP_CLASS_HID_23de0] = 3825,
+	[BNXT_ULP_CLASS_HID_2a6e0] = 3826,
+	[BNXT_ULP_CLASS_HID_353e0] = 3827,
+	[BNXT_ULP_CLASS_HID_3dce0] = 3828,
+	[BNXT_ULP_CLASS_HID_20930] = 3829,
+	[BNXT_ULP_CLASS_HID_2b230] = 3830,
+	[BNXT_ULP_CLASS_HID_33f30] = 3831,
+	[BNXT_ULP_CLASS_HID_3a830] = 3832,
+	[BNXT_ULP_CLASS_HID_205e4] = 3833,
+	[BNXT_ULP_CLASS_HID_28ee4] = 3834,
+	[BNXT_ULP_CLASS_HID_33be4] = 3835,
+	[BNXT_ULP_CLASS_HID_3a4e4] = 3836,
+	[BNXT_ULP_CLASS_HID_236d4] = 3837,
+	[BNXT_ULP_CLASS_HID_2a3d4] = 3838,
+	[BNXT_ULP_CLASS_HID_32cd4] = 3839,
+	[BNXT_ULP_CLASS_HID_3d9d4] = 3840,
+	[BNXT_ULP_CLASS_HID_25e74] = 3841,
+	[BNXT_ULP_CLASS_HID_2cb74] = 3842,
+	[BNXT_ULP_CLASS_HID_31928] = 3843,
+	[BNXT_ULP_CLASS_HID_38228] = 3844,
+	[BNXT_ULP_CLASS_HID_22d84] = 3845,
+	[BNXT_ULP_CLASS_HID_2d684] = 3846,
+	[BNXT_ULP_CLASS_HID_34384] = 3847,
+	[BNXT_ULP_CLASS_HID_39178] = 3848,
+	[BNXT_ULP_CLASS_HID_22678] = 3849,
+	[BNXT_ULP_CLASS_HID_2d378] = 3850,
+	[BNXT_ULP_CLASS_HID_35c78] = 3851,
+	[BNXT_ULP_CLASS_HID_3c978] = 3852,
+	[BNXT_ULP_CLASS_HID_25b28] = 3853,
+	[BNXT_ULP_CLASS_HID_2c428] = 3854,
+	[BNXT_ULP_CLASS_HID_3121c] = 3855,
+	[BNXT_ULP_CLASS_HID_39f1c] = 3856,
+	[BNXT_ULP_CLASS_HID_3488] = 3857,
+	[BNXT_ULP_CLASS_HID_3a44] = 3858,
+	[BNXT_ULP_CLASS_HID_5ed8] = 3859,
+	[BNXT_ULP_CLASS_HID_07e0] = 3860,
+	[BNXT_ULP_CLASS_HID_2874] = 3861,
+	[BNXT_ULP_CLASS_HID_591c] = 3862,
+	[BNXT_ULP_CLASS_HID_1e24] = 3863,
+	[BNXT_ULP_CLASS_HID_22b8] = 3864
 };
 
 /* Array for the proto matcher list */
 struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	[1] = {
-	.class_hid = BNXT_ULP_CLASS_HID_005c,
+	.class_hid = BNXT_ULP_CLASS_HID_26d1,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 0,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[2] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0003,
+	.class_hid = BNXT_ULP_CLASS_HID_0071,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 1,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[3] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0132,
+	.class_hid = BNXT_ULP_CLASS_HID_53a5,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
 	.flow_sig_id = 1,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[4] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00e1,
+	.class_hid = BNXT_ULP_CLASS_HID_1d49,
 	.class_tid = 1,
 	.hdr_sig_id = 0,
-	.flow_sig_id = 1,
+	.flow_sig_id = 2,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[5] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0044,
+	.class_hid = BNXT_ULP_CLASS_HID_2095,
 	.class_tid = 1,
-	.hdr_sig_id = 1,
-	.flow_sig_id = 1,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 2,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[6] = {
-	.class_hid = BNXT_ULP_CLASS_HID_001b,
+	.class_hid = BNXT_ULP_CLASS_HID_5701,
 	.class_tid = 1,
-	.hdr_sig_id = 1,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 2,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[7] = {
-	.class_hid = BNXT_ULP_CLASS_HID_012a,
+	.class_hid = BNXT_ULP_CLASS_HID_4d79,
 	.class_tid = 1,
-	.hdr_sig_id = 1,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 2,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[8] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00f9,
+	.class_hid = BNXT_ULP_CLASS_HID_170d,
 	.class_tid = 1,
-	.hdr_sig_id = 1,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 2,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[9] = {
-	.class_hid = BNXT_ULP_CLASS_HID_018d,
+	.class_hid = BNXT_ULP_CLASS_HID_1a69,
 	.class_tid = 1,
-	.hdr_sig_id = 2,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 2,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[10] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00a7,
+	.class_hid = BNXT_ULP_CLASS_HID_50c5,
 	.class_tid = 1,
-	.hdr_sig_id = 2,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 3,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[11] = {
-	.class_hid = BNXT_ULP_CLASS_HID_006f,
+	.class_hid = BNXT_ULP_CLASS_HID_473d,
 	.class_tid = 1,
-	.hdr_sig_id = 2,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 3,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[12] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0181,
+	.class_hid = BNXT_ULP_CLASS_HID_10c1,
 	.class_tid = 1,
-	.hdr_sig_id = 2,
-	.flow_sig_id = 3,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 4,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[13] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0195,
+	.class_hid = BNXT_ULP_CLASS_HID_142d,
 	.class_tid = 1,
-	.hdr_sig_id = 3,
-	.flow_sig_id = 3,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 4,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[14] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00bf,
+	.class_hid = BNXT_ULP_CLASS_HID_4a99,
 	.class_tid = 1,
-	.hdr_sig_id = 3,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 4,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[15] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0077,
+	.class_hid = BNXT_ULP_CLASS_HID_40f1,
 	.class_tid = 1,
-	.hdr_sig_id = 3,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 4,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[16] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0199,
+	.class_hid = BNXT_ULP_CLASS_HID_0a85,
 	.class_tid = 1,
-	.hdr_sig_id = 3,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 4,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[17] = {
-	.class_hid = BNXT_ULP_CLASS_HID_009a,
+	.class_hid = BNXT_ULP_CLASS_HID_0179,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
+	.hdr_sig_id = 0,
 	.flow_sig_id = 4,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[18] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0192,
+	.class_hid = BNXT_ULP_CLASS_HID_37d5,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 4,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 5,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[19] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01e2,
+	.class_hid = BNXT_ULP_CLASS_HID_2e4d,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 4,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 5,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[20] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00fa,
+	.class_hid = BNXT_ULP_CLASS_HID_54ad,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 4,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 6,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[21] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0165,
+	.class_hid = BNXT_ULP_CLASS_HID_5809,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 4,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 6,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[22] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0042,
+	.class_hid = BNXT_ULP_CLASS_HID_31a9,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 6,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[23] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00cd,
+	.class_hid = BNXT_ULP_CLASS_HID_2801,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 6,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[24] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01aa,
+	.class_hid = BNXT_ULP_CLASS_HID_4e61,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 6,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[25] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0178,
+	.class_hid = BNXT_ULP_CLASS_HID_2561,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 6,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[26] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0070,
+	.class_hid = BNXT_ULP_CLASS_HID_2bad,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 7,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[27] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00f3,
+	.class_hid = BNXT_ULP_CLASS_HID_26f1,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 7,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[28] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01d8,
+	.class_hid = BNXT_ULP_CLASS_HID_13cf1,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 7,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[29] = {
-	.class_hid = BNXT_ULP_CLASS_HID_005b,
+	.class_hid = BNXT_ULP_CLASS_HID_252f1,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 8,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[30] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0153,
+	.class_hid = BNXT_ULP_CLASS_HID_30c25,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 9,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[31] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01a3,
+	.class_hid = BNXT_ULP_CLASS_HID_0051,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 10,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[32] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00bb,
+	.class_hid = BNXT_ULP_CLASS_HID_11651,
 	.class_tid = 1,
-	.hdr_sig_id = 4,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 10,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[33] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0082,
+	.class_hid = BNXT_ULP_CLASS_HID_22c51,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 10,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[34] = {
-	.class_hid = BNXT_ULP_CLASS_HID_018a,
+	.class_hid = BNXT_ULP_CLASS_HID_34251,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 10,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[35] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01fa,
+	.class_hid = BNXT_ULP_CLASS_HID_5385,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 10,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[36] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00e2,
+	.class_hid = BNXT_ULP_CLASS_HID_10cc9,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 10,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[37] = {
-	.class_hid = BNXT_ULP_CLASS_HID_017d,
+	.class_hid = BNXT_ULP_CLASS_HID_222c9,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 5,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 11,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[38] = {
-	.class_hid = BNXT_ULP_CLASS_HID_005a,
+	.class_hid = BNXT_ULP_CLASS_HID_338c9,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 12,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[39] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00d5,
+	.class_hid = BNXT_ULP_CLASS_HID_1d69,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[40] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01b2,
+	.class_hid = BNXT_ULP_CLASS_HID_13369,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[41] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0160,
+	.class_hid = BNXT_ULP_CLASS_HID_24969,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[42] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0068,
+	.class_hid = BNXT_ULP_CLASS_HID_3025d,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[43] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00eb,
+	.class_hid = BNXT_ULP_CLASS_HID_20b5,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[44] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01c0,
+	.class_hid = BNXT_ULP_CLASS_HID_136b5,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[45] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0043,
+	.class_hid = BNXT_ULP_CLASS_HID_24cb5,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[46] = {
-	.class_hid = BNXT_ULP_CLASS_HID_014b,
+	.class_hid = BNXT_ULP_CLASS_HID_305f9,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[47] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01bb,
+	.class_hid = BNXT_ULP_CLASS_HID_5721,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[48] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00a3,
+	.class_hid = BNXT_ULP_CLASS_HID_11015,
 	.class_tid = 1,
-	.hdr_sig_id = 5,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[49] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00cb,
+	.class_hid = BNXT_ULP_CLASS_HID_22615,
 	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
 	[50] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00b4,
+	.class_hid = BNXT_ULP_CLASS_HID_33c15,
 	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 6,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[51] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4d59,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[52] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1068d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[53] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21c8d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[54] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3328d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[55] = {
+	.class_hid = BNXT_ULP_CLASS_HID_172d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[56] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12d2d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[57] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2432d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[58] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3592d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[59] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a49,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[60] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13049,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 13,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[61] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24649,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 14,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[62] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35c49,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 15,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[63] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50e5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 16,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[64] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10a29,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 16,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[65] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22029,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 16,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[66] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33629,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 16,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[67] = {
+	.class_hid = BNXT_ULP_CLASS_HID_471d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 16,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[68] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10041,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 16,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[69] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21641,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 17,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[70] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32c41,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 18,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[71] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10e1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[72] = {
+	.class_hid = BNXT_ULP_CLASS_HID_126e1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[73] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ce1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[74] = {
+	.class_hid = BNXT_ULP_CLASS_HID_352e1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[75] = {
+	.class_hid = BNXT_ULP_CLASS_HID_140d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[76] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12a0d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[77] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2400d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[78] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3560d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[79] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4ab9,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[80] = {
+	.class_hid = BNXT_ULP_CLASS_HID_103ed,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[81] = {
+	.class_hid = BNXT_ULP_CLASS_HID_219ed,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[82] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32fed,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[83] = {
+	.class_hid = BNXT_ULP_CLASS_HID_40d1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[84] = {
+	.class_hid = BNXT_ULP_CLASS_HID_156d1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[85] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21005,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[86] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32605,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[87] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0aa5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[88] = {
+	.class_hid = BNXT_ULP_CLASS_HID_120a5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[89] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236a5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[90] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34ca5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[91] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0159,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[92] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11759,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 19,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[93] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22d59,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 20,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[94] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34359,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 21,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[95] = {
+	.class_hid = BNXT_ULP_CLASS_HID_37f5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 22,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[96] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14df5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 22,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[97] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20739,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 22,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[98] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31d39,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 22,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[99] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2e6d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 22,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[100] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1446d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 22,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[101] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25a6d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 23,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[102] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31351,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 24,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[103] = {
+	.class_hid = BNXT_ULP_CLASS_HID_548d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[104] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10df1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[105] = {
+	.class_hid = BNXT_ULP_CLASS_HID_223f1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[106] = {
+	.class_hid = BNXT_ULP_CLASS_HID_339f1,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[107] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5829,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[108] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1111d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[109] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2271d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[110] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33d1d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[111] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3189,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[112] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14789,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[113] = {
+	.class_hid = BNXT_ULP_CLASS_HID_200fd,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[114] = {
+	.class_hid = BNXT_ULP_CLASS_HID_316fd,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[115] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2821,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[116] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13e21,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[117] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25421,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[118] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30d15,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[119] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4e41,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[120] = {
+	.class_hid = BNXT_ULP_CLASS_HID_107b5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[121] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21db5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[122] = {
+	.class_hid = BNXT_ULP_CLASS_HID_333b5,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[123] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2541,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[124] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b8d,
+	.class_tid = 1,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[125] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2691,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[126] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13c91,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 25,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[127] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25291,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 26,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[128] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30c45,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 27,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[129] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0031,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 28,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[130] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11631,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 28,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[131] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c31,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 28,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[132] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34231,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 28,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[133] = {
+	.class_hid = BNXT_ULP_CLASS_HID_53e5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 28,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[134] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10ca9,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 28,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[135] = {
+	.class_hid = BNXT_ULP_CLASS_HID_222a9,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 29,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[136] = {
+	.class_hid = BNXT_ULP_CLASS_HID_338a9,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 30,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[137] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d09,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[138] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13309,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[139] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24909,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[140] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3023d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[141] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20d5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[142] = {
+	.class_hid = BNXT_ULP_CLASS_HID_136d5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[143] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24cd5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[144] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30599,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[145] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5741,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[146] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11075,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[147] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22675,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[148] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33c75,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[149] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4d39,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[150] = {
+	.class_hid = BNXT_ULP_CLASS_HID_106ed,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[151] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21ced,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[152] = {
+	.class_hid = BNXT_ULP_CLASS_HID_332ed,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[153] = {
+	.class_hid = BNXT_ULP_CLASS_HID_174d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[154] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12d4d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[155] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2434d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[156] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3594d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[157] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a29,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[158] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13029,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 31,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[159] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24629,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 32,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[160] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35c29,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 33,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[161] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5085,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 34,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[162] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10a49,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 34,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[163] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22049,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 34,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[164] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33649,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 34,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[165] = {
+	.class_hid = BNXT_ULP_CLASS_HID_477d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 34,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[166] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10021,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 34,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[167] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21621,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 35,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[168] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32c21,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 36,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[169] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1081,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[170] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12681,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[171] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23c81,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[172] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35281,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[173] = {
+	.class_hid = BNXT_ULP_CLASS_HID_146d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[174] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12a6d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[175] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2406d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[176] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3566d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[177] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4ad9,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[178] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1038d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[179] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2198d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[180] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32f8d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[181] = {
+	.class_hid = BNXT_ULP_CLASS_HID_40b1,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[182] = {
+	.class_hid = BNXT_ULP_CLASS_HID_156b1,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[183] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21065,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[184] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32665,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[185] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0ac5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[186] = {
+	.class_hid = BNXT_ULP_CLASS_HID_120c5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[187] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236c5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[188] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34cc5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[189] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0139,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[190] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11739,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 37,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[191] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22d39,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 38,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[192] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34339,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 39,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[193] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3795,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 40,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[194] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14d95,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 40,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[195] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20759,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 40,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[196] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31d59,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 40,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[197] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2e0d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 40,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[198] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1440d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 40,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[199] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25a0d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 41,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[200] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31331,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 42,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[201] = {
+	.class_hid = BNXT_ULP_CLASS_HID_54ed,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[202] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10d91,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[203] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22391,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[204] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33991,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[205] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5849,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[206] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1117d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[207] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2277d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[208] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33d7d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[209] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31e9,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[210] = {
+	.class_hid = BNXT_ULP_CLASS_HID_147e9,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[211] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2009d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[212] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3169d,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[213] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2841,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[214] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13e41,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[215] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25441,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[216] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30d75,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[217] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4e21,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[218] = {
+	.class_hid = BNXT_ULP_CLASS_HID_107d5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[219] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21dd5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[220] = {
+	.class_hid = BNXT_ULP_CLASS_HID_333d5,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[221] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2521,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[222] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bed,
+	.class_tid = 1,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[223] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1865,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 43,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[224] = {
+	.class_hid = BNXT_ULP_CLASS_HID_389d,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 44,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[225] = {
+	.class_hid = BNXT_ULP_CLASS_HID_123d,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 44,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[226] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4ef1,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 45,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[227] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1229,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 45,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[228] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3241,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 45,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[229] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0be1,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 45,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[230] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48b5,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 45,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[231] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0bed,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 45,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[232] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c05,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 46,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[233] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05a5,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 46,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[234] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4279,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 47,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[235] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05d1,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 47,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[236] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25c9,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 47,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[237] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5c55,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 47,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[238] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c3d,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 47,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[239] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4fc9,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 47,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[240] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1335,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 48,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[241] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4981,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 48,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[242] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2969,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[243] = {
+	.class_hid = BNXT_ULP_CLASS_HID_498d,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[244] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0cf9,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[245] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4345,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[246] = {
+	.class_hid = BNXT_ULP_CLASS_HID_232d,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[247] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2579,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[248] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bb5,
+	.class_tid = 1,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[249] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1845,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[250] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1399,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 49,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[251] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0eed,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 50,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[252] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0a21,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 51,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[253] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38bd,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 52,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[254] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33f1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 52,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[255] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ec5,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 52,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[256] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a19,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 52,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[257] = {
+	.class_hid = BNXT_ULP_CLASS_HID_121d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 52,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[258] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0d51,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 52,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[259] = {
+	.class_hid = BNXT_ULP_CLASS_HID_08a5,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 53,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[260] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03f9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 54,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[261] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4ed1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[262] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4a25,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[263] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4579,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[264] = {
+	.class_hid = BNXT_ULP_CLASS_HID_404d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[265] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1209,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[266] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0d5d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[267] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0891,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[268] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03e5,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[269] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3261,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[270] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2db5,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[271] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2889,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[272] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23dd,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[273] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0bc1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[274] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0715,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[275] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0269,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[276] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5a69,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[277] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4895,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[278] = {
+	.class_hid = BNXT_ULP_CLASS_HID_43e9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[279] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3f3d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[280] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a71,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[281] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0bcd,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[282] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0701,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 55,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[283] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0255,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 56,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[284] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5a55,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 57,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[285] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c25,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 58,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[286] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2779,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 58,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[287] = {
+	.class_hid = BNXT_ULP_CLASS_HID_224d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 58,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[288] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d81,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 58,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[289] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0585,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 58,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[290] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00d9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 58,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[291] = {
+	.class_hid = BNXT_ULP_CLASS_HID_58d9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 59,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[292] = {
+	.class_hid = BNXT_ULP_CLASS_HID_542d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 60,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[293] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4259,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[294] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dad,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[295] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38e1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[296] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3435,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[297] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05f1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[298] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00c5,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[299] = {
+	.class_hid = BNXT_ULP_CLASS_HID_58c5,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[300] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5419,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[301] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25e9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[302] = {
+	.class_hid = BNXT_ULP_CLASS_HID_213d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[303] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c71,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[304] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1745,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[305] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5c75,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[306] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5749,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[307] = {
+	.class_hid = BNXT_ULP_CLASS_HID_529d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[308] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4dd1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[309] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c1d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[310] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3751,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[311] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32a5,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[312] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2df9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[313] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4fe9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[314] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4b3d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 61,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[315] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4671,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 62,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[316] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4145,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 63,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[317] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1315,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 64,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[318] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0e69,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 64,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[319] = {
+	.class_hid = BNXT_ULP_CLASS_HID_09bd,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 64,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[320] = {
+	.class_hid = BNXT_ULP_CLASS_HID_04f1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 64,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[321] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49a1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 64,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[322] = {
+	.class_hid = BNXT_ULP_CLASS_HID_44f5,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 64,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[323] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3fc9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 65,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[324] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b1d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 66,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[325] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2949,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[326] = {
+	.class_hid = BNXT_ULP_CLASS_HID_249d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[327] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fd1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[328] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b25,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[329] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49ad,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[330] = {
+	.class_hid = BNXT_ULP_CLASS_HID_44e1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[331] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4035,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[332] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b09,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[333] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0cd9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[334] = {
+	.class_hid = BNXT_ULP_CLASS_HID_082d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[335] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0361,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[336] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5b61,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[337] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4365,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[338] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3eb9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[339] = {
+	.class_hid = BNXT_ULP_CLASS_HID_398d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[340] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34c1,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[341] = {
+	.class_hid = BNXT_ULP_CLASS_HID_230d,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[342] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e41,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[343] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1995,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[344] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14e9,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[345] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2559,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[346] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b95,
+	.class_tid = 1,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[347] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1825,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[348] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13f9,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 67,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[349] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0e8d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 68,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[350] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0a41,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 69,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[351] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38dd,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 70,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[352] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3391,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 70,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[353] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ea5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 70,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[354] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a79,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 70,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[355] = {
+	.class_hid = BNXT_ULP_CLASS_HID_127d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 70,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[356] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0d31,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 70,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[357] = {
+	.class_hid = BNXT_ULP_CLASS_HID_08c5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 71,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[358] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0399,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 72,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[359] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4eb1,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[360] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4a45,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[361] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4519,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[362] = {
+	.class_hid = BNXT_ULP_CLASS_HID_402d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[363] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1269,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[364] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0d3d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[365] = {
+	.class_hid = BNXT_ULP_CLASS_HID_08f1,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[366] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0385,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[367] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3201,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[368] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dd5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[369] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28e9,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[370] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23bd,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[371] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0ba1,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[372] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0775,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[373] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0209,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[374] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5a09,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[375] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48f5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[376] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4389,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[377] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3f5d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[378] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a11,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[379] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0bad,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[380] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0761,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 73,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[381] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0235,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 74,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[382] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5a35,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 75,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[383] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c45,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 76,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[384] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2719,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 76,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[385] = {
+	.class_hid = BNXT_ULP_CLASS_HID_222d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 76,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[386] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1de1,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 76,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[387] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05e5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 76,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[388] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00b9,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 76,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[389] = {
+	.class_hid = BNXT_ULP_CLASS_HID_58b9,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 77,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[390] = {
+	.class_hid = BNXT_ULP_CLASS_HID_544d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 78,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[391] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4239,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[392] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dcd,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[393] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3881,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[394] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3455,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[395] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0591,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[396] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00a5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[397] = {
+	.class_hid = BNXT_ULP_CLASS_HID_58a5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[398] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5479,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[399] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2589,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[400] = {
+	.class_hid = BNXT_ULP_CLASS_HID_215d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[401] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c11,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[402] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1725,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[403] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5c15,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[404] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5729,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[405] = {
+	.class_hid = BNXT_ULP_CLASS_HID_52fd,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[406] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4db1,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[407] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c7d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[408] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3731,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[409] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32c5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[410] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d99,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[411] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4f89,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[412] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4b5d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 79,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[413] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4611,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 80,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[414] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4125,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 81,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[415] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1375,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 82,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[416] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0e09,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 82,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[417] = {
+	.class_hid = BNXT_ULP_CLASS_HID_09dd,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 82,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[418] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0491,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 82,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[419] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49c1,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 82,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[420] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4495,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 82,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[421] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3fa9,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 83,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[422] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b7d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 84,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[423] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2929,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[424] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24fd,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[425] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fb1,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[426] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b45,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[427] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49cd,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[428] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4481,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[429] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4055,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[430] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b69,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[431] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0cb9,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[432] = {
+	.class_hid = BNXT_ULP_CLASS_HID_084d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[433] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0301,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[434] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5b01,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[435] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4305,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[436] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ed9,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[437] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39ed,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[438] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34a1,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[439] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236d,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[440] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e21,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[441] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19f5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[442] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1489,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[443] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2539,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[444] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bf5,
+	.class_tid = 1,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[445] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b6af,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[446] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b1d3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[447] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c7d3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[448] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ccaf,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[449] = {
+	.class_hid = BNXT_ULP_CLASS_HID_da33,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[450] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d567,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[451] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18eab,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[452] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19367,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[453] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a10b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 85,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[454] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9c3f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 86,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[455] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b23f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 86,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[456] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b70b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[457] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c49f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[458] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bfc3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[459] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d5c3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[460] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1da9f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[461] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b063,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[462] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ab97,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[463] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c197,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[464] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c663,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[465] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d3f7,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[466] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cf3b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[467] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1886f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[468] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18d3b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[469] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9acf,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[470] = {
+	.class_hid = BNXT_ULP_CLASS_HID_95f3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[471] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1abf3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[472] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b0cf,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[473] = {
+	.class_hid = BNXT_ULP_CLASS_HID_be53,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[474] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b987,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[475] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cf87,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[476] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d453,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[477] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aa27,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[478] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a56b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[479] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bb6b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[480] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c027,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[481] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cdcb,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[482] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c8ff,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[483] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18223,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[484] = {
+	.class_hid = BNXT_ULP_CLASS_HID_186ff,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[485] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9483,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 87,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[486] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8fb7,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 88,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[487] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a5b7,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 88,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[488] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1aa83,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[489] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b817,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[490] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b35b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[491] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c95b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[492] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ce17,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[493] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a3fb,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[494] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9f2f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[495] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b52f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[496] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b9fb,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[497] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c78f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[498] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c2b3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[499] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d8b3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[500] = {
+	.class_hid = BNXT_ULP_CLASS_HID_180b3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[501] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8e47,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[502] = {
+	.class_hid = BNXT_ULP_CLASS_HID_898b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[503] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19f8b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[504] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a447,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[505] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b1eb,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[506] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ad1f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[507] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c31f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[508] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c7eb,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[509] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9137,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[510] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8c7b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[511] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a27b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[512] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a737,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[513] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b4db,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[514] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b00f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[515] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c60f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[516] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cadb,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[517] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8b0b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[518] = {
+	.class_hid = BNXT_ULP_CLASS_HID_863f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[519] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19c3f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[520] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a10b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[521] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ae9f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[522] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a9c3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[523] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bfc3,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[524] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c49f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[525] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2563,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[526] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2baf,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[527] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4f33,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[528] = {
+	.class_hid = BNXT_ULP_CLASS_HID_160b,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 89,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[529] = {
+	.class_hid = BNXT_ULP_CLASS_HID_399f,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[530] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48f7,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[531] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0fcf,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[532] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3353,
+	.class_tid = 1,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[533] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b68f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[534] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b94f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[535] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fc0f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[536] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fecf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[537] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b1f3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[538] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b4b3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[539] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f773,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[540] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fa33,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[541] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c7f3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[542] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eab3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[543] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cd73,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[544] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f033,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[545] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cc8f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[546] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ef4f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[547] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d20f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[548] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f4cf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[549] = {
+	.class_hid = BNXT_ULP_CLASS_HID_da13,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[550] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a007,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[551] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c2c7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[552] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e587,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[553] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d547,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[554] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f807,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[555] = {
+	.class_hid = BNXT_ULP_CLASS_HID_dac7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[556] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e0cb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[557] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18e8b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[558] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b14b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[559] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d40b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[560] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f6cb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[561] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19347,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[562] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b607,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[563] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d8c7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[564] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fb87,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[565] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a12b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[566] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a3eb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 90,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[567] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e6ab,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 91,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[568] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e96b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 92,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[569] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9c1f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 93,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[570] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bedf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 93,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[571] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e19f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 93,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[572] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e45f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 93,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[573] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b21f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 93,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[574] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b4df,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 93,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[575] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f79f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 94,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[576] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fa5f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 95,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[577] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b72b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[578] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b9eb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[579] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fcab,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[580] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ff6b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[581] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c4bf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[582] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e77f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[583] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ca3f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[584] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ecff,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[585] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bfe3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[586] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e2a3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[587] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c563,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[588] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e823,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[589] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d5e3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[590] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f8a3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[591] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1db63,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[592] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e117,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[593] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dabf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[594] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a0a3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[595] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c363,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[596] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e623,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[597] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b043,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[598] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b303,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[599] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f5c3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[600] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f883,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[601] = {
+	.class_hid = BNXT_ULP_CLASS_HID_abb7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[602] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ae77,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[603] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f137,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[604] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f3f7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[605] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c1b7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[606] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e477,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[607] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c737,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[608] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e9f7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[609] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c643,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[610] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e903,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[611] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cbc3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[612] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ee83,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[613] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d3d7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[614] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f697,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[615] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d957,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[616] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fc17,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[617] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cf1b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[618] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f1db,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[619] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d49b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[620] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f75b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[621] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1884f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[622] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ab0f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[623] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cdcf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[624] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f08f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[625] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18d1b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[626] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1afdb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[627] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d29b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[628] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f55b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[629] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9aef,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[630] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bdaf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[631] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e06f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[632] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e32f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[633] = {
+	.class_hid = BNXT_ULP_CLASS_HID_95d3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[634] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b893,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[635] = {
+	.class_hid = BNXT_ULP_CLASS_HID_db53,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[636] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fe13,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[637] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1abd3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[638] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ae93,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[639] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f153,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[640] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f413,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[641] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b0ef,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[642] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b3af,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[643] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f66f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[644] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f92f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[645] = {
+	.class_hid = BNXT_ULP_CLASS_HID_be73,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[646] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e133,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[647] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c3f3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[648] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e6b3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[649] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b9a7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[650] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bc67,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[651] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ff27,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[652] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e1e7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[653] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cfa7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[654] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f267,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[655] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d527,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[656] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f7e7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[657] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d473,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[658] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f733,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[659] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d9f3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[660] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fcb3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[661] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aa07,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[662] = {
+	.class_hid = BNXT_ULP_CLASS_HID_acc7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[663] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef87,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[664] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f247,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[665] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a54b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[666] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a80b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[667] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eacb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[668] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ed8b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[669] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bb4b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[670] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1be0b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[671] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c0cb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[672] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e38b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[673] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c007,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[674] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e2c7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[675] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c587,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[676] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e847,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[677] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cdeb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[678] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f0ab,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[679] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d36b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[680] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f62b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[681] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c8df,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[682] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eb9f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[683] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ce5f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[684] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f11f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[685] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18203,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[686] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a4c3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[687] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c783,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[688] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea43,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[689] = {
+	.class_hid = BNXT_ULP_CLASS_HID_186df,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[690] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a99f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[691] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cc5f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[692] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ef1f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[693] = {
+	.class_hid = BNXT_ULP_CLASS_HID_94a3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[694] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b763,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 96,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[695] = {
+	.class_hid = BNXT_ULP_CLASS_HID_da23,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 97,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[696] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fce3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 98,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[697] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8f97,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 99,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[698] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b257,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 99,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[699] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d517,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 99,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[700] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f7d7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 99,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[701] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a597,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 99,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[702] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a857,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 99,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[703] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eb17,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 100,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[704] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1edd7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 101,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[705] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1aaa3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[706] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ad63,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[707] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f023,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[708] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f2e3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[709] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b837,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[710] = {
+	.class_hid = BNXT_ULP_CLASS_HID_baf7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[711] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fdb7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[712] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e077,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[713] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b37b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[714] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b63b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[715] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f8fb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[716] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fbbb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[717] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c97b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[718] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ec3b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[719] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cefb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[720] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f1bb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[721] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ce37,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[722] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f0f7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[723] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d3b7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[724] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f677,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[725] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a3db,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[726] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a69b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[727] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e95b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[728] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ec1b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[729] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9f0f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[730] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a1cf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[731] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e48f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[732] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e74f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[733] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b50f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[734] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b7cf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[735] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fa8f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[736] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fd4f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[737] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b9db,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[738] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bc9b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[739] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ff5b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[740] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e21b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[741] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c7af,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[742] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ea6f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[743] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cd2f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[744] = {
+	.class_hid = BNXT_ULP_CLASS_HID_efef,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[745] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c293,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[746] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e553,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[747] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c813,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[748] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ead3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[749] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d893,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[750] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fb53,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[751] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c147,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[752] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e407,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[753] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18093,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[754] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a353,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[755] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c613,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[756] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e8d3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[757] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8e67,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[758] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b127,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[759] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d3e7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[760] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f6a7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[761] = {
+	.class_hid = BNXT_ULP_CLASS_HID_89ab,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[762] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ac6b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[763] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cf2b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[764] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f1eb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[765] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19fab,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[766] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a26b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[767] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e52b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[768] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e7eb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[769] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a467,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[770] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a727,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[771] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e9e7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[772] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eca7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[773] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b1cb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[774] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b48b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[775] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f74b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[776] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fa0b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[777] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ad3f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[778] = {
+	.class_hid = BNXT_ULP_CLASS_HID_afff,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[779] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f2bf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[780] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f57f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[781] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c33f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[782] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e5ff,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[783] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c8bf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[784] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eb7f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[785] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c7cb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[786] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea8b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[787] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cd4b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[788] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f00b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[789] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9117,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[790] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b3d7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[791] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d697,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[792] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f957,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[793] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8c5b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[794] = {
+	.class_hid = BNXT_ULP_CLASS_HID_af1b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[795] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d1db,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[796] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f49b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[797] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a25b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[798] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a51b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[799] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e7db,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[800] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea9b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[801] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a717,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[802] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a9d7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[803] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ec97,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[804] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ef57,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[805] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b4fb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[806] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b7bb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[807] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fa7b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[808] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fd3b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[809] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b02f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[810] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b2ef,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[811] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f5af,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[812] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f86f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[813] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c62f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[814] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e8ef,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[815] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cbaf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[816] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ee6f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[817] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cafb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[818] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1edbb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[819] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d07b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[820] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f33b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[821] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8b2b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[822] = {
+	.class_hid = BNXT_ULP_CLASS_HID_adeb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[823] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d0ab,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[824] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f36b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[825] = {
+	.class_hid = BNXT_ULP_CLASS_HID_861f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[826] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a8df,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[827] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cb9f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[828] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ee5f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[829] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19c1f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[830] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bedf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[831] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e19f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[832] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e45f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[833] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a12b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[834] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a3eb,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[835] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e6ab,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[836] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e96b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[837] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aebf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[838] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b17f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[839] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f43f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[840] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f6ff,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[841] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a9e3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[842] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aca3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[843] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef63,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[844] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f223,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[845] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bfe3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[846] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e2a3,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[847] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c563,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[848] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e823,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[849] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c4bf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[850] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e77f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[851] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ca3f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[852] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ecff,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[853] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2543,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[854] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b8f,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[855] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4f13,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[856] = {
+	.class_hid = BNXT_ULP_CLASS_HID_162b,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[857] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39bf,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[858] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48d7,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[859] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0fef,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[860] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3373,
+	.class_tid = 1,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[861] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b6ef,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[862] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b92f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[863] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fc6f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[864] = {
+	.class_hid = BNXT_ULP_CLASS_HID_feaf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[865] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b193,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[866] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b4d3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[867] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f713,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[868] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fa53,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[869] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c793,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[870] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ead3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[871] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cd13,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[872] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f053,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[873] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ccef,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[874] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ef2f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[875] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d26f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[876] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f4af,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[877] = {
+	.class_hid = BNXT_ULP_CLASS_HID_da73,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[878] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a067,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[879] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c2a7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[880] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e5e7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[881] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d527,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[882] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f867,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[883] = {
+	.class_hid = BNXT_ULP_CLASS_HID_daa7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[884] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e0ab,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[885] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18eeb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[886] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b12b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[887] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d46b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[888] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f6ab,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[889] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19327,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[890] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b667,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[891] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d8a7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[892] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fbe7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[893] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a14b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[894] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a38b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 102,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[895] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e6cb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 103,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[896] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e90b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 104,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[897] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9c7f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 105,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[898] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bebf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 105,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[899] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e1ff,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 105,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[900] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e43f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 105,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[901] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b27f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 105,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[902] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b4bf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 105,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[903] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f7ff,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 106,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[904] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fa3f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 107,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[905] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b74b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[906] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b98b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[907] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fccb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[908] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ff0b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[909] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c4df,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[910] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e71f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[911] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ca5f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[912] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ec9f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[913] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bf83,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[914] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e2c3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[915] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c503,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[916] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e843,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[917] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d583,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[918] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f8c3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[919] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1db03,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[920] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e177,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[921] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dadf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[922] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a0c3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[923] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c303,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[924] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e643,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[925] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b023,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[926] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b363,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[927] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f5a3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[928] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f8e3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[929] = {
+	.class_hid = BNXT_ULP_CLASS_HID_abd7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[930] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ae17,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[931] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f157,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[932] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f397,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[933] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c1d7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[934] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e417,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[935] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c757,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[936] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e997,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[937] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c623,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[938] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e963,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[939] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cba3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[940] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eee3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[941] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d3b7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[942] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f6f7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[943] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d937,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[944] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fc77,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[945] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cf7b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[946] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f1bb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[947] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d4fb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[948] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f73b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[949] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1882f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[950] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ab6f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[951] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cdaf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[952] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f0ef,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[953] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18d7b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[954] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1afbb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[955] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d2fb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[956] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f53b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[957] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9a8f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[958] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bdcf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[959] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e00f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[960] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e34f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[961] = {
+	.class_hid = BNXT_ULP_CLASS_HID_95b3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[962] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b8f3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[963] = {
+	.class_hid = BNXT_ULP_CLASS_HID_db33,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[964] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fe73,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[965] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1abb3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[966] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1aef3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[967] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f133,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[968] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f473,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[969] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b08f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[970] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b3cf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[971] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f60f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[972] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f94f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[973] = {
+	.class_hid = BNXT_ULP_CLASS_HID_be13,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[974] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e153,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[975] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c393,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[976] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e6d3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[977] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b9c7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[978] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bc07,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[979] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ff47,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[980] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e187,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[981] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cfc7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[982] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f207,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[983] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d547,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[984] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f787,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[985] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d413,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[986] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f753,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[987] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d993,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[988] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fcd3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[989] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aa67,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[990] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aca7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[991] = {
+	.class_hid = BNXT_ULP_CLASS_HID_efe7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[992] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f227,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[993] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a52b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[994] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a86b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[995] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eaab,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[996] = {
+	.class_hid = BNXT_ULP_CLASS_HID_edeb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[997] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bb2b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[998] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1be6b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[999] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c0ab,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1000] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e3eb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1001] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c067,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1002] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e2a7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1003] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c5e7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1004] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e827,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1005] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cd8b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1006] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f0cb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1007] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d30b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1008] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f64b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1009] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c8bf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1010] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ebff,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1011] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ce3f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1012] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f17f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1013] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18263,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1014] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a4a3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1015] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c7e3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1016] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea23,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1017] = {
+	.class_hid = BNXT_ULP_CLASS_HID_186bf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1018] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a9ff,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1019] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cc3f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1020] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ef7f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1021] = {
+	.class_hid = BNXT_ULP_CLASS_HID_94c3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1022] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b703,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 108,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1023] = {
+	.class_hid = BNXT_ULP_CLASS_HID_da43,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 109,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1024] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fc83,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 110,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1025] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8ff7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 111,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1026] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b237,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 111,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1027] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d577,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 111,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1028] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f7b7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 111,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1029] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a5f7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 111,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1030] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a837,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 111,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1031] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eb77,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 112,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1032] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1edb7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 113,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1033] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1aac3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1034] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ad03,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1035] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f043,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1036] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f283,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1037] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b857,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1038] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ba97,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1039] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fdd7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1040] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e017,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1041] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b31b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1042] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b65b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1043] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f89b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1044] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fbdb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1045] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c91b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1046] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ec5b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1047] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ce9b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1048] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f1db,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1049] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ce57,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1050] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f097,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1051] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d3d7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1052] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f617,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1053] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a3bb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1054] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a6fb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1055] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e93b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1056] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ec7b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1057] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9f6f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1058] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a1af,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1059] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e4ef,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1060] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e72f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1061] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b56f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1062] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b7af,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1063] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1faef,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1064] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fd2f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1065] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b9bb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1066] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bcfb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1067] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ff3b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1068] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e27b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1069] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c7cf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1070] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ea0f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1071] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cd4f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1072] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef8f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1073] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c2f3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1074] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e533,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1075] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c873,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1076] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eab3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1077] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d8f3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1078] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fb33,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1079] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c127,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1080] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e467,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1081] = {
+	.class_hid = BNXT_ULP_CLASS_HID_180f3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1082] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a333,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1083] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c673,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1084] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e8b3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1085] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8e07,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1086] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b147,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1087] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d387,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1088] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f6c7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1089] = {
+	.class_hid = BNXT_ULP_CLASS_HID_89cb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1090] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ac0b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1091] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cf4b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1092] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f18b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1093] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19fcb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1094] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a20b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1095] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e54b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1096] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e78b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1097] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a407,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1098] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a747,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1099] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e987,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1100] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ecc7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1101] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b1ab,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1102] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b4eb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1103] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f72b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1104] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fa6b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1105] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ad5f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1106] = {
+	.class_hid = BNXT_ULP_CLASS_HID_af9f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1107] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f2df,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1108] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f51f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1109] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c35f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1110] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e59f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1111] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c8df,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1112] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eb1f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1113] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c7ab,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1114] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eaeb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1115] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cd2b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1116] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f06b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1117] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9177,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1118] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b3b7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1119] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d6f7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1120] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f937,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1121] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8c3b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1122] = {
+	.class_hid = BNXT_ULP_CLASS_HID_af7b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1123] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d1bb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1124] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f4fb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1125] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a23b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1126] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a57b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1127] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e7bb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1128] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eafb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1129] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a777,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1130] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a9b7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1131] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ecf7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1132] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ef37,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1133] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b49b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1134] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b7db,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1135] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fa1b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1136] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fd5b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1137] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b04f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1138] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b28f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1139] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f5cf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1140] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f80f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1141] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c64f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1142] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e88f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1143] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cbcf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1144] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ee0f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1145] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ca9b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1146] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eddb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1147] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d01b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1148] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f35b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1149] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8b4b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1150] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ad8b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1151] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d0cb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1152] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f30b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1153] = {
+	.class_hid = BNXT_ULP_CLASS_HID_867f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1154] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a8bf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1155] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cbff,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1156] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ee3f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1157] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19c7f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1158] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bebf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1159] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e1ff,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1160] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e43f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1161] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a14b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1162] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a38b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1163] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e6cb,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1164] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e90b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1165] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aedf,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1166] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b11f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1167] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f45f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1168] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f69f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1169] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a983,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1170] = {
+	.class_hid = BNXT_ULP_CLASS_HID_acc3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1171] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef03,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1172] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f243,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1173] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bf83,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1174] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e2c3,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1175] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c503,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1176] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e843,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1177] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c4df,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1178] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e71f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1179] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ca5f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1180] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ec9f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1181] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2523,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1182] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bef,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1183] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4f73,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1184] = {
+	.class_hid = BNXT_ULP_CLASS_HID_164b,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1185] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39df,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1186] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48b7,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1187] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0f8f,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1188] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3313,
+	.class_tid = 1,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1189] = {
+	.class_hid = BNXT_ULP_CLASS_HID_257b7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1190] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24467,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1191] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23fbb,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1192] = {
+	.class_hid = BNXT_ULP_CLASS_HID_252cb,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1193] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21e7f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1194] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20b2f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1195] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20663,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1196] = {
+	.class_hid = BNXT_ULP_CLASS_HID_219b3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1197] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24213,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 114,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1198] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22ec3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 115,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1199] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22a17,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 115,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1200] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23d27,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1201] = {
+	.class_hid = BNXT_ULP_CLASS_HID_208db,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1202] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25277,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1203] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24d8b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1204] = {
+	.class_hid = BNXT_ULP_CLASS_HID_203ef,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1205] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2517b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1206] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23e2b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1207] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2397f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1208] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24c8f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1209] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21823,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1210] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20513,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1211] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20027,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1212] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21377,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1213] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23bd7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1214] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22887,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1215] = {
+	.class_hid = BNXT_ULP_CLASS_HID_223db,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1216] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236eb,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1217] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2029f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1218] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24c3b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1219] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2474f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1220] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25a9f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1221] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24b3f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1222] = {
+	.class_hid = BNXT_ULP_CLASS_HID_237ef,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1223] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23323,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1224] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24673,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1225] = {
+	.class_hid = BNXT_ULP_CLASS_HID_211e7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1226] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25b83,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1227] = {
+	.class_hid = BNXT_ULP_CLASS_HID_256d7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1228] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20d3b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1229] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2359b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 116,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1230] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2224b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 117,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1231] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21d9f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 117,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1232] = {
+	.class_hid = BNXT_ULP_CLASS_HID_230af,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1233] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2590f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1234] = {
+	.class_hid = BNXT_ULP_CLASS_HID_245ff,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1235] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24133,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1236] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25443,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1237] = {
+	.class_hid = BNXT_ULP_CLASS_HID_244e3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1238] = {
+	.class_hid = BNXT_ULP_CLASS_HID_231d3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1239] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22ce7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1240] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24037,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1241] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20bab,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1242] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25547,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1243] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2509b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1244] = {
+	.class_hid = BNXT_ULP_CLASS_HID_206ff,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1245] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22f5f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1246] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21c0f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1247] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21743,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1248] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22a93,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1249] = {
+	.class_hid = BNXT_ULP_CLASS_HID_252f3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1250] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23fa3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1251] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23af7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1252] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24e07,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1253] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2322f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1254] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21f1f,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1255] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21a53,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1256] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22d63,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1257] = {
+	.class_hid = BNXT_ULP_CLASS_HID_255c3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1258] = {
+	.class_hid = BNXT_ULP_CLASS_HID_242b3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1259] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23dc7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1260] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25117,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1261] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c13,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1262] = {
+	.class_hid = BNXT_ULP_CLASS_HID_218c3,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1263] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21417,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1264] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22727,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1265] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24f87,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1266] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23c77,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1267] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2378b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1268] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24adb,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1269] = {
+	.class_hid = BNXT_ULP_CLASS_HID_257b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1270] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bb7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1271] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4f2b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1272] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1613,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1273] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3987,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1274] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48ef,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1275] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0fd7,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1276] = {
+	.class_hid = BNXT_ULP_CLASS_HID_334b,
+	.class_tid = 1,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1277] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25797,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1278] = {
+	.class_hid = BNXT_ULP_CLASS_HID_285eb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1279] = {
+	.class_hid = BNXT_ULP_CLASS_HID_310eb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1280] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39beb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1281] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24447,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1282] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cf47,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1283] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35a47,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1284] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3889b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1285] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23f9b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1286] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ca9b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1287] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3559b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1288] = {
+	.class_hid = BNXT_ULP_CLASS_HID_383ef,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1289] = {
+	.class_hid = BNXT_ULP_CLASS_HID_252eb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1290] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2813f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1291] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30c3f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1292] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3973f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1293] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21e5f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1294] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a95f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1295] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3345f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1296] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bf5f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1297] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20b0f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1298] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2960f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1299] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3210f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1300] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ac0f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1301] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20643,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1302] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29143,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1303] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31c43,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1304] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a743,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1305] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21993,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1306] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a493,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1307] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32f93,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1308] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ba93,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1309] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24233,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1310] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cd33,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 118,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1311] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35833,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 119,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1312] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38607,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 120,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1313] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22ee3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 121,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1314] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b9e3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 121,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1315] = {
+	.class_hid = BNXT_ULP_CLASS_HID_344e3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 121,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1316] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cfe3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 121,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1317] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22a37,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 121,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1318] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b537,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 121,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1319] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34037,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 122,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1320] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cb37,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 123,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1321] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23d07,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1322] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c807,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1323] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35307,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1324] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3815b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1325] = {
+	.class_hid = BNXT_ULP_CLASS_HID_208fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1326] = {
+	.class_hid = BNXT_ULP_CLASS_HID_293fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1327] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31efb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1328] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a9fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1329] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25257,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1330] = {
+	.class_hid = BNXT_ULP_CLASS_HID_280ab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1331] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30bab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1332] = {
+	.class_hid = BNXT_ULP_CLASS_HID_396ab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1333] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24dab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1334] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d8ab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1335] = {
+	.class_hid = BNXT_ULP_CLASS_HID_306ff,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1336] = {
+	.class_hid = BNXT_ULP_CLASS_HID_391ff,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1337] = {
+	.class_hid = BNXT_ULP_CLASS_HID_203cf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1338] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28ecf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1339] = {
+	.class_hid = BNXT_ULP_CLASS_HID_319cf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1340] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a4cf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1341] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2515b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1342] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dc5b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1343] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30aaf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1344] = {
+	.class_hid = BNXT_ULP_CLASS_HID_395af,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1345] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23e0b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1346] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c90b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1347] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3540b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1348] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3825f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1349] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2395f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1350] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c45f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1351] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34f5f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1352] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3da5f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1353] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24caf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1354] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d7af,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1355] = {
+	.class_hid = BNXT_ULP_CLASS_HID_305e3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1356] = {
+	.class_hid = BNXT_ULP_CLASS_HID_390e3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1357] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21803,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1358] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a303,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1359] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32e03,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1360] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b903,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1361] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20533,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1362] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29033,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1363] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31b33,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1364] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a633,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1365] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20007,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1366] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28b07,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1367] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31607,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1368] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a107,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1369] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21357,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1370] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29e57,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1371] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32957,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1372] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b457,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1373] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23bf7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1374] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c6f7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1375] = {
+	.class_hid = BNXT_ULP_CLASS_HID_351f7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1376] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dcf7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1377] = {
+	.class_hid = BNXT_ULP_CLASS_HID_228a7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1378] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b3a7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1379] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33ea7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1380] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c9a7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1381] = {
+	.class_hid = BNXT_ULP_CLASS_HID_223fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1382] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2aefb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1383] = {
+	.class_hid = BNXT_ULP_CLASS_HID_339fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1384] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c4fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1385] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236cb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1386] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c1cb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1387] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34ccb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1388] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d7cb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1389] = {
+	.class_hid = BNXT_ULP_CLASS_HID_202bf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1390] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28dbf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1391] = {
+	.class_hid = BNXT_ULP_CLASS_HID_318bf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1392] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a3bf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1393] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24c1b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1394] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d71b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1395] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3056f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1396] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3906f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1397] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2476f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1398] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d26f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1399] = {
+	.class_hid = BNXT_ULP_CLASS_HID_300a3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1400] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38ba3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1401] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25abf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1402] = {
+	.class_hid = BNXT_ULP_CLASS_HID_288f3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1403] = {
+	.class_hid = BNXT_ULP_CLASS_HID_313f3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1404] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39ef3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1405] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24b1f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1406] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d61f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1407] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30453,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1408] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38f53,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1409] = {
+	.class_hid = BNXT_ULP_CLASS_HID_237cf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1410] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c2cf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1411] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34dcf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1412] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d8cf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1413] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23303,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1414] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2be03,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1415] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34903,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1416] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d403,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1417] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24653,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1418] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d153,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1419] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35c53,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1420] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38aa7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1421] = {
+	.class_hid = BNXT_ULP_CLASS_HID_211c7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1422] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29cc7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1423] = {
+	.class_hid = BNXT_ULP_CLASS_HID_327c7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1424] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b2c7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1425] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25ba3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1426] = {
+	.class_hid = BNXT_ULP_CLASS_HID_289f7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1427] = {
+	.class_hid = BNXT_ULP_CLASS_HID_314f7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1428] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39ff7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1429] = {
+	.class_hid = BNXT_ULP_CLASS_HID_256f7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1430] = {
+	.class_hid = BNXT_ULP_CLASS_HID_284cb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1431] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30fcb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1432] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39acb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1433] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20d1b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1434] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2981b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1435] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3231b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1436] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ae1b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1437] = {
+	.class_hid = BNXT_ULP_CLASS_HID_235bb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1438] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c0bb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 124,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1439] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34bbb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 125,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1440] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d6bb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 126,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1441] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2226b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 127,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1442] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ad6b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 127,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1443] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3386b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 127,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1444] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c36b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 127,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1445] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21dbf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 127,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1446] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a8bf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 127,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1447] = {
+	.class_hid = BNXT_ULP_CLASS_HID_333bf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 128,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1448] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bebf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 129,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1449] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2308f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1450] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bb8f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1451] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3468f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1452] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d18f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1453] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2592f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1454] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28763,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1455] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31263,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1456] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39d63,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1457] = {
+	.class_hid = BNXT_ULP_CLASS_HID_245df,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1458] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d0df,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1459] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35bdf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1460] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38a13,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1461] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24113,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1462] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cc13,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1463] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35713,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1464] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38567,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1465] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25463,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1466] = {
+	.class_hid = BNXT_ULP_CLASS_HID_282b7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1467] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30db7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1468] = {
+	.class_hid = BNXT_ULP_CLASS_HID_398b7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1469] = {
+	.class_hid = BNXT_ULP_CLASS_HID_244c3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1470] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cfc3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1471] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35ac3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1472] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38917,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1473] = {
+	.class_hid = BNXT_ULP_CLASS_HID_231f3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1474] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bcf3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1475] = {
+	.class_hid = BNXT_ULP_CLASS_HID_347f3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1476] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d2f3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1477] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22cc7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1478] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b7c7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1479] = {
+	.class_hid = BNXT_ULP_CLASS_HID_342c7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1480] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cdc7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1481] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24017,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1482] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cb17,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1483] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35617,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1484] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3846b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1485] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20b8b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1486] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2968b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1487] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3218b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1488] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ac8b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1489] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25567,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1490] = {
+	.class_hid = BNXT_ULP_CLASS_HID_283bb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1491] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30ebb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1492] = {
+	.class_hid = BNXT_ULP_CLASS_HID_399bb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1493] = {
+	.class_hid = BNXT_ULP_CLASS_HID_250bb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1494] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dbbb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1495] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3098f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1496] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3948f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1497] = {
+	.class_hid = BNXT_ULP_CLASS_HID_206df,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1498] = {
+	.class_hid = BNXT_ULP_CLASS_HID_291df,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1499] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31cdf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1500] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a7df,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1501] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22f7f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1502] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ba7f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1503] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3457f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1504] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d07f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1505] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21c2f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1506] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a72f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1507] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3322f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1508] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bd2f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1509] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21763,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1510] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a263,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1511] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32d63,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1512] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b863,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1513] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22ab3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1514] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b5b3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1515] = {
+	.class_hid = BNXT_ULP_CLASS_HID_340b3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1516] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cbb3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1517] = {
+	.class_hid = BNXT_ULP_CLASS_HID_252d3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1518] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28127,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1519] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30c27,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1520] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39727,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1521] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23f83,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1522] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ca83,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1523] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35583,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1524] = {
+	.class_hid = BNXT_ULP_CLASS_HID_383d7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1525] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ad7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1526] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c5d7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1527] = {
+	.class_hid = BNXT_ULP_CLASS_HID_350d7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1528] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dbd7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1529] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24e27,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1530] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d927,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1531] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3077b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1532] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3927b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1533] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2320f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1534] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bd0f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1535] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3480f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1536] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d30f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1537] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21f3f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1538] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2aa3f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1539] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3353f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1540] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c03f,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1541] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21a73,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1542] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a573,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1543] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33073,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1544] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bb73,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1545] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22d43,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1546] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b843,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1547] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34343,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1548] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ce43,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1549] = {
+	.class_hid = BNXT_ULP_CLASS_HID_255e3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1550] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28437,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1551] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30f37,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1552] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39a37,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1553] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24293,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1554] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cd93,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1555] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35893,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1556] = {
+	.class_hid = BNXT_ULP_CLASS_HID_386e7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1557] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23de7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1558] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c8e7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1559] = {
+	.class_hid = BNXT_ULP_CLASS_HID_353e7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1560] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3823b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1561] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25137,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1562] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dc37,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1563] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30a0b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1564] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3950b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1565] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c33,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1566] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b733,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1567] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34233,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1568] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cd33,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1569] = {
+	.class_hid = BNXT_ULP_CLASS_HID_218e3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1570] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a3e3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1571] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32ee3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1572] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b9e3,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1573] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21437,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1574] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29f37,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1575] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32a37,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1576] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b537,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1577] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22707,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1578] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b207,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1579] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33d07,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1580] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c807,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1581] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24fa7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1582] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2daa7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1583] = {
+	.class_hid = BNXT_ULP_CLASS_HID_308fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1584] = {
+	.class_hid = BNXT_ULP_CLASS_HID_393fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1585] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23c57,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1586] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c757,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1587] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35257,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1588] = {
+	.class_hid = BNXT_ULP_CLASS_HID_380ab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1589] = {
+	.class_hid = BNXT_ULP_CLASS_HID_237ab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1590] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c2ab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1591] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34dab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1592] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d8ab,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1593] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24afb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1594] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d5fb,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1595] = {
+	.class_hid = BNXT_ULP_CLASS_HID_303cf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1596] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38ecf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1597] = {
+	.class_hid = BNXT_ULP_CLASS_HID_255b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1598] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b97,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1599] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4f0b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1600] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1633,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1601] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39a7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1602] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48cf,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1603] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0ff7,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1604] = {
+	.class_hid = BNXT_ULP_CLASS_HID_336b,
+	.class_tid = 1,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1605] = {
+	.class_hid = BNXT_ULP_CLASS_HID_257f7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1606] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2858b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1607] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3108b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1608] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39b8b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1609] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24427,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1610] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cf27,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1611] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35a27,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1612] = {
+	.class_hid = BNXT_ULP_CLASS_HID_388fb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1613] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ffb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1614] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cafb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1615] = {
+	.class_hid = BNXT_ULP_CLASS_HID_355fb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1616] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3838f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1617] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2528b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1618] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2815f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1619] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30c5f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1620] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3975f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1621] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21e3f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1622] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a93f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1623] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3343f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1624] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bf3f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1625] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20b6f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1626] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2966f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1627] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3216f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1628] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ac6f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1629] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20623,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1630] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29123,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1631] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31c23,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1632] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a723,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1633] = {
+	.class_hid = BNXT_ULP_CLASS_HID_219f3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1634] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a4f3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1635] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32ff3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1636] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3baf3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1637] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24253,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1638] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cd53,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 130,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1639] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35853,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 131,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1640] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38667,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 132,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1641] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22e83,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 133,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1642] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b983,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 133,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1643] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34483,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 133,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1644] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cf83,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 133,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1645] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22a57,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 133,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1646] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b557,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 133,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1647] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34057,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 134,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1648] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cb57,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 135,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1649] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23d67,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1650] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c867,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1651] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35367,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1652] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3813b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1653] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2089b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1654] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2939b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1655] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31e9b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1656] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a99b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1657] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25237,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1658] = {
+	.class_hid = BNXT_ULP_CLASS_HID_280cb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1659] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30bcb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1660] = {
+	.class_hid = BNXT_ULP_CLASS_HID_396cb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1661] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24dcb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1662] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d8cb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1663] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3069f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1664] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3919f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1665] = {
+	.class_hid = BNXT_ULP_CLASS_HID_203af,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1666] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28eaf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1667] = {
+	.class_hid = BNXT_ULP_CLASS_HID_319af,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1668] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a4af,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1669] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2513b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1670] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dc3b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1671] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30acf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1672] = {
+	.class_hid = BNXT_ULP_CLASS_HID_395cf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1673] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23e6b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1674] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c96b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1675] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3546b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1676] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3823f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1677] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2393f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1678] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c43f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1679] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34f3f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1680] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3da3f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1681] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24ccf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1682] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d7cf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1683] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30583,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1684] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39083,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1685] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21863,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1686] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a363,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1687] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32e63,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1688] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b963,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1689] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20553,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1690] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29053,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1691] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31b53,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1692] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a653,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1693] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20067,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1694] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28b67,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1695] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31667,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1696] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a167,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1697] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21337,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1698] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29e37,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1699] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32937,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1700] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b437,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1701] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23b97,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1702] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c697,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1703] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35197,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1704] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dc97,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1705] = {
+	.class_hid = BNXT_ULP_CLASS_HID_228c7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1706] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b3c7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1707] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33ec7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1708] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c9c7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1709] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2239b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1710] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ae9b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1711] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3399b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1712] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c49b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1713] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236ab,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1714] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c1ab,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1715] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34cab,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1716] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d7ab,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1717] = {
+	.class_hid = BNXT_ULP_CLASS_HID_202df,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1718] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28ddf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1719] = {
+	.class_hid = BNXT_ULP_CLASS_HID_318df,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1720] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a3df,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1721] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24c7b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1722] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d77b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1723] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3050f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1724] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3900f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1725] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2470f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1726] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d20f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1727] = {
+	.class_hid = BNXT_ULP_CLASS_HID_300c3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1728] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38bc3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1729] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25adf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1730] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28893,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1731] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31393,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1732] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39e93,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1733] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24b7f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1734] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d67f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1735] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30433,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1736] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38f33,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1737] = {
+	.class_hid = BNXT_ULP_CLASS_HID_237af,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1738] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c2af,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1739] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34daf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1740] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d8af,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1741] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23363,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1742] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2be63,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1743] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34963,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1744] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d463,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1745] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24633,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1746] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d133,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1747] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35c33,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1748] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38ac7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1749] = {
+	.class_hid = BNXT_ULP_CLASS_HID_211a7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1750] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29ca7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1751] = {
+	.class_hid = BNXT_ULP_CLASS_HID_327a7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1752] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b2a7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1753] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25bc3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1754] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28997,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1755] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31497,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1756] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39f97,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1757] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25697,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1758] = {
+	.class_hid = BNXT_ULP_CLASS_HID_284ab,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1759] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30fab,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1760] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39aab,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1761] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20d7b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1762] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2987b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1763] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3237b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1764] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ae7b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1765] = {
+	.class_hid = BNXT_ULP_CLASS_HID_235db,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1766] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c0db,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 136,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1767] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34bdb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 137,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1768] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d6db,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 138,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1769] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2220b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 139,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1770] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ad0b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 139,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1771] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3380b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 139,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1772] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c30b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 139,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1773] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21ddf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 139,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1774] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a8df,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 139,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1775] = {
+	.class_hid = BNXT_ULP_CLASS_HID_333df,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 140,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1776] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bedf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 141,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1777] = {
+	.class_hid = BNXT_ULP_CLASS_HID_230ef,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1778] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bbef,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1779] = {
+	.class_hid = BNXT_ULP_CLASS_HID_346ef,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1780] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d1ef,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1781] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2594f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1782] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28703,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1783] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31203,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1784] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39d03,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1785] = {
+	.class_hid = BNXT_ULP_CLASS_HID_245bf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1786] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d0bf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1787] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35bbf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1788] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38a73,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1789] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24173,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1790] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cc73,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1791] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35773,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1792] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38507,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1793] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25403,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1794] = {
+	.class_hid = BNXT_ULP_CLASS_HID_282d7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1795] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30dd7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1796] = {
+	.class_hid = BNXT_ULP_CLASS_HID_398d7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1797] = {
+	.class_hid = BNXT_ULP_CLASS_HID_244a3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1798] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cfa3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1799] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35aa3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1800] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38977,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1801] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23193,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1802] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bc93,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1803] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34793,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1804] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d293,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1805] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22ca7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1806] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b7a7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1807] = {
+	.class_hid = BNXT_ULP_CLASS_HID_342a7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1808] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cda7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1809] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24077,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1810] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cb77,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1811] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35677,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1812] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3840b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1813] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20beb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1814] = {
+	.class_hid = BNXT_ULP_CLASS_HID_296eb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1815] = {
+	.class_hid = BNXT_ULP_CLASS_HID_321eb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1816] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3aceb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1817] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25507,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1818] = {
+	.class_hid = BNXT_ULP_CLASS_HID_283db,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1819] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30edb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1820] = {
+	.class_hid = BNXT_ULP_CLASS_HID_399db,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1821] = {
+	.class_hid = BNXT_ULP_CLASS_HID_250db,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1822] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dbdb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1823] = {
+	.class_hid = BNXT_ULP_CLASS_HID_309ef,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1824] = {
+	.class_hid = BNXT_ULP_CLASS_HID_394ef,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1825] = {
+	.class_hid = BNXT_ULP_CLASS_HID_206bf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1826] = {
+	.class_hid = BNXT_ULP_CLASS_HID_291bf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1827] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31cbf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1828] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a7bf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1829] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22f1f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1830] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ba1f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1831] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3451f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1832] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d01f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1833] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21c4f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1834] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a74f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1835] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3324f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1836] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bd4f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1837] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21703,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1838] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a203,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1839] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32d03,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1840] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b803,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1841] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22ad3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1842] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b5d3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1843] = {
+	.class_hid = BNXT_ULP_CLASS_HID_340d3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1844] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cbd3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1845] = {
+	.class_hid = BNXT_ULP_CLASS_HID_252b3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1846] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28147,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1847] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30c47,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1848] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39747,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1849] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23fe3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1850] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cae3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1851] = {
+	.class_hid = BNXT_ULP_CLASS_HID_355e3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1852] = {
+	.class_hid = BNXT_ULP_CLASS_HID_383b7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1853] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ab7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1854] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c5b7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1855] = {
+	.class_hid = BNXT_ULP_CLASS_HID_350b7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1856] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dbb7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1857] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24e47,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1858] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d947,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1859] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3071b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1860] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3921b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1861] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2326f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1862] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bd6f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1863] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3486f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1864] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d36f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1865] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21f5f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1866] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2aa5f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1867] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3355f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1868] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c05f,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1869] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21a13,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1870] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a513,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1871] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33013,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1872] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bb13,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1873] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22d23,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1874] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b823,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1875] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34323,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1876] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ce23,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1877] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25583,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1878] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28457,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1879] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30f57,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1880] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39a57,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1881] = {
+	.class_hid = BNXT_ULP_CLASS_HID_242f3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1882] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cdf3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1883] = {
+	.class_hid = BNXT_ULP_CLASS_HID_358f3,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1884] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38687,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1885] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23d87,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1886] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c887,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1887] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35387,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1888] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3825b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1889] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25157,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1890] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dc57,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1891] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30a6b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1892] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3956b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1893] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c53,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1894] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b753,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1895] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34253,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1896] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cd53,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1897] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21883,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1898] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a383,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1899] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32e83,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1900] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b983,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1901] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21457,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1902] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29f57,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1903] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32a57,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1904] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b557,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1905] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22767,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1906] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b267,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1907] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33d67,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1908] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c867,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1909] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24fc7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1910] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dac7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1911] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3089b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1912] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3939b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1913] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23c37,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1914] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c737,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1915] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35237,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1916] = {
+	.class_hid = BNXT_ULP_CLASS_HID_380cb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1917] = {
+	.class_hid = BNXT_ULP_CLASS_HID_237cb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1918] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c2cb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1919] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34dcb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1920] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d8cb,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1921] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24a9b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1922] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d59b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1923] = {
+	.class_hid = BNXT_ULP_CLASS_HID_303af,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1924] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38eaf,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1925] = {
+	.class_hid = BNXT_ULP_CLASS_HID_253b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1926] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bf7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1927] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4f6b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1928] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1653,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1929] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39c7,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1930] = {
+	.class_hid = BNXT_ULP_CLASS_HID_48af,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1931] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0f97,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1932] = {
+	.class_hid = BNXT_ULP_CLASS_HID_330b,
+	.class_tid = 1,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1933] = {
+	.class_hid = BNXT_ULP_CLASS_HID_374e,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 142,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1934] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11ee,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 143,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1935] = {
+	.class_hid = BNXT_ULP_CLASS_HID_423a,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 143,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1936] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0cd6,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 144,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1937] = {
+	.class_hid = BNXT_ULP_CLASS_HID_310a,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 144,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1938] = {
+	.class_hid = BNXT_ULP_CLASS_HID_469e,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 144,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1939] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ce6,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 144,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1940] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0692,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 144,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1941] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c7e,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 144,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1942] = {
+	.class_hid = BNXT_ULP_CLASS_HID_55c2,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 145,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1943] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b2a,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 145,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1944] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15c6,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 146,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1945] = {
+	.class_hid = BNXT_ULP_CLASS_HID_163a,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 146,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1946] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2f8e,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 146,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1947] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2516,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 146,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1948] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4b76,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 146,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1949] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10e6,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 146,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1950] = {
+	.class_hid = BNXT_ULP_CLASS_HID_264a,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 147,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1951] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3fd2,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 147,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1952] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4532,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 148,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1953] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4996,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 148,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1954] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2036,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 148,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1955] = {
+	.class_hid = BNXT_ULP_CLASS_HID_399e,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 148,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1956] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ffe,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 148,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1957] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34fe,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 148,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1958] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a32,
+	.class_tid = 2,
+	.hdr_sig_id = 0,
+	.flow_sig_id = 149,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1959] = {
+	.class_hid = BNXT_ULP_CLASS_HID_376e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 149,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1960] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12d6e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 149,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1961] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2436e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 150,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1962] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31dba,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 151,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1963] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11ce,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 152,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1964] = {
+	.class_hid = BNXT_ULP_CLASS_HID_107ce,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 152,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1965] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23dce,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 152,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1966] = {
+	.class_hid = BNXT_ULP_CLASS_HID_353ce,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 152,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1967] = {
+	.class_hid = BNXT_ULP_CLASS_HID_421a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 152,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1968] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11d56,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 152,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1969] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23356,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 153,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1970] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32956,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 154,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1971] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0cf6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1972] = {
+	.class_hid = BNXT_ULP_CLASS_HID_122f6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1973] = {
+	.class_hid = BNXT_ULP_CLASS_HID_258f6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1974] = {
+	.class_hid = BNXT_ULP_CLASS_HID_313c2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1975] = {
+	.class_hid = BNXT_ULP_CLASS_HID_312a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1976] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1272a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1977] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d2a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1978] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31466,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1979] = {
+	.class_hid = BNXT_ULP_CLASS_HID_46be,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1980] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1018a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1981] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2378a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1982] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32d8a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1983] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5cc6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1984] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11712,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1985] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20d12,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1986] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32312,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1987] = {
+	.class_hid = BNXT_ULP_CLASS_HID_06b2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1988] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13cb2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1989] = {
+	.class_hid = BNXT_ULP_CLASS_HID_252b2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1990] = {
+	.class_hid = BNXT_ULP_CLASS_HID_348b2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1991] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c5e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1992] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1325e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 155,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1993] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2285e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 156,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1994] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35e5e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 157,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1995] = {
+	.class_hid = BNXT_ULP_CLASS_HID_55e2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 158,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1996] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14be2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 158,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1997] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2023e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 158,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1998] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3383e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 158,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[1999] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b0a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 158,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2000] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1410a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 158,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2001] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21846,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 159,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2002] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30e46,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 160,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2003] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15e6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2004] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10be6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2005] = {
+	.class_hid = BNXT_ULP_CLASS_HID_221e6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2006] = {
+	.class_hid = BNXT_ULP_CLASS_HID_357e6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2007] = {
+	.class_hid = BNXT_ULP_CLASS_HID_161a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2008] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10c1a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2009] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2221a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2010] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3581a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2011] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2fae,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2012] = {
+	.class_hid = BNXT_ULP_CLASS_HID_145ae,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2013] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21cfa,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2014] = {
+	.class_hid = BNXT_ULP_CLASS_HID_332fa,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2015] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2536,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2016] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15b36,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2017] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21202,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2018] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30802,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2019] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4b56,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2020] = {
+	.class_hid = BNXT_ULP_CLASS_HID_105a2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2021] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ba2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2022] = {
+	.class_hid = BNXT_ULP_CLASS_HID_351a2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2023] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10c6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2024] = {
+	.class_hid = BNXT_ULP_CLASS_HID_106c6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 161,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2025] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23cc6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 162,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2026] = {
+	.class_hid = BNXT_ULP_CLASS_HID_352c6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 163,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2027] = {
+	.class_hid = BNXT_ULP_CLASS_HID_266a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 164,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2028] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15c6a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 164,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2029] = {
+	.class_hid = BNXT_ULP_CLASS_HID_216a6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 164,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2030] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30ca6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 164,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2031] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ff2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 164,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2032] = {
+	.class_hid = BNXT_ULP_CLASS_HID_155f2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 164,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2033] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24bf2,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 165,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2034] = {
+	.class_hid = BNXT_ULP_CLASS_HID_302ce,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 166,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2035] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4512,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2036] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11c6e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2037] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2326e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2038] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3286e,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2039] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49b6,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2040] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10082,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2041] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23682,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2042] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32c82,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2043] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2016,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2044] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15616,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2045] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21162,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2046] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30762,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2047] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39be,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2048] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12fbe,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2049] = {
+	.class_hid = BNXT_ULP_CLASS_HID_245be,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2050] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31c8a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2051] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5fde,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2052] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1162a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2053] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20c2a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2054] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3222a,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2055] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34de,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2056] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a12,
+	.class_tid = 2,
+	.hdr_sig_id = 1,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2057] = {
+	.class_hid = BNXT_ULP_CLASS_HID_370e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2058] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12d0e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 167,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2059] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2430e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 168,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2060] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31dda,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 169,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2061] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11ae,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 170,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2062] = {
+	.class_hid = BNXT_ULP_CLASS_HID_107ae,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 170,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2063] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23dae,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 170,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2064] = {
+	.class_hid = BNXT_ULP_CLASS_HID_353ae,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 170,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2065] = {
+	.class_hid = BNXT_ULP_CLASS_HID_427a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 170,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2066] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11d36,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 170,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2067] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23336,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 171,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2068] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32936,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 172,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2069] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0c96,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2070] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12296,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2071] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25896,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2072] = {
+	.class_hid = BNXT_ULP_CLASS_HID_313a2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2073] = {
+	.class_hid = BNXT_ULP_CLASS_HID_314a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2074] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1274a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2075] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d4a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2076] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31406,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2077] = {
+	.class_hid = BNXT_ULP_CLASS_HID_46de,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2078] = {
+	.class_hid = BNXT_ULP_CLASS_HID_101ea,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2079] = {
+	.class_hid = BNXT_ULP_CLASS_HID_237ea,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2080] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32dea,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2081] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ca6,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2082] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11772,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2083] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20d72,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2084] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32372,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2085] = {
+	.class_hid = BNXT_ULP_CLASS_HID_06d2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2086] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13cd2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2087] = {
+	.class_hid = BNXT_ULP_CLASS_HID_252d2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2088] = {
+	.class_hid = BNXT_ULP_CLASS_HID_348d2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2089] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c3e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2090] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1323e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 173,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2091] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2283e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 174,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2092] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35e3e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 175,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2093] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5582,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 176,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2094] = {
+	.class_hid = BNXT_ULP_CLASS_HID_14b82,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 176,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2095] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2025e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 176,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2096] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3385e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 176,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2097] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b6a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 176,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2098] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1416a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 176,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2099] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21826,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 177,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2100] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30e26,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 178,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2101] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1586,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2102] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10b86,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2103] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22186,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2104] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35786,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2105] = {
+	.class_hid = BNXT_ULP_CLASS_HID_167a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2106] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10c7a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2107] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2227a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2108] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3587a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2109] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2fce,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2110] = {
+	.class_hid = BNXT_ULP_CLASS_HID_145ce,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2111] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21c9a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2112] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3329a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2113] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2556,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2114] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15b56,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2115] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21262,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2116] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30862,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2117] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4b36,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2118] = {
+	.class_hid = BNXT_ULP_CLASS_HID_105c2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2119] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23bc2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2120] = {
+	.class_hid = BNXT_ULP_CLASS_HID_351c2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2121] = {
+	.class_hid = BNXT_ULP_CLASS_HID_10a6,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2122] = {
+	.class_hid = BNXT_ULP_CLASS_HID_106a6,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 179,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2123] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ca6,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 180,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2124] = {
+	.class_hid = BNXT_ULP_CLASS_HID_352a6,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 181,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2125] = {
+	.class_hid = BNXT_ULP_CLASS_HID_260a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 182,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2126] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15c0a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 182,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2127] = {
+	.class_hid = BNXT_ULP_CLASS_HID_216c6,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 182,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2128] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30cc6,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 182,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2129] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3f92,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 182,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2130] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15592,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 182,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2131] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24b92,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 183,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2132] = {
+	.class_hid = BNXT_ULP_CLASS_HID_302ae,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 184,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2133] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4572,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2134] = {
+	.class_hid = BNXT_ULP_CLASS_HID_11c0e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2135] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2320e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2136] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3280e,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2137] = {
+	.class_hid = BNXT_ULP_CLASS_HID_49d6,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2138] = {
+	.class_hid = BNXT_ULP_CLASS_HID_100e2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2139] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236e2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2140] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32ce2,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2141] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2076,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2142] = {
+	.class_hid = BNXT_ULP_CLASS_HID_15676,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2143] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21102,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2144] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30702,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2145] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39de,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2146] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12fde,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2147] = {
+	.class_hid = BNXT_ULP_CLASS_HID_245de,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2148] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31cea,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2149] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5fbe,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2150] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1164a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2151] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20c4a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2152] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3224a,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2153] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34be,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2154] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a72,
+	.class_tid = 2,
+	.hdr_sig_id = 2,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2155] = {
+	.class_hid = BNXT_ULP_CLASS_HID_09ea,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 185,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2156] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2912,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 186,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2157] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03b2,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 186,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2158] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5f7e,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 187,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2159] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03a6,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 187,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2160] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ce,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 187,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2161] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a6e,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 187,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2162] = {
+	.class_hid = BNXT_ULP_CLASS_HID_593a,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 187,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2163] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4dce,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 187,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2164] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0e02,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 188,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2165] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4796,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 188,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2166] = {
+	.class_hid = BNXT_ULP_CLASS_HID_246e,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 189,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2167] = {
+	.class_hid = BNXT_ULP_CLASS_HID_478a,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 189,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2168] = {
+	.class_hid = BNXT_ULP_CLASS_HID_08fe,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 189,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2169] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5e52,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 189,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2170] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3e2a,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 189,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2171] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5e46,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 189,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2172] = {
+	.class_hid = BNXT_ULP_CLASS_HID_02ba,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 190,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2173] = {
+	.class_hid = BNXT_ULP_CLASS_HID_580e,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 190,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2174] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38e6,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2175] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5802,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2176] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d76,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2177] = {
+	.class_hid = BNXT_ULP_CLASS_HID_52ca,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2178] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32a2,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2179] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34f6,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2180] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a3a,
+	.class_tid = 2,
+	.hdr_sig_id = 3,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2181] = {
+	.class_hid = BNXT_ULP_CLASS_HID_09ca,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2182] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0216,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 191,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2183] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f62,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 192,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2184] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bae,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 193,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2185] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2932,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 194,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2186] = {
+	.class_hid = BNXT_ULP_CLASS_HID_227e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 194,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2187] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3f4a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 194,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2188] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b96,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 194,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2189] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0392,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 194,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2190] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cde,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 194,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2191] = {
+	.class_hid = BNXT_ULP_CLASS_HID_192a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 195,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2192] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1276,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 196,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2193] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5f5e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2194] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5baa,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2195] = {
+	.class_hid = BNXT_ULP_CLASS_HID_54f6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2196] = {
+	.class_hid = BNXT_ULP_CLASS_HID_51c2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2197] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0386,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2198] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cd2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2199] = {
+	.class_hid = BNXT_ULP_CLASS_HID_191e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2200] = {
+	.class_hid = BNXT_ULP_CLASS_HID_126a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2201] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ee,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2202] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c3a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2203] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3906,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2204] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3252,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2205] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a4e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2206] = {
+	.class_hid = BNXT_ULP_CLASS_HID_169a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2207] = {
+	.class_hid = BNXT_ULP_CLASS_HID_13e6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2208] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4be6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2209] = {
+	.class_hid = BNXT_ULP_CLASS_HID_591a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2210] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5266,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2211] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2eb2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2212] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bfe,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2213] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4dee,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2214] = {
+	.class_hid = BNXT_ULP_CLASS_HID_463a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 197,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2215] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4306,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 198,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2216] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5c52,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 199,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2217] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0e22,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 200,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2218] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0b6e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 200,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2219] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07ba,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 200,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2220] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0086,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 200,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2221] = {
+	.class_hid = BNXT_ULP_CLASS_HID_47b6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 200,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2222] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4082,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 200,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2223] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5dce,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 201,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2224] = {
+	.class_hid = BNXT_ULP_CLASS_HID_561a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 202,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2225] = {
+	.class_hid = BNXT_ULP_CLASS_HID_244e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2226] = {
+	.class_hid = BNXT_ULP_CLASS_HID_209a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2227] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3de6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2228] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3632,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2229] = {
+	.class_hid = BNXT_ULP_CLASS_HID_47aa,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2230] = {
+	.class_hid = BNXT_ULP_CLASS_HID_40f6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2231] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5dc2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2232] = {
+	.class_hid = BNXT_ULP_CLASS_HID_560e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2233] = {
+	.class_hid = BNXT_ULP_CLASS_HID_08de,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2234] = {
+	.class_hid = BNXT_ULP_CLASS_HID_052a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2235] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e76,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2236] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b42,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2237] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5e72,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2238] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5abe,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2239] = {
+	.class_hid = BNXT_ULP_CLASS_HID_578a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2240] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50d6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2241] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3e0a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2242] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b56,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2243] = {
+	.class_hid = BNXT_ULP_CLASS_HID_37a2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2244] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30ee,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2245] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5e66,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2246] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ab2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 203,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2247] = {
+	.class_hid = BNXT_ULP_CLASS_HID_57fe,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 204,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2248] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50ca,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 205,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2249] = {
+	.class_hid = BNXT_ULP_CLASS_HID_029a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 206,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2250] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fe6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 206,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2251] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1832,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 206,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2252] = {
+	.class_hid = BNXT_ULP_CLASS_HID_157e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 206,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2253] = {
+	.class_hid = BNXT_ULP_CLASS_HID_582e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 206,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2254] = {
+	.class_hid = BNXT_ULP_CLASS_HID_557a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 206,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2255] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2e46,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 207,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2256] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a92,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 208,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2257] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38c6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2258] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3512,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2259] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0e5e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2260] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0aaa,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2261] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5822,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2262] = {
+	.class_hid = BNXT_ULP_CLASS_HID_556e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2263] = {
+	.class_hid = BNXT_ULP_CLASS_HID_51ba,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2264] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a86,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2265] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d56,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2266] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19a2,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2267] = {
+	.class_hid = BNXT_ULP_CLASS_HID_12ee,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2268] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4aee,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2269] = {
+	.class_hid = BNXT_ULP_CLASS_HID_52ea,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2270] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2f36,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2271] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2802,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2272] = {
+	.class_hid = BNXT_ULP_CLASS_HID_254e,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2273] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3282,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2274] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0fce,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2275] = {
+	.class_hid = BNXT_ULP_CLASS_HID_081a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2276] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0566,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2277] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34d6,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2278] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a1a,
+	.class_tid = 2,
+	.hdr_sig_id = 4,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2279] = {
+	.class_hid = BNXT_ULP_CLASS_HID_09aa,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2280] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0276,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 209,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2281] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f02,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 210,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2282] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bce,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 211,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2283] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2952,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 212,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2284] = {
+	.class_hid = BNXT_ULP_CLASS_HID_221e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 212,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2285] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3f2a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 212,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2286] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bf6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 212,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2287] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03f2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 212,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2288] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cbe,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 212,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2289] = {
+	.class_hid = BNXT_ULP_CLASS_HID_194a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 213,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2290] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1216,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 214,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2291] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5f3e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2292] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5bca,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2293] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5496,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2294] = {
+	.class_hid = BNXT_ULP_CLASS_HID_51a2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2295] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03e6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2296] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cb2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2297] = {
+	.class_hid = BNXT_ULP_CLASS_HID_197e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2298] = {
+	.class_hid = BNXT_ULP_CLASS_HID_120a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2299] = {
+	.class_hid = BNXT_ULP_CLASS_HID_238e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2300] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c5a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2301] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3966,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2302] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3232,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2303] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a2e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2304] = {
+	.class_hid = BNXT_ULP_CLASS_HID_16fa,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2305] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1386,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2306] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4b86,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2307] = {
+	.class_hid = BNXT_ULP_CLASS_HID_597a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2308] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5206,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2309] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ed2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2310] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b9e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2311] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4d8e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2312] = {
+	.class_hid = BNXT_ULP_CLASS_HID_465a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 215,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2313] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4366,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 216,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2314] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5c32,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 217,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2315] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0e42,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 218,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2316] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0b0e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 218,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2317] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07da,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 218,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2318] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00e6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 218,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2319] = {
+	.class_hid = BNXT_ULP_CLASS_HID_47d6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 218,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2320] = {
+	.class_hid = BNXT_ULP_CLASS_HID_40e2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 218,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2321] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5dae,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 219,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2322] = {
+	.class_hid = BNXT_ULP_CLASS_HID_567a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 220,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2323] = {
+	.class_hid = BNXT_ULP_CLASS_HID_242e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2324] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20fa,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2325] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d86,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2326] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3652,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2327] = {
+	.class_hid = BNXT_ULP_CLASS_HID_47ca,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2328] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4096,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2329] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5da2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2330] = {
+	.class_hid = BNXT_ULP_CLASS_HID_566e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2331] = {
+	.class_hid = BNXT_ULP_CLASS_HID_08be,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2332] = {
+	.class_hid = BNXT_ULP_CLASS_HID_054a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2333] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e16,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2334] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b22,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2335] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5e12,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2336] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ade,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2337] = {
+	.class_hid = BNXT_ULP_CLASS_HID_57ea,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2338] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50b6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2339] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3e6a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2340] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b36,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2341] = {
+	.class_hid = BNXT_ULP_CLASS_HID_37c2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2342] = {
+	.class_hid = BNXT_ULP_CLASS_HID_308e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2343] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5e06,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2344] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ad2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 221,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2345] = {
+	.class_hid = BNXT_ULP_CLASS_HID_579e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 222,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2346] = {
+	.class_hid = BNXT_ULP_CLASS_HID_50aa,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 223,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2347] = {
+	.class_hid = BNXT_ULP_CLASS_HID_02fa,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 224,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2348] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f86,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 224,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2349] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1852,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 224,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2350] = {
+	.class_hid = BNXT_ULP_CLASS_HID_151e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 224,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2351] = {
+	.class_hid = BNXT_ULP_CLASS_HID_584e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 224,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2352] = {
+	.class_hid = BNXT_ULP_CLASS_HID_551a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 224,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2353] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2e26,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 225,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2354] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2af2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 226,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2355] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38a6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2356] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3572,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2357] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0e3e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2358] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0aca,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2359] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5842,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2360] = {
+	.class_hid = BNXT_ULP_CLASS_HID_550e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2361] = {
+	.class_hid = BNXT_ULP_CLASS_HID_51da,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2362] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ae6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2363] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d36,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2364] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19c2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2365] = {
+	.class_hid = BNXT_ULP_CLASS_HID_128e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2366] = {
+	.class_hid = BNXT_ULP_CLASS_HID_4a8e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2367] = {
+	.class_hid = BNXT_ULP_CLASS_HID_528a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2368] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2f56,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2369] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2862,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2370] = {
+	.class_hid = BNXT_ULP_CLASS_HID_252e,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2371] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32e2,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2372] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0fae,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2373] = {
+	.class_hid = BNXT_ULP_CLASS_HID_087a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2374] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0506,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2375] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34b6,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2376] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a7a,
+	.class_tid = 2,
+	.hdr_sig_id = 5,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2377] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a73c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2378] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a040,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2379] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d640,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2380] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dd3c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2381] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cba0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2382] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c4f4,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2383] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19f38,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2384] = {
+	.class_hid = BNXT_ULP_CLASS_HID_182f4,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2385] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b098,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 227,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2386] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8dac,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 228,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2387] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a3ac,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 228,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2388] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a698,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2389] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d50c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2390] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ae50,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2391] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c450,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2392] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cb0c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2393] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a1f0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2394] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ba04,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2395] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d004,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2396] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d7f0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2397] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c264,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2398] = {
+	.class_hid = BNXT_ULP_CLASS_HID_dea8,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2399] = {
+	.class_hid = BNXT_ULP_CLASS_HID_199fc,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2400] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19ca8,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2401] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8b5c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2402] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8460,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2403] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ba60,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2404] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a15c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2405] = {
+	.class_hid = BNXT_ULP_CLASS_HID_afc0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2406] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a814,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2407] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1de14,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2408] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c5c0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2409] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8c2c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2410] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8970,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2411] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bf70,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2412] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a22c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2413] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d0d0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2414] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ade4,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2415] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c3e4,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2416] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c6d0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2417] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9988,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 229,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2418] = {
+	.class_hid = BNXT_ULP_CLASS_HID_92dc,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 230,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2419] = {
+	.class_hid = BNXT_ULP_CLASS_HID_188dc,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 230,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2420] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18f88,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2421] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ba3c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2422] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b740,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2423] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ad40,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2424] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d03c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2425] = {
+	.class_hid = BNXT_ULP_CLASS_HID_86e0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2426] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8334,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2427] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b934,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2428] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bce0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2429] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aa94,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2430] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a7d8,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2431] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ddd8,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2432] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c094,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2433] = {
+	.class_hid = BNXT_ULP_CLASS_HID_904c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2434] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c84c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2435] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18290,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2436] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1864c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2437] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b4f0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2438] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b104,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2439] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a704,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2440] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1aaf0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2441] = {
+	.class_hid = BNXT_ULP_CLASS_HID_80a4,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2442] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9de8,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2443] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b3e8,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2444] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b6a4,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2445] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a548,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2446] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a19c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2447] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d79c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2448] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1db48,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2449] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9a98,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2450] = {
+	.class_hid = BNXT_ULP_CLASS_HID_97ac,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2451] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18dac,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2452] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b098,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2453] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bf0c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2454] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b850,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2455] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ae50,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2456] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d50c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2457] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34f0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2458] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a3c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2459] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ea0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2460] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0798,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 231,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2461] = {
+	.class_hid = BNXT_ULP_CLASS_HID_280c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2462] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5964,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2463] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e5c,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2464] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c0,
+	.class_tid = 2,
+	.hdr_sig_id = 6,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2465] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a71c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2466] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a8dc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2467] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ed9c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2468] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef5c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2469] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a060,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2470] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a520,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2471] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e6e0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2472] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eba0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2473] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d660,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2474] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fb20,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2475] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dce0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2476] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e1a0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2477] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dd1c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2478] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fedc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2479] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c39c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2480] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e55c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2481] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cb80,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2482] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b194,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2483] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d354,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2484] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f414,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2485] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c4d4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2486] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e994,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2487] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cb54,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2488] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f158,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2489] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19f18,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2490] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a0d8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2491] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c598,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2492] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e758,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2493] = {
+	.class_hid = BNXT_ULP_CLASS_HID_182d4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2494] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a794,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2495] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c954,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2496] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea14,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2497] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b0b8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2498] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b278,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 232,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2499] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f738,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 233,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2500] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f8f8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 234,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2501] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8d8c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 235,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2502] = {
+	.class_hid = BNXT_ULP_CLASS_HID_af4c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 235,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2503] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f00c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 235,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2504] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f5cc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 235,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2505] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a38c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 235,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2506] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a54c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 235,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2507] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e60c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 236,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2508] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ebcc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 237,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2509] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a6b8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2510] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a878,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2511] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ed38,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2512] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eef8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2513] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d52c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2514] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f6ec,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2515] = {
+	.class_hid = BNXT_ULP_CLASS_HID_dbac,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2516] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fd6c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2517] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ae70,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2518] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f330,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2519] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d4f0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2520] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f9b0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2521] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c470,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2522] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e930,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2523] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1caf0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2524] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f084,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2525] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cb2c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2526] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b130,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2527] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d2f0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2528] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f7b0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2529] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a1d0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2530] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a290,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2531] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e450,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2532] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e910,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2533] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ba24,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2534] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bfe4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2535] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e0a4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2536] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e264,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2537] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d024,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2538] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f5e4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2539] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d6a4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2540] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f864,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2541] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d7d0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2542] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f890,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2543] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1da50,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2544] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ff10,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2545] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c244,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2546] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e704,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2547] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c8c4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2548] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ed84,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2549] = {
+	.class_hid = BNXT_ULP_CLASS_HID_de88,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2550] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e048,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2551] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c508,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2552] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e6c8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2553] = {
+	.class_hid = BNXT_ULP_CLASS_HID_199dc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2554] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ba9c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2555] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dc5c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2556] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e11c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2557] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19c88,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2558] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1be48,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2559] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c308,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2560] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e4c8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2561] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8b7c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2562] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ac3c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2563] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f1fc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2564] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f2bc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2565] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8440,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2566] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a900,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2567] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cac0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2568] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef80,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2569] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ba40,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2570] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bf00,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2571] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e0c0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2572] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e580,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2573] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a17c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2574] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a23c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2575] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e7fc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2576] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e8bc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2577] = {
+	.class_hid = BNXT_ULP_CLASS_HID_afe0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2578] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f0a0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2579] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d260,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2580] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f720,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2581] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a834,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2582] = {
+	.class_hid = BNXT_ULP_CLASS_HID_adf4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2583] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eeb4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2584] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f074,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2585] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1de34,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2586] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e3f4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2587] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c4b4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2588] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e674,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2589] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c5e0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2590] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e6a0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2591] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c860,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2592] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ed20,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2593] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8c0c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2594] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b1cc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2595] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f28c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2596] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f44c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2597] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8950,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2598] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aa10,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2599] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cfd0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2600] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f090,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2601] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bf50,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2602] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a010,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2603] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e5d0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2604] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e690,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2605] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a20c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2606] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a7cc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2607] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e88c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2608] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea4c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2609] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d0f0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2610] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f5b0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2611] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d770,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2612] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f830,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2613] = {
+	.class_hid = BNXT_ULP_CLASS_HID_adc4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2614] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ae84,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2615] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d044,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2616] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f504,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2617] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c3c4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2618] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e484,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2619] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c644,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2620] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eb04,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2621] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c6f0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2622] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ebb0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2623] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cd70,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2624] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f304,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2625] = {
+	.class_hid = BNXT_ULP_CLASS_HID_99a8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2626] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bb68,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 238,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2627] = {
+	.class_hid = BNXT_ULP_CLASS_HID_dc28,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 239,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2628] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e1e8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 240,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2629] = {
+	.class_hid = BNXT_ULP_CLASS_HID_92fc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 241,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2630] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b7bc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 241,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2631] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d97c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 241,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2632] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fa3c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 241,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2633] = {
+	.class_hid = BNXT_ULP_CLASS_HID_188fc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 241,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2634] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1adbc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 241,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2635] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cf7c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 242,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2636] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f03c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 243,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2637] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18fa8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2638] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b168,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2639] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f228,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2640] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f7e8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2641] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ba1c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2642] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bfdc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2643] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e09c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2644] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e25c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2645] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b760,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2646] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b820,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2647] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fde0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2648] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fea0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2649] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ad60,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2650] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ae20,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2651] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d3e0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2652] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f4a0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2653] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d01c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2654] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f5dc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2655] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d69c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2656] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f85c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2657] = {
+	.class_hid = BNXT_ULP_CLASS_HID_86c0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2658] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ab80,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2659] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cd40,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2660] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ee00,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2661] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8314,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2662] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a4d4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2663] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c994,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2664] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eb54,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2665] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b914,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2666] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bad4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2667] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ff94,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2668] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e154,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2669] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bcc0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2670] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a180,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2671] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e340,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2672] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e400,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2673] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aab4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2674] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ac74,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2675] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d134,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2676] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f2f4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2677] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a7f8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2678] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a8b8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2679] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ea78,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2680] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef38,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2681] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ddf8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2682] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1feb8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2683] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c078,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2684] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e538,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2685] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c0b4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2686] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e274,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2687] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c734,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2688] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e8f4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2689] = {
+	.class_hid = BNXT_ULP_CLASS_HID_906c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2690] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b52c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2691] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d6ec,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2692] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fbac,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2693] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c86c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2694] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ed2c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2695] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d330,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2696] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f4f0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2697] = {
+	.class_hid = BNXT_ULP_CLASS_HID_182b0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2698] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a470,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2699] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c930,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2700] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eaf0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2701] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1866c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2702] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ab2c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2703] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ccec,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2704] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f1ac,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2705] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b4d0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2706] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b990,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2707] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fb50,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2708] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fc10,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2709] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b124,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2710] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b2e4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2711] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f7a4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2712] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f964,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2713] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a724,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2714] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a8e4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2715] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eda4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2716] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ef64,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2717] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1aad0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2718] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1af90,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2719] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d150,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2720] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f210,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2721] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8084,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2722] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a244,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2723] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c704,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2724] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e8c4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2725] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9dc8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2726] = {
+	.class_hid = BNXT_ULP_CLASS_HID_be88,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2727] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c048,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2728] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e508,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2729] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b3c8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2730] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b488,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2731] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f648,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2732] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fb08,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2733] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b684,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2734] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b844,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2735] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fd04,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2736] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fec4,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2737] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a568,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2738] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a628,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2739] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ebe8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2740] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eca8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2741] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a1bc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2742] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a37c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2743] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e43c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2744] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e9fc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2745] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d7bc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2746] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f97c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2747] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1da3c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2748] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fffc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2749] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1db68,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2750] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fc28,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2751] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c1e8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2752] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e2a8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2753] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9ab8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2754] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bc78,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2755] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c138,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2756] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e2f8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2757] = {
+	.class_hid = BNXT_ULP_CLASS_HID_978c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2758] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b94c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2759] = {
+	.class_hid = BNXT_ULP_CLASS_HID_da0c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2760] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ffcc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2761] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18d8c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2762] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1af4c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2763] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f00c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2764] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f5cc,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2765] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b0b8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2766] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b278,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2767] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f738,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2768] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f8f8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2769] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bf2c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2770] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a0ec,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2771] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e5ac,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2772] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e76c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2773] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b870,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2774] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bd30,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2775] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fef0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2776] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e3b0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2777] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ae70,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2778] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f330,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2779] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d4f0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2780] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f9b0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2781] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d52c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2782] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f6ec,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2783] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dbac,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2784] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fd6c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2785] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34d0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2786] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a1c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2787] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5e80,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2788] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07b8,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2789] = {
+	.class_hid = BNXT_ULP_CLASS_HID_282c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2790] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5944,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2791] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e7c,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2792] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22e0,
+	.class_tid = 2,
+	.hdr_sig_id = 7,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2793] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a77c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2794] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a8bc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2795] = {
+	.class_hid = BNXT_ULP_CLASS_HID_edfc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2796] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef3c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2797] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a000,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2798] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a540,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2799] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e680,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2800] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ebc0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2801] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d600,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2802] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fb40,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2803] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dc80,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2804] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e1c0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2805] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dd7c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2806] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1febc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2807] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c3fc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2808] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e53c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2809] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cbe0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2810] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b1f4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2811] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d334,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2812] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f474,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2813] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c4b4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2814] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e9f4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2815] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cb34,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2816] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f138,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2817] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19f78,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2818] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a0b8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2819] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c5f8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2820] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e738,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2821] = {
+	.class_hid = BNXT_ULP_CLASS_HID_182b4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2822] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a7f4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2823] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c934,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2824] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea74,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2825] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b0d8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2826] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b218,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 244,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2827] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f758,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 245,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2828] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f898,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 246,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2829] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8dec,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 247,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2830] = {
+	.class_hid = BNXT_ULP_CLASS_HID_af2c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 247,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2831] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f06c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 247,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2832] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f5ac,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 247,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2833] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a3ec,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 247,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2834] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a52c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 247,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2835] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e66c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 248,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2836] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ebac,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 249,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2837] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a6d8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2838] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a818,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2839] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ed58,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2840] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ee98,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2841] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d54c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2842] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f68c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2843] = {
+	.class_hid = BNXT_ULP_CLASS_HID_dbcc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2844] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fd0c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2845] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ae10,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2846] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f350,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2847] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d490,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2848] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f9d0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2849] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c410,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2850] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e950,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2851] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ca90,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2852] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f0e4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2853] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cb4c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2854] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b150,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2855] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d290,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2856] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f7d0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2857] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a1b0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2858] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a2f0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2859] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e430,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2860] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e970,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2861] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ba44,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2862] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bf84,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2863] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e0c4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2864] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e204,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2865] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d044,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2866] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f584,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2867] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d6c4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2868] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f804,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2869] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d7b0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2870] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f8f0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2871] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1da30,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2872] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ff70,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2873] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c224,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2874] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e764,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2875] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c8a4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2876] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ede4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2877] = {
+	.class_hid = BNXT_ULP_CLASS_HID_dee8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2878] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e028,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2879] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c568,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2880] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e6a8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2881] = {
+	.class_hid = BNXT_ULP_CLASS_HID_199bc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2882] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bafc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2883] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dc3c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2884] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e17c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2885] = {
+	.class_hid = BNXT_ULP_CLASS_HID_19ce8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2886] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1be28,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2887] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c368,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2888] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e4a8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2889] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8b1c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2890] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ac5c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2891] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f19c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2892] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f2dc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2893] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8420,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2894] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a960,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2895] = {
+	.class_hid = BNXT_ULP_CLASS_HID_caa0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2896] = {
+	.class_hid = BNXT_ULP_CLASS_HID_efe0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2897] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ba20,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2898] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bf60,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2899] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e0a0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2900] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e5e0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2901] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a11c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2902] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a25c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2903] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e79c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2904] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e8dc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2905] = {
+	.class_hid = BNXT_ULP_CLASS_HID_af80,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2906] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f0c0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2907] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d200,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2908] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f740,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2909] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a854,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2910] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ad94,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2911] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eed4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2912] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f014,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2913] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1de54,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2914] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e394,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2915] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c4d4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2916] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e614,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2917] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c580,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2918] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e6c0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2919] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c800,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2920] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ed40,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2921] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8c6c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2922] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b1ac,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2923] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f2ec,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2924] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f42c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2925] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8930,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2926] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aa70,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2927] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cfb0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2928] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f0f0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2929] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bf30,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2930] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a070,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2931] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e5b0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2932] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e6f0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2933] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a26c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2934] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a7ac,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2935] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e8ec,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2936] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea2c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2937] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d090,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2938] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f5d0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2939] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d710,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2940] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f850,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2941] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ada4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2942] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aee4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2943] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d024,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2944] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f564,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2945] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c3a4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2946] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e4e4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2947] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c624,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2948] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1eb64,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2949] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c690,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2950] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ebd0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2951] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cd10,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2952] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f364,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2953] = {
+	.class_hid = BNXT_ULP_CLASS_HID_99c8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2954] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bb08,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 250,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2955] = {
+	.class_hid = BNXT_ULP_CLASS_HID_dc48,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 251,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2956] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e188,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 252,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2957] = {
+	.class_hid = BNXT_ULP_CLASS_HID_929c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 253,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2958] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b7dc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 253,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2959] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d91c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 253,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2960] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fa5c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 253,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2961] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1889c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 253,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2962] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1addc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 253,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2963] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cf1c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 254,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2964] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f05c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 255,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2965] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18fc8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2966] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b108,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2967] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f248,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2968] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f788,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2969] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ba7c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2970] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bfbc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2971] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e0fc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2972] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e23c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2973] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b700,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2974] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b840,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2975] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fd80,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2976] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fec0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2977] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ad00,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2978] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ae40,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2979] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d380,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2980] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f4c0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2981] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d07c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2982] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f5bc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2983] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d6fc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2984] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f83c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2985] = {
+	.class_hid = BNXT_ULP_CLASS_HID_86a0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2986] = {
+	.class_hid = BNXT_ULP_CLASS_HID_abe0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2987] = {
+	.class_hid = BNXT_ULP_CLASS_HID_cd20,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2988] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ee60,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2989] = {
+	.class_hid = BNXT_ULP_CLASS_HID_8374,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2990] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a4b4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2991] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c9f4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2992] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eb34,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2993] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b974,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2994] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bab4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2995] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fff4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2996] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e134,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2997] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1bca0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2998] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a1e0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[2999] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e320,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3000] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e460,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3001] = {
+	.class_hid = BNXT_ULP_CLASS_HID_aad4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3002] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ac14,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3003] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d154,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3004] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f294,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3005] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a798,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3006] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a8d8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3007] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ea18,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3008] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ef58,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3009] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dd98,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3010] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fed8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3011] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c018,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3012] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e558,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3013] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c0d4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3014] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e214,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3015] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c754,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3016] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e894,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3017] = {
+	.class_hid = BNXT_ULP_CLASS_HID_900c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3018] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b54c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3019] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d68c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3020] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fbcc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3021] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c80c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3022] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ed4c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3023] = {
+	.class_hid = BNXT_ULP_CLASS_HID_d350,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3024] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f490,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3025] = {
+	.class_hid = BNXT_ULP_CLASS_HID_182d0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3026] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a410,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3027] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c950,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3028] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ea90,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3029] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1860c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3030] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ab4c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3031] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1cc8c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3032] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f1cc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3033] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b4b0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3034] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b9f0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3035] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fb30,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3036] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fc70,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3037] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b144,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3038] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b284,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3039] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f7c4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3040] = {
+	.class_hid = BNXT_ULP_CLASS_HID_f904,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3041] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a744,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3042] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1a884,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3043] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1edc4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3044] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ef04,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3045] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1aab0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3046] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1aff0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3047] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d130,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3048] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f270,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3049] = {
+	.class_hid = BNXT_ULP_CLASS_HID_80e4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3050] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a224,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3051] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c764,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3052] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e8a4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3053] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9da8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3054] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bee8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3055] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c028,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3056] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e568,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3057] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b3a8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3058] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b4e8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3059] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f628,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3060] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fb68,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3061] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b6e4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3062] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b824,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3063] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fd64,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3064] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fea4,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3065] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a508,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3066] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a648,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3067] = {
+	.class_hid = BNXT_ULP_CLASS_HID_eb88,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3068] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ecc8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3069] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a1dc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3070] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a31c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3071] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e45c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3072] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e99c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3073] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d7dc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3074] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f91c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3075] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1da5c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3076] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ff9c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3077] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1db08,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3078] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fc48,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3079] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1c188,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3080] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e2c8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3081] = {
+	.class_hid = BNXT_ULP_CLASS_HID_9ad8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3082] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bc18,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3083] = {
+	.class_hid = BNXT_ULP_CLASS_HID_c158,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3084] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e298,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3085] = {
+	.class_hid = BNXT_ULP_CLASS_HID_97ec,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3086] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b92c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3087] = {
+	.class_hid = BNXT_ULP_CLASS_HID_da6c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3088] = {
+	.class_hid = BNXT_ULP_CLASS_HID_ffac,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3089] = {
+	.class_hid = BNXT_ULP_CLASS_HID_18dec,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3090] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1af2c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3091] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f06c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3092] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f5ac,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3093] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b0d8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3094] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1b218,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3095] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f758,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3096] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f898,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3097] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bf4c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3098] = {
+	.class_hid = BNXT_ULP_CLASS_HID_a08c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3099] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e5cc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3100] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e70c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3101] = {
+	.class_hid = BNXT_ULP_CLASS_HID_b810,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3102] = {
+	.class_hid = BNXT_ULP_CLASS_HID_bd50,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3103] = {
+	.class_hid = BNXT_ULP_CLASS_HID_fe90,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3104] = {
+	.class_hid = BNXT_ULP_CLASS_HID_e3d0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3105] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1ae10,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3106] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f350,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3107] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d490,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3108] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f9d0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3109] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1d54c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3110] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1f68c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3111] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1dbcc,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3112] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1fd0c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3113] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34b0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3114] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a7c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3115] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ee0,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3116] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07d8,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3117] = {
+	.class_hid = BNXT_ULP_CLASS_HID_284c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3118] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5924,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3119] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e1c,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3120] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2280,
+	.class_tid = 2,
+	.hdr_sig_id = 8,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3121] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24604,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3122] = {
+	.class_hid = BNXT_ULP_CLASS_HID_255d4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3123] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22e08,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3124] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24378,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3125] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20fcc,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3126] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21a9c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3127] = {
+	.class_hid = BNXT_ULP_CLASS_HID_217d0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3128] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20800,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3129] = {
+	.class_hid = BNXT_ULP_CLASS_HID_253a0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 256,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3130] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23f70,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 257,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3131] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23ba4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 257,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3132] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c94,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3133] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21968,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3134] = {
+	.class_hid = BNXT_ULP_CLASS_HID_243c4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3135] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25c38,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3136] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2125c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3137] = {
+	.class_hid = BNXT_ULP_CLASS_HID_240c8,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3138] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22f98,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3139] = {
+	.class_hid = BNXT_ULP_CLASS_HID_228cc,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3140] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d3c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3141] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20990,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3142] = {
+	.class_hid = BNXT_ULP_CLASS_HID_214a0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3143] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21194,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3144] = {
+	.class_hid = BNXT_ULP_CLASS_HID_202c4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3145] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22a64,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3146] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23934,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3147] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23268,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3148] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22758,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3149] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2132c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3150] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d88,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3151] = {
+	.class_hid = BNXT_ULP_CLASS_HID_256fc,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3152] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24b2c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3153] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22f14,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3154] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23a24,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3155] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23718,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3156] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22848,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3157] = {
+	.class_hid = BNXT_ULP_CLASS_HID_214dc,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3158] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25eb8,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3159] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25bec,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3160] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21110,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3161] = {
+	.class_hid = BNXT_ULP_CLASS_HID_238b0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 258,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3162] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20440,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 259,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3163] = {
+	.class_hid = BNXT_ULP_CLASS_HID_200b4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 259,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3164] = {
+	.class_hid = BNXT_ULP_CLASS_HID_235e4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3165] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d04,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3166] = {
+	.class_hid = BNXT_ULP_CLASS_HID_228d4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3167] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22508,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3168] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25678,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3169] = {
+	.class_hid = BNXT_ULP_CLASS_HID_229d8,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3170] = {
+	.class_hid = BNXT_ULP_CLASS_HID_234e8,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3171] = {
+	.class_hid = BNXT_ULP_CLASS_HID_231dc,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3172] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2220c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3173] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24dac,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3174] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2597c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3175] = {
+	.class_hid = BNXT_ULP_CLASS_HID_255b0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3176] = {
+	.class_hid = BNXT_ULP_CLASS_HID_246e0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3177] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23374,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3178] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21e04,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3179] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21b78,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3180] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20fa8,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3181] = {
+	.class_hid = BNXT_ULP_CLASS_HID_257c8,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3182] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22298,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3183] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23fcc,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3184] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2503c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3185] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2239c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3186] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20eac,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3187] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20be0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3188] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23cd0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3189] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24470,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3190] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25300,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3191] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c74,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3192] = {
+	.class_hid = BNXT_ULP_CLASS_HID_240a4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3193] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23da0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3194] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20970,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3195] = {
+	.class_hid = BNXT_ULP_CLASS_HID_205a4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3196] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23694,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3197] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25e34,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3198] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22dc4,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3199] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22638,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3200] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25b68,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3201] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34c8,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3202] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a04,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3203] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5e98,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3204] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07a0,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3205] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2834,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3206] = {
+	.class_hid = BNXT_ULP_CLASS_HID_595c,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3207] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e64,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3208] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22f8,
+	.class_tid = 2,
+	.hdr_sig_id = 9,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3209] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24664,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3210] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29418,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3211] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30118,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3212] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38a18,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3213] = {
+	.class_hid = BNXT_ULP_CLASS_HID_255b4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3214] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2deb4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3215] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34bb4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3216] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39968,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3217] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22e68,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3218] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2db68,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3219] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34468,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3220] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3921c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3221] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24318,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3222] = {
+	.class_hid = BNXT_ULP_CLASS_HID_290cc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3223] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31dcc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3224] = {
+	.class_hid = BNXT_ULP_CLASS_HID_386cc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3225] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20fac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3226] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b8ac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3227] = {
+	.class_hid = BNXT_ULP_CLASS_HID_325ac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3228] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3aeac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3229] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21afc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3230] = {
+	.class_hid = BNXT_ULP_CLASS_HID_287fc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3231] = {
+	.class_hid = BNXT_ULP_CLASS_HID_330fc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3232] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bdfc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3233] = {
+	.class_hid = BNXT_ULP_CLASS_HID_217b0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3234] = {
+	.class_hid = BNXT_ULP_CLASS_HID_280b0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3235] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30db0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3236] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b6b0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3237] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20860,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3238] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b560,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3239] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33e60,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3240] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ab60,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3241] = {
+	.class_hid = BNXT_ULP_CLASS_HID_253c0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3242] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dcc0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 260,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3243] = {
+	.class_hid = BNXT_ULP_CLASS_HID_349c0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 261,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3244] = {
+	.class_hid = BNXT_ULP_CLASS_HID_397f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 262,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3245] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23f10,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 263,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3246] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a810,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 263,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3247] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35510,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 263,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3248] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3de10,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 263,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3249] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23bc4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 263,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3250] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a4c4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 263,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3251] = {
+	.class_hid = BNXT_ULP_CLASS_HID_351c4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 264,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3252] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dac4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 265,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3253] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22cf4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3254] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d9f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3255] = {
+	.class_hid = BNXT_ULP_CLASS_HID_342f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3256] = {
+	.class_hid = BNXT_ULP_CLASS_HID_390a8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3257] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21908,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3258] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28208,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3259] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30f08,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3260] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b808,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3261] = {
+	.class_hid = BNXT_ULP_CLASS_HID_243a4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3262] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29158,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3263] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31a58,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3264] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38758,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3265] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25c58,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3266] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c958,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3267] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3170c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3268] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3800c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3269] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2123c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3270] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29f3c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3271] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3083c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3272] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b53c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3273] = {
+	.class_hid = BNXT_ULP_CLASS_HID_240a8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3274] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cda8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3275] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31b5c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3276] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3845c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3277] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22ff8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3278] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d8f8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3279] = {
+	.class_hid = BNXT_ULP_CLASS_HID_345f8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3280] = {
+	.class_hid = BNXT_ULP_CLASS_HID_393ac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3281] = {
+	.class_hid = BNXT_ULP_CLASS_HID_228ac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3282] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d5ac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3283] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35eac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3284] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cbac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3285] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d5c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3286] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c65c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3287] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31410,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3288] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38110,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3289] = {
+	.class_hid = BNXT_ULP_CLASS_HID_209f0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3290] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b2f0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3291] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33ff0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3292] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a8f0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3293] = {
+	.class_hid = BNXT_ULP_CLASS_HID_214c0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3294] = {
+	.class_hid = BNXT_ULP_CLASS_HID_281c0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3295] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30ac0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3296] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b7c0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3297] = {
+	.class_hid = BNXT_ULP_CLASS_HID_211f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3298] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29af4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3299] = {
+	.class_hid = BNXT_ULP_CLASS_HID_307f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3300] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b0f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3301] = {
+	.class_hid = BNXT_ULP_CLASS_HID_202a4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3302] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28fa4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3303] = {
+	.class_hid = BNXT_ULP_CLASS_HID_338a4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3304] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a5a4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3305] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22a04,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3306] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d704,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3307] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34004,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3308] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cd04,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3309] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23954,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3310] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a254,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3311] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32f54,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3312] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d854,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3313] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23208,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3314] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bf08,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3315] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32808,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3316] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d508,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3317] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22738,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3318] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d038,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3319] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35d38,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3320] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c638,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3321] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2134c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3322] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29c4c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3323] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3094c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3324] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b24c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3325] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25de8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3326] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c6e8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3327] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3149c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3328] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3819c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3329] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2569c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3330] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c39c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3331] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31150,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3332] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39a50,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3333] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24b4c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3334] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29900,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3335] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30200,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3336] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38f00,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3337] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22f74,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3338] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d874,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3339] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34574,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3340] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39328,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3341] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23a44,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3342] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a744,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3343] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35044,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3344] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dd44,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3345] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23778,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3346] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a078,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3347] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32d78,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3348] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d678,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3349] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22828,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3350] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d528,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3351] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35e28,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3352] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cb28,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3353] = {
+	.class_hid = BNXT_ULP_CLASS_HID_214bc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3354] = {
+	.class_hid = BNXT_ULP_CLASS_HID_281bc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3355] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30abc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3356] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b7bc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3357] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25ed8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3358] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cbd8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3359] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3198c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3360] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3828c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3361] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25b8c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3362] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c48c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3363] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31240,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3364] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39f40,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3365] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21170,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3366] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29a70,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3367] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30770,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3368] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b070,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3369] = {
+	.class_hid = BNXT_ULP_CLASS_HID_238d0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3370] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a5d0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 266,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3371] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32ed0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 267,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3372] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dbd0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 268,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3373] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20420,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 269,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3374] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b120,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 269,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3375] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33a20,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 269,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3376] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a720,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 269,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3377] = {
+	.class_hid = BNXT_ULP_CLASS_HID_200d4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 269,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3378] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28dd4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 269,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3379] = {
+	.class_hid = BNXT_ULP_CLASS_HID_336d4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 270,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3380] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a3d4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 271,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3381] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23584,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3382] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2be84,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3383] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32b84,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3384] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d484,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3385] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d64,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3386] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c664,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3387] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31418,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3388] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38118,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3389] = {
+	.class_hid = BNXT_ULP_CLASS_HID_228b4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3390] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d5b4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3391] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35eb4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3392] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cbb4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3393] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22568,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3394] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ae68,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3395] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35b68,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3396] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c468,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3397] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25618,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3398] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c318,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3399] = {
+	.class_hid = BNXT_ULP_CLASS_HID_310cc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3400] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39dcc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3401] = {
+	.class_hid = BNXT_ULP_CLASS_HID_229b8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3402] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d2b8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3403] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35fb8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3404] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c8b8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3405] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23488,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3406] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a188,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3407] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32a88,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3408] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d788,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3409] = {
+	.class_hid = BNXT_ULP_CLASS_HID_231bc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3410] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2babc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3411] = {
+	.class_hid = BNXT_ULP_CLASS_HID_327bc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3412] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d0bc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3413] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2226c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3414] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2af6c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3415] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3586c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3416] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c56c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3417] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24dcc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3418] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29b80,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3419] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30480,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3420] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b180,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3421] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2591c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3422] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c21c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3423] = {
+	.class_hid = BNXT_ULP_CLASS_HID_313d0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3424] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39cd0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3425] = {
+	.class_hid = BNXT_ULP_CLASS_HID_255d0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3426] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ded0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3427] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34bd0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3428] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39984,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3429] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24680,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3430] = {
+	.class_hid = BNXT_ULP_CLASS_HID_294b4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3431] = {
+	.class_hid = BNXT_ULP_CLASS_HID_301b4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3432] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38ab4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3433] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23314,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3434] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bc14,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3435] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32914,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3436] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d214,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3437] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21e64,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3438] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28b64,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3439] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33464,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3440] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a164,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3441] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21b18,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3442] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28418,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3443] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33118,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3444] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ba18,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3445] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20fc8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3446] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b8c8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3447] = {
+	.class_hid = BNXT_ULP_CLASS_HID_325c8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3448] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3aec8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3449] = {
+	.class_hid = BNXT_ULP_CLASS_HID_257a8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3450] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c0a8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3451] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34da8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3452] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39b5c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3453] = {
+	.class_hid = BNXT_ULP_CLASS_HID_222f8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3454] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2aff8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3455] = {
+	.class_hid = BNXT_ULP_CLASS_HID_358f8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3456] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c5f8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3457] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23fac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3458] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a8ac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3459] = {
+	.class_hid = BNXT_ULP_CLASS_HID_355ac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3460] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3deac,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3461] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2505c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3462] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dd5c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3463] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3465c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3464] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39410,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3465] = {
+	.class_hid = BNXT_ULP_CLASS_HID_223fc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3466] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2acfc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3467] = {
+	.class_hid = BNXT_ULP_CLASS_HID_359fc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3468] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c2fc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3469] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20ecc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3470] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bbcc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3471] = {
+	.class_hid = BNXT_ULP_CLASS_HID_324cc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3472] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d1cc,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3473] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20b80,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3474] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b480,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3475] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32180,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3476] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3aa80,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3477] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23cb0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3478] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a9b0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3479] = {
+	.class_hid = BNXT_ULP_CLASS_HID_352b0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3480] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dfb0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3481] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24410,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3482] = {
+	.class_hid = BNXT_ULP_CLASS_HID_295c4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3483] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31ec4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3484] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38bc4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3485] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25360,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3486] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dc60,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3487] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34960,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3488] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39714,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3489] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c14,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3490] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d914,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3491] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34214,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3492] = {
+	.class_hid = BNXT_ULP_CLASS_HID_393c8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3493] = {
+	.class_hid = BNXT_ULP_CLASS_HID_240c4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3494] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cdc4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3495] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31bf8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3496] = {
+	.class_hid = BNXT_ULP_CLASS_HID_384f8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3497] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23dc0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3498] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a6c0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3499] = {
+	.class_hid = BNXT_ULP_CLASS_HID_353c0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3500] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dcc0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3501] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20910,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3502] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b210,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3503] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33f10,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3504] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a810,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3505] = {
+	.class_hid = BNXT_ULP_CLASS_HID_205c4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3506] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28ec4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3507] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33bc4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3508] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a4c4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3509] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3510] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a3f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3511] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32cf4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3512] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d9f4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3513] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25e54,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3514] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cb54,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3515] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31908,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3516] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38208,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3517] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22da4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3518] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d6a4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3519] = {
+	.class_hid = BNXT_ULP_CLASS_HID_343a4,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3520] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39158,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3521] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22658,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3522] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d358,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3523] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35c58,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3524] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c958,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3525] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25b08,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3526] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c408,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3527] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3123c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3528] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39f3c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3529] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34a8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3530] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a64,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3531] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ef8,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3532] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07c0,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3533] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2854,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3534] = {
+	.class_hid = BNXT_ULP_CLASS_HID_593c,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3535] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e04,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3536] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2298,
+	.class_tid = 2,
+	.hdr_sig_id = 10,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3537] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24644,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3538] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29438,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3539] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30138,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3540] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38a38,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3541] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25594,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3542] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2de94,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3543] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34b94,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3544] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39948,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3545] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22e48,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3546] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2db48,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3547] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34448,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3548] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3923c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3549] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24338,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3550] = {
+	.class_hid = BNXT_ULP_CLASS_HID_290ec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3551] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31dec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3552] = {
+	.class_hid = BNXT_ULP_CLASS_HID_386ec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3553] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20f8c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3554] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b88c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3555] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3258c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3556] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ae8c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3557] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21adc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3558] = {
+	.class_hid = BNXT_ULP_CLASS_HID_287dc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3559] = {
+	.class_hid = BNXT_ULP_CLASS_HID_330dc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3560] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3bddc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3561] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21790,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3562] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28090,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3563] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30d90,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3564] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b690,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3565] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20840,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3566] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b540,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3567] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33e40,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3568] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ab40,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3569] = {
+	.class_hid = BNXT_ULP_CLASS_HID_253e0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3570] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dce0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 272,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3571] = {
+	.class_hid = BNXT_ULP_CLASS_HID_349e0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 273,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3572] = {
+	.class_hid = BNXT_ULP_CLASS_HID_397d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 274,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3573] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23f30,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 275,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3574] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a830,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 275,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3575] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35530,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 275,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3576] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3de30,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 275,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3577] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23be4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 275,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3578] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a4e4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 275,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3579] = {
+	.class_hid = BNXT_ULP_CLASS_HID_351e4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 276,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3580] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dae4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 277,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3581] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22cd4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3582] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d9d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3583] = {
+	.class_hid = BNXT_ULP_CLASS_HID_342d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3584] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39088,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3585] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21928,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3586] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28228,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3587] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30f28,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3588] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b828,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3589] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24384,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3590] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29178,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3591] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31a78,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3592] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38778,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3593] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25c78,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3594] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c978,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3595] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3172c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3596] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3802c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3597] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2121c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3598] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29f1c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3599] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3081c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3600] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b51c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3601] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24088,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3602] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cd88,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3603] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31b7c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3604] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3847c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3605] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22fd8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3606] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d8d8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3607] = {
+	.class_hid = BNXT_ULP_CLASS_HID_345d8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3608] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3938c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3609] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2288c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3610] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d58c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3611] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35e8c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3612] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cb8c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3613] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d7c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3614] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c67c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3615] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31430,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3616] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38130,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3617] = {
+	.class_hid = BNXT_ULP_CLASS_HID_209d0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3618] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b2d0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3619] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33fd0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3620] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a8d0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3621] = {
+	.class_hid = BNXT_ULP_CLASS_HID_214e0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3622] = {
+	.class_hid = BNXT_ULP_CLASS_HID_281e0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3623] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30ae0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3624] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b7e0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3625] = {
+	.class_hid = BNXT_ULP_CLASS_HID_211d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3626] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29ad4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3627] = {
+	.class_hid = BNXT_ULP_CLASS_HID_307d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3628] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b0d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3629] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20284,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3630] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28f84,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3631] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33884,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3632] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a584,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3633] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22a24,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3634] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d724,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3635] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34024,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3636] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cd24,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3637] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23974,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3638] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a274,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3639] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32f74,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3640] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d874,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3641] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23228,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3642] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bf28,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3643] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32828,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3644] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d528,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3645] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22718,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3646] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d018,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3647] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35d18,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3648] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c618,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3649] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2136c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3650] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29c6c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3651] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3096c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3652] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b26c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3653] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25dc8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3654] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c6c8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3655] = {
+	.class_hid = BNXT_ULP_CLASS_HID_314bc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3656] = {
+	.class_hid = BNXT_ULP_CLASS_HID_381bc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3657] = {
+	.class_hid = BNXT_ULP_CLASS_HID_256bc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3658] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c3bc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3659] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31170,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3660] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39a70,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3661] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24b6c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3662] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29920,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3663] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30220,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3664] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38f20,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3665] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22f54,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3666] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d854,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3667] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34554,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3668] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39308,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3669] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23a64,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3670] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a764,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3671] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35064,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3672] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dd64,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3673] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23758,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3674] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a058,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3675] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32d58,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3676] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d658,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3677] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22808,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3678] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d508,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3679] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35e08,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3680] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cb08,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3681] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2149c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3682] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2819c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3683] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30a9c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3684] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b79c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3685] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25ef8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3686] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cbf8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3687] = {
+	.class_hid = BNXT_ULP_CLASS_HID_319ac,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3688] = {
+	.class_hid = BNXT_ULP_CLASS_HID_382ac,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3689] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25bac,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3690] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c4ac,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3691] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31260,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3692] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39f60,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3693] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21150,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3694] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29a50,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3695] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30750,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3696] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b050,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3697] = {
+	.class_hid = BNXT_ULP_CLASS_HID_238f0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3698] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a5f0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 278,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3699] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32ef0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 279,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3700] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dbf0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 280,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3701] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20400,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 281,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3702] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b100,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 281,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3703] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33a00,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 281,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3704] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a700,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 281,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3705] = {
+	.class_hid = BNXT_ULP_CLASS_HID_200f4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 281,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3706] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28df4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 281,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3707] = {
+	.class_hid = BNXT_ULP_CLASS_HID_336f4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 282,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3708] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a3f4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 283,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3709] = {
+	.class_hid = BNXT_ULP_CLASS_HID_235a4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3710] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bea4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3711] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32ba4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3712] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d4a4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3713] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25d44,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3714] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c644,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3715] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31438,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3716] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38138,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3717] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22894,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3718] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d594,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3719] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35e94,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3720] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3cb94,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3721] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22548,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3722] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ae48,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3723] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35b48,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3724] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c448,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3725] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25638,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3726] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c338,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3727] = {
+	.class_hid = BNXT_ULP_CLASS_HID_310ec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3728] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39dec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3729] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22998,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3730] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d298,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3731] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35f98,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3732] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c898,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3733] = {
+	.class_hid = BNXT_ULP_CLASS_HID_234a8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3734] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a1a8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3735] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32aa8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3736] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d7a8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3737] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2319c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3738] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2ba9c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3739] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3279c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3740] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d09c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3741] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2224c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3742] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2af4c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3743] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3584c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3744] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c54c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3745] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24dec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3746] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29ba0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3747] = {
+	.class_hid = BNXT_ULP_CLASS_HID_304a0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3748] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3b1a0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3749] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2593c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3750] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c23c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3751] = {
+	.class_hid = BNXT_ULP_CLASS_HID_313f0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3752] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39cf0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3753] = {
+	.class_hid = BNXT_ULP_CLASS_HID_255f0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3754] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2def0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3755] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34bf0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3756] = {
+	.class_hid = BNXT_ULP_CLASS_HID_399a4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3757] = {
+	.class_hid = BNXT_ULP_CLASS_HID_246a0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3758] = {
+	.class_hid = BNXT_ULP_CLASS_HID_29494,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3759] = {
+	.class_hid = BNXT_ULP_CLASS_HID_30194,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3760] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38a94,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3761] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23334,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3762] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bc34,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3763] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32934,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3764] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d234,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3765] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21e44,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3766] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28b44,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3767] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33444,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3768] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a144,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3769] = {
+	.class_hid = BNXT_ULP_CLASS_HID_21b38,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3770] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28438,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3771] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33138,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3772] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3ba38,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3773] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20fe8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3774] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b8e8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3775] = {
+	.class_hid = BNXT_ULP_CLASS_HID_325e8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3776] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3aee8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3777] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25788,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3778] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c088,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3779] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34d88,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3780] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39b7c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3781] = {
+	.class_hid = BNXT_ULP_CLASS_HID_222d8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3782] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2afd8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3783] = {
+	.class_hid = BNXT_ULP_CLASS_HID_358d8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3784] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c5d8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3785] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23f8c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3786] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a88c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3787] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3558c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3788] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3de8c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3789] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2507c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3790] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dd7c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3791] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3467c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3792] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39430,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 0,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3793] = {
+	.class_hid = BNXT_ULP_CLASS_HID_223dc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3794] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2acdc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3795] = {
+	.class_hid = BNXT_ULP_CLASS_HID_359dc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3796] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c2dc,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3797] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20eec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3798] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2bbec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3799] = {
+	.class_hid = BNXT_ULP_CLASS_HID_324ec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3800] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d1ec,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3801] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20ba0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3802] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b4a0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3803] = {
+	.class_hid = BNXT_ULP_CLASS_HID_321a0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3804] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3aaa0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3805] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23c90,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3806] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a990,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3807] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35290,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3808] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3df90,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3809] = {
+	.class_hid = BNXT_ULP_CLASS_HID_24430,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3810] = {
+	.class_hid = BNXT_ULP_CLASS_HID_295e4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3811] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31ee4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3812] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38be4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3813] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25340,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3814] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2dc40,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3815] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34940,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3816] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39734,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3817] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22c34,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3818] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d934,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3819] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34234,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3820] = {
+	.class_hid = BNXT_ULP_CLASS_HID_393e8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3821] = {
+	.class_hid = BNXT_ULP_CLASS_HID_240e4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3822] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cde4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3823] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31bd8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3824] = {
+	.class_hid = BNXT_ULP_CLASS_HID_384d8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3825] = {
+	.class_hid = BNXT_ULP_CLASS_HID_23de0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3826] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a6e0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3827] = {
+	.class_hid = BNXT_ULP_CLASS_HID_353e0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3828] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3dce0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3829] = {
+	.class_hid = BNXT_ULP_CLASS_HID_20930,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3830] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2b230,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3831] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33f30,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3832] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a830,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3833] = {
+	.class_hid = BNXT_ULP_CLASS_HID_205e4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	},
+	[3834] = {
+	.class_hid = BNXT_ULP_CLASS_HID_28ee4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[51] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0013,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 6,
+	[3835] = {
+	.class_hid = BNXT_ULP_CLASS_HID_33be4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[52] = {
-	.class_hid = BNXT_ULP_CLASS_HID_001c,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 6,
+	[3836] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a4e4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[53] = {
-	.class_hid = BNXT_ULP_CLASS_HID_017b,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 6,
+	[3837] = {
+	.class_hid = BNXT_ULP_CLASS_HID_236d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[54] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0164,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3838] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2a3d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[55] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00c3,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3839] = {
+	.class_hid = BNXT_ULP_CLASS_HID_32cd4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[56] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00cc,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3840] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3d9d4,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[57] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01a5,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3841] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25e74,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[58] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0196,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3842] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2cb74,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[59] = {
-	.class_hid = BNXT_ULP_CLASS_HID_010d,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3843] = {
+	.class_hid = BNXT_ULP_CLASS_HID_31928,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[60] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00fe,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3844] = {
+	.class_hid = BNXT_ULP_CLASS_HID_38228,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[61] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0084,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3845] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22d84,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[62] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0046,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3846] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d684,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[63] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01ec,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3847] = {
+	.class_hid = BNXT_ULP_CLASS_HID_34384,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[64] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01ae,
-	.class_tid = 1,
-	.hdr_sig_id = 6,
-	.flow_sig_id = 7,
+	[3848] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39178,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[65] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00d3,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 7,
+	[3849] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22678,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[66] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00ac,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 7,
+	[3850] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2d378,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[67] = {
-	.class_hid = BNXT_ULP_CLASS_HID_000b,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 7,
+	[3851] = {
+	.class_hid = BNXT_ULP_CLASS_HID_35c78,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[68] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0004,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 7,
+	[3852] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3c978,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[69] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0163,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 7,
+	[3853] = {
+	.class_hid = BNXT_ULP_CLASS_HID_25b28,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[70] = {
-	.class_hid = BNXT_ULP_CLASS_HID_017c,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3854] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2c428,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[71] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00db,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3855] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3121c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[72] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00d4,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3856] = {
+	.class_hid = BNXT_ULP_CLASS_HID_39f1c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[73] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01bd,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3857] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3488,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[74] = {
-	.class_hid = BNXT_ULP_CLASS_HID_018e,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3858] = {
+	.class_hid = BNXT_ULP_CLASS_HID_3a44,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[75] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0115,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3859] = {
+	.class_hid = BNXT_ULP_CLASS_HID_5ed8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[76] = {
-	.class_hid = BNXT_ULP_CLASS_HID_00e6,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3860] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07e0,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[77] = {
-	.class_hid = BNXT_ULP_CLASS_HID_009c,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3861] = {
+	.class_hid = BNXT_ULP_CLASS_HID_2874,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[78] = {
-	.class_hid = BNXT_ULP_CLASS_HID_005e,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3862] = {
+	.class_hid = BNXT_ULP_CLASS_HID_591c,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[79] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01f4,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3863] = {
+	.class_hid = BNXT_ULP_CLASS_HID_1e24,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	},
-	[80] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01b6,
-	.class_tid = 1,
-	.hdr_sig_id = 7,
-	.flow_sig_id = 8,
+	[3864] = {
+	.class_hid = BNXT_ULP_CLASS_HID_22b8,
+	.class_tid = 2,
+	.hdr_sig_id = 11,
+	.flow_sig_id = 284,
+	.flow_pattern_id = 2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
-		BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	}
 };
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 324c288564..4a1faacfbe 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Tue Dec  8 14:57:13 2020 */
+/* date: Thu Dec 17 19:43:07 2020 */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_
@@ -12,43 +12,43 @@
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
 #define BNXT_ULP_GEN_TBL_MAX_SZ 6
-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 512
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 81
-#define BNXT_ULP_CLASS_HID_LOW_PRIME 4049
-#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
-#define BNXT_ULP_CLASS_HID_SHFTR 25
-#define BNXT_ULP_CLASS_HID_SHFTL 23
-#define BNXT_ULP_CLASS_HID_MASK 511
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 262144
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 3865
+#define BNXT_ULP_CLASS_HID_LOW_PRIME 5939
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7669
+#define BNXT_ULP_CLASS_HID_SHFTR 31
+#define BNXT_ULP_CLASS_HID_SHFTL 31
+#define BNXT_ULP_CLASS_HID_MASK 262143
 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 30
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
-#define BNXT_ULP_ACT_HID_HIGH_PRIME 6701
-#define BNXT_ULP_ACT_HID_SHFTR 24
-#define BNXT_ULP_ACT_HID_SHFTL 23
+#define BNXT_ULP_ACT_HID_HIGH_PRIME 3793
+#define BNXT_ULP_ACT_HID_SHFTR 27
+#define BNXT_ULP_ACT_HID_SHFTL 26
 #define BNXT_ULP_ACT_HID_MASK 2047
 #define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8
 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1
 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4
-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033
-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7
-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 257
-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 11
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 367
-#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 14
+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5593
+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8
+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 63
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 412
+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 17
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 503
+#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 16
 #define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7
 #define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38
 #define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192
 #define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10
 #define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341
 #define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10
-#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 3
-#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 11
+#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
+#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
 #define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 132
-#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 13
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 512
+#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 26
 #define ULP_STINGRAY_ACT_TMPL_LIST_SIZE 2
 #define ULP_STINGRAY_ACT_TBL_LIST_SIZE 4
 #define ULP_STINGRAY_ACT_KEY_INFO_LIST_SIZE 0
@@ -202,7 +202,9 @@ enum bnxt_ulp_cond_opc {
 	BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7,
 	BNXT_ULP_COND_OPC_RF_IS_SET = 8,
 	BNXT_ULP_COND_OPC_RF_NOT_SET = 9,
-	BNXT_ULP_COND_OPC_LAST = 10
+	BNXT_ULP_COND_OPC_FLOW_PAT_MATCH = 10,
+	BNXT_ULP_COND_OPC_ACT_PAT_MATCH = 11,
+	BNXT_ULP_COND_OPC_LAST = 12
 };
 
 enum bnxt_ulp_critical_resource {
@@ -231,9 +233,9 @@ enum bnxt_ulp_direction {
 };
 
 enum bnxt_ulp_fdb_opc {
-	BNXT_ULP_FDB_OPC_PUSH = 0,
-	BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE = 1,
-	BNXT_ULP_FDB_OPC_PUSH_REGFILE = 2,
+	BNXT_ULP_FDB_OPC_PUSH_FID = 0,
+	BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1,
+	BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE = 2,
 	BNXT_ULP_FDB_OPC_NOP = 3,
 	BNXT_ULP_FDB_OPC_LAST = 4
 };
@@ -252,7 +254,9 @@ enum bnxt_ulp_field_cond_src {
 	BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3,
 	BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4,
 	BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5,
-	BNXT_ULP_FIELD_COND_SRC_LAST = 6
+	BNXT_ULP_FIELD_COND_SRC_FLOW_PAT_MATCH = 6,
+	BNXT_ULP_FIELD_COND_SRC_ACT_PAT_MATCH = 7,
+	BNXT_ULP_FIELD_COND_SRC_LAST = 8
 };
 
 enum bnxt_ulp_field_opc {
@@ -266,19 +270,20 @@ enum bnxt_ulp_field_opc {
 
 enum bnxt_ulp_field_src {
 	BNXT_ULP_FIELD_SRC_ZERO = 0,
-	BNXT_ULP_FIELD_SRC_CONST = 1,
-	BNXT_ULP_FIELD_SRC_CF = 2,
-	BNXT_ULP_FIELD_SRC_RF = 3,
-	BNXT_ULP_FIELD_SRC_ACT_PROP = 4,
-	BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 5,
-	BNXT_ULP_FIELD_SRC_GLB_RF = 6,
-	BNXT_ULP_FIELD_SRC_HF = 7,
-	BNXT_ULP_FIELD_SRC_HDR_BIT = 8,
-	BNXT_ULP_FIELD_SRC_ACT_BIT = 9,
-	BNXT_ULP_FIELD_SRC_FIELD_BIT = 10,
-	BNXT_ULP_FIELD_SRC_SKIP = 11,
-	BNXT_ULP_FIELD_SRC_REJECT = 12,
-	BNXT_ULP_FIELD_SRC_LAST = 13
+	BNXT_ULP_FIELD_SRC_ONES = 1,
+	BNXT_ULP_FIELD_SRC_CONST = 2,
+	BNXT_ULP_FIELD_SRC_CF = 3,
+	BNXT_ULP_FIELD_SRC_RF = 4,
+	BNXT_ULP_FIELD_SRC_ACT_PROP = 5,
+	BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 6,
+	BNXT_ULP_FIELD_SRC_GLB_RF = 7,
+	BNXT_ULP_FIELD_SRC_HF = 8,
+	BNXT_ULP_FIELD_SRC_HDR_BIT = 9,
+	BNXT_ULP_FIELD_SRC_ACT_BIT = 10,
+	BNXT_ULP_FIELD_SRC_FIELD_BIT = 11,
+	BNXT_ULP_FIELD_SRC_SKIP = 12,
+	BNXT_ULP_FIELD_SRC_REJECT = 13,
+	BNXT_ULP_FIELD_SRC_LAST = 14
 };
 
 enum bnxt_ulp_generic_tbl_opc {
@@ -429,7 +434,7 @@ enum bnxt_ulp_resource_func {
 	BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,
 	BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86,
 	BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87,
-	BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE = 0x88
+	BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE = 0x88
 };
 
 enum bnxt_ulp_resource_sub_type {
@@ -973,126 +978,3965 @@ enum ulp_sr_sym {
 };
 
 enum bnxt_ulp_class_hid {
-	BNXT_ULP_CLASS_HID_005c = 0x005c,
-	BNXT_ULP_CLASS_HID_0003 = 0x0003,
-	BNXT_ULP_CLASS_HID_0132 = 0x0132,
-	BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
-	BNXT_ULP_CLASS_HID_0044 = 0x0044,
-	BNXT_ULP_CLASS_HID_001b = 0x001b,
-	BNXT_ULP_CLASS_HID_012a = 0x012a,
-	BNXT_ULP_CLASS_HID_00f9 = 0x00f9,
-	BNXT_ULP_CLASS_HID_018d = 0x018d,
-	BNXT_ULP_CLASS_HID_00a7 = 0x00a7,
-	BNXT_ULP_CLASS_HID_006f = 0x006f,
-	BNXT_ULP_CLASS_HID_0181 = 0x0181,
-	BNXT_ULP_CLASS_HID_0195 = 0x0195,
-	BNXT_ULP_CLASS_HID_00bf = 0x00bf,
-	BNXT_ULP_CLASS_HID_0077 = 0x0077,
-	BNXT_ULP_CLASS_HID_0199 = 0x0199,
-	BNXT_ULP_CLASS_HID_009a = 0x009a,
-	BNXT_ULP_CLASS_HID_0192 = 0x0192,
-	BNXT_ULP_CLASS_HID_01e2 = 0x01e2,
-	BNXT_ULP_CLASS_HID_00fa = 0x00fa,
-	BNXT_ULP_CLASS_HID_0165 = 0x0165,
-	BNXT_ULP_CLASS_HID_0042 = 0x0042,
-	BNXT_ULP_CLASS_HID_00cd = 0x00cd,
-	BNXT_ULP_CLASS_HID_01aa = 0x01aa,
-	BNXT_ULP_CLASS_HID_0178 = 0x0178,
-	BNXT_ULP_CLASS_HID_0070 = 0x0070,
-	BNXT_ULP_CLASS_HID_00f3 = 0x00f3,
-	BNXT_ULP_CLASS_HID_01d8 = 0x01d8,
-	BNXT_ULP_CLASS_HID_005b = 0x005b,
-	BNXT_ULP_CLASS_HID_0153 = 0x0153,
-	BNXT_ULP_CLASS_HID_01a3 = 0x01a3,
-	BNXT_ULP_CLASS_HID_00bb = 0x00bb,
-	BNXT_ULP_CLASS_HID_0082 = 0x0082,
-	BNXT_ULP_CLASS_HID_018a = 0x018a,
-	BNXT_ULP_CLASS_HID_01fa = 0x01fa,
-	BNXT_ULP_CLASS_HID_00e2 = 0x00e2,
-	BNXT_ULP_CLASS_HID_017d = 0x017d,
-	BNXT_ULP_CLASS_HID_005a = 0x005a,
-	BNXT_ULP_CLASS_HID_00d5 = 0x00d5,
-	BNXT_ULP_CLASS_HID_01b2 = 0x01b2,
-	BNXT_ULP_CLASS_HID_0160 = 0x0160,
-	BNXT_ULP_CLASS_HID_0068 = 0x0068,
-	BNXT_ULP_CLASS_HID_00eb = 0x00eb,
-	BNXT_ULP_CLASS_HID_01c0 = 0x01c0,
-	BNXT_ULP_CLASS_HID_0043 = 0x0043,
-	BNXT_ULP_CLASS_HID_014b = 0x014b,
-	BNXT_ULP_CLASS_HID_01bb = 0x01bb,
-	BNXT_ULP_CLASS_HID_00a3 = 0x00a3,
-	BNXT_ULP_CLASS_HID_00cb = 0x00cb,
-	BNXT_ULP_CLASS_HID_00b4 = 0x00b4,
-	BNXT_ULP_CLASS_HID_0013 = 0x0013,
-	BNXT_ULP_CLASS_HID_001c = 0x001c,
-	BNXT_ULP_CLASS_HID_017b = 0x017b,
-	BNXT_ULP_CLASS_HID_0164 = 0x0164,
-	BNXT_ULP_CLASS_HID_00c3 = 0x00c3,
-	BNXT_ULP_CLASS_HID_00cc = 0x00cc,
-	BNXT_ULP_CLASS_HID_01a5 = 0x01a5,
-	BNXT_ULP_CLASS_HID_0196 = 0x0196,
-	BNXT_ULP_CLASS_HID_010d = 0x010d,
-	BNXT_ULP_CLASS_HID_00fe = 0x00fe,
-	BNXT_ULP_CLASS_HID_0084 = 0x0084,
-	BNXT_ULP_CLASS_HID_0046 = 0x0046,
-	BNXT_ULP_CLASS_HID_01ec = 0x01ec,
-	BNXT_ULP_CLASS_HID_01ae = 0x01ae,
-	BNXT_ULP_CLASS_HID_00d3 = 0x00d3,
-	BNXT_ULP_CLASS_HID_00ac = 0x00ac,
-	BNXT_ULP_CLASS_HID_000b = 0x000b,
-	BNXT_ULP_CLASS_HID_0004 = 0x0004,
-	BNXT_ULP_CLASS_HID_0163 = 0x0163,
-	BNXT_ULP_CLASS_HID_017c = 0x017c,
-	BNXT_ULP_CLASS_HID_00db = 0x00db,
-	BNXT_ULP_CLASS_HID_00d4 = 0x00d4,
-	BNXT_ULP_CLASS_HID_01bd = 0x01bd,
-	BNXT_ULP_CLASS_HID_018e = 0x018e,
-	BNXT_ULP_CLASS_HID_0115 = 0x0115,
+	BNXT_ULP_CLASS_HID_26d1 = 0x26d1,
+	BNXT_ULP_CLASS_HID_0071 = 0x0071,
+	BNXT_ULP_CLASS_HID_53a5 = 0x53a5,
+	BNXT_ULP_CLASS_HID_1d49 = 0x1d49,
+	BNXT_ULP_CLASS_HID_2095 = 0x2095,
+	BNXT_ULP_CLASS_HID_5701 = 0x5701,
+	BNXT_ULP_CLASS_HID_4d79 = 0x4d79,
+	BNXT_ULP_CLASS_HID_170d = 0x170d,
+	BNXT_ULP_CLASS_HID_1a69 = 0x1a69,
+	BNXT_ULP_CLASS_HID_50c5 = 0x50c5,
+	BNXT_ULP_CLASS_HID_473d = 0x473d,
+	BNXT_ULP_CLASS_HID_10c1 = 0x10c1,
+	BNXT_ULP_CLASS_HID_142d = 0x142d,
+	BNXT_ULP_CLASS_HID_4a99 = 0x4a99,
+	BNXT_ULP_CLASS_HID_40f1 = 0x40f1,
+	BNXT_ULP_CLASS_HID_0a85 = 0x0a85,
+	BNXT_ULP_CLASS_HID_0179 = 0x0179,
+	BNXT_ULP_CLASS_HID_37d5 = 0x37d5,
+	BNXT_ULP_CLASS_HID_2e4d = 0x2e4d,
+	BNXT_ULP_CLASS_HID_54ad = 0x54ad,
+	BNXT_ULP_CLASS_HID_5809 = 0x5809,
+	BNXT_ULP_CLASS_HID_31a9 = 0x31a9,
+	BNXT_ULP_CLASS_HID_2801 = 0x2801,
+	BNXT_ULP_CLASS_HID_4e61 = 0x4e61,
+	BNXT_ULP_CLASS_HID_2561 = 0x2561,
+	BNXT_ULP_CLASS_HID_2bad = 0x2bad,
+	BNXT_ULP_CLASS_HID_26f1 = 0x26f1,
+	BNXT_ULP_CLASS_HID_13cf1 = 0x13cf1,
+	BNXT_ULP_CLASS_HID_252f1 = 0x252f1,
+	BNXT_ULP_CLASS_HID_30c25 = 0x30c25,
+	BNXT_ULP_CLASS_HID_0051 = 0x0051,
+	BNXT_ULP_CLASS_HID_11651 = 0x11651,
+	BNXT_ULP_CLASS_HID_22c51 = 0x22c51,
+	BNXT_ULP_CLASS_HID_34251 = 0x34251,
+	BNXT_ULP_CLASS_HID_5385 = 0x5385,
+	BNXT_ULP_CLASS_HID_10cc9 = 0x10cc9,
+	BNXT_ULP_CLASS_HID_222c9 = 0x222c9,
+	BNXT_ULP_CLASS_HID_338c9 = 0x338c9,
+	BNXT_ULP_CLASS_HID_1d69 = 0x1d69,
+	BNXT_ULP_CLASS_HID_13369 = 0x13369,
+	BNXT_ULP_CLASS_HID_24969 = 0x24969,
+	BNXT_ULP_CLASS_HID_3025d = 0x3025d,
+	BNXT_ULP_CLASS_HID_20b5 = 0x20b5,
+	BNXT_ULP_CLASS_HID_136b5 = 0x136b5,
+	BNXT_ULP_CLASS_HID_24cb5 = 0x24cb5,
+	BNXT_ULP_CLASS_HID_305f9 = 0x305f9,
+	BNXT_ULP_CLASS_HID_5721 = 0x5721,
+	BNXT_ULP_CLASS_HID_11015 = 0x11015,
+	BNXT_ULP_CLASS_HID_22615 = 0x22615,
+	BNXT_ULP_CLASS_HID_33c15 = 0x33c15,
+	BNXT_ULP_CLASS_HID_4d59 = 0x4d59,
+	BNXT_ULP_CLASS_HID_1068d = 0x1068d,
+	BNXT_ULP_CLASS_HID_21c8d = 0x21c8d,
+	BNXT_ULP_CLASS_HID_3328d = 0x3328d,
+	BNXT_ULP_CLASS_HID_172d = 0x172d,
+	BNXT_ULP_CLASS_HID_12d2d = 0x12d2d,
+	BNXT_ULP_CLASS_HID_2432d = 0x2432d,
+	BNXT_ULP_CLASS_HID_3592d = 0x3592d,
+	BNXT_ULP_CLASS_HID_1a49 = 0x1a49,
+	BNXT_ULP_CLASS_HID_13049 = 0x13049,
+	BNXT_ULP_CLASS_HID_24649 = 0x24649,
+	BNXT_ULP_CLASS_HID_35c49 = 0x35c49,
+	BNXT_ULP_CLASS_HID_50e5 = 0x50e5,
+	BNXT_ULP_CLASS_HID_10a29 = 0x10a29,
+	BNXT_ULP_CLASS_HID_22029 = 0x22029,
+	BNXT_ULP_CLASS_HID_33629 = 0x33629,
+	BNXT_ULP_CLASS_HID_471d = 0x471d,
+	BNXT_ULP_CLASS_HID_10041 = 0x10041,
+	BNXT_ULP_CLASS_HID_21641 = 0x21641,
+	BNXT_ULP_CLASS_HID_32c41 = 0x32c41,
+	BNXT_ULP_CLASS_HID_10e1 = 0x10e1,
+	BNXT_ULP_CLASS_HID_126e1 = 0x126e1,
+	BNXT_ULP_CLASS_HID_23ce1 = 0x23ce1,
+	BNXT_ULP_CLASS_HID_352e1 = 0x352e1,
+	BNXT_ULP_CLASS_HID_140d = 0x140d,
+	BNXT_ULP_CLASS_HID_12a0d = 0x12a0d,
+	BNXT_ULP_CLASS_HID_2400d = 0x2400d,
+	BNXT_ULP_CLASS_HID_3560d = 0x3560d,
+	BNXT_ULP_CLASS_HID_4ab9 = 0x4ab9,
+	BNXT_ULP_CLASS_HID_103ed = 0x103ed,
+	BNXT_ULP_CLASS_HID_219ed = 0x219ed,
+	BNXT_ULP_CLASS_HID_32fed = 0x32fed,
+	BNXT_ULP_CLASS_HID_40d1 = 0x40d1,
+	BNXT_ULP_CLASS_HID_156d1 = 0x156d1,
+	BNXT_ULP_CLASS_HID_21005 = 0x21005,
+	BNXT_ULP_CLASS_HID_32605 = 0x32605,
+	BNXT_ULP_CLASS_HID_0aa5 = 0x0aa5,
+	BNXT_ULP_CLASS_HID_120a5 = 0x120a5,
+	BNXT_ULP_CLASS_HID_236a5 = 0x236a5,
+	BNXT_ULP_CLASS_HID_34ca5 = 0x34ca5,
+	BNXT_ULP_CLASS_HID_0159 = 0x0159,
+	BNXT_ULP_CLASS_HID_11759 = 0x11759,
+	BNXT_ULP_CLASS_HID_22d59 = 0x22d59,
+	BNXT_ULP_CLASS_HID_34359 = 0x34359,
+	BNXT_ULP_CLASS_HID_37f5 = 0x37f5,
+	BNXT_ULP_CLASS_HID_14df5 = 0x14df5,
+	BNXT_ULP_CLASS_HID_20739 = 0x20739,
+	BNXT_ULP_CLASS_HID_31d39 = 0x31d39,
+	BNXT_ULP_CLASS_HID_2e6d = 0x2e6d,
+	BNXT_ULP_CLASS_HID_1446d = 0x1446d,
+	BNXT_ULP_CLASS_HID_25a6d = 0x25a6d,
+	BNXT_ULP_CLASS_HID_31351 = 0x31351,
+	BNXT_ULP_CLASS_HID_548d = 0x548d,
+	BNXT_ULP_CLASS_HID_10df1 = 0x10df1,
+	BNXT_ULP_CLASS_HID_223f1 = 0x223f1,
+	BNXT_ULP_CLASS_HID_339f1 = 0x339f1,
+	BNXT_ULP_CLASS_HID_5829 = 0x5829,
+	BNXT_ULP_CLASS_HID_1111d = 0x1111d,
+	BNXT_ULP_CLASS_HID_2271d = 0x2271d,
+	BNXT_ULP_CLASS_HID_33d1d = 0x33d1d,
+	BNXT_ULP_CLASS_HID_3189 = 0x3189,
+	BNXT_ULP_CLASS_HID_14789 = 0x14789,
+	BNXT_ULP_CLASS_HID_200fd = 0x200fd,
+	BNXT_ULP_CLASS_HID_316fd = 0x316fd,
+	BNXT_ULP_CLASS_HID_2821 = 0x2821,
+	BNXT_ULP_CLASS_HID_13e21 = 0x13e21,
+	BNXT_ULP_CLASS_HID_25421 = 0x25421,
+	BNXT_ULP_CLASS_HID_30d15 = 0x30d15,
+	BNXT_ULP_CLASS_HID_4e41 = 0x4e41,
+	BNXT_ULP_CLASS_HID_107b5 = 0x107b5,
+	BNXT_ULP_CLASS_HID_21db5 = 0x21db5,
+	BNXT_ULP_CLASS_HID_333b5 = 0x333b5,
+	BNXT_ULP_CLASS_HID_2541 = 0x2541,
+	BNXT_ULP_CLASS_HID_2b8d = 0x2b8d,
+	BNXT_ULP_CLASS_HID_2691 = 0x2691,
+	BNXT_ULP_CLASS_HID_13c91 = 0x13c91,
+	BNXT_ULP_CLASS_HID_25291 = 0x25291,
+	BNXT_ULP_CLASS_HID_30c45 = 0x30c45,
+	BNXT_ULP_CLASS_HID_0031 = 0x0031,
+	BNXT_ULP_CLASS_HID_11631 = 0x11631,
+	BNXT_ULP_CLASS_HID_22c31 = 0x22c31,
+	BNXT_ULP_CLASS_HID_34231 = 0x34231,
+	BNXT_ULP_CLASS_HID_53e5 = 0x53e5,
+	BNXT_ULP_CLASS_HID_10ca9 = 0x10ca9,
+	BNXT_ULP_CLASS_HID_222a9 = 0x222a9,
+	BNXT_ULP_CLASS_HID_338a9 = 0x338a9,
+	BNXT_ULP_CLASS_HID_1d09 = 0x1d09,
+	BNXT_ULP_CLASS_HID_13309 = 0x13309,
+	BNXT_ULP_CLASS_HID_24909 = 0x24909,
+	BNXT_ULP_CLASS_HID_3023d = 0x3023d,
+	BNXT_ULP_CLASS_HID_20d5 = 0x20d5,
+	BNXT_ULP_CLASS_HID_136d5 = 0x136d5,
+	BNXT_ULP_CLASS_HID_24cd5 = 0x24cd5,
+	BNXT_ULP_CLASS_HID_30599 = 0x30599,
+	BNXT_ULP_CLASS_HID_5741 = 0x5741,
+	BNXT_ULP_CLASS_HID_11075 = 0x11075,
+	BNXT_ULP_CLASS_HID_22675 = 0x22675,
+	BNXT_ULP_CLASS_HID_33c75 = 0x33c75,
+	BNXT_ULP_CLASS_HID_4d39 = 0x4d39,
+	BNXT_ULP_CLASS_HID_106ed = 0x106ed,
+	BNXT_ULP_CLASS_HID_21ced = 0x21ced,
+	BNXT_ULP_CLASS_HID_332ed = 0x332ed,
+	BNXT_ULP_CLASS_HID_174d = 0x174d,
+	BNXT_ULP_CLASS_HID_12d4d = 0x12d4d,
+	BNXT_ULP_CLASS_HID_2434d = 0x2434d,
+	BNXT_ULP_CLASS_HID_3594d = 0x3594d,
+	BNXT_ULP_CLASS_HID_1a29 = 0x1a29,
+	BNXT_ULP_CLASS_HID_13029 = 0x13029,
+	BNXT_ULP_CLASS_HID_24629 = 0x24629,
+	BNXT_ULP_CLASS_HID_35c29 = 0x35c29,
+	BNXT_ULP_CLASS_HID_5085 = 0x5085,
+	BNXT_ULP_CLASS_HID_10a49 = 0x10a49,
+	BNXT_ULP_CLASS_HID_22049 = 0x22049,
+	BNXT_ULP_CLASS_HID_33649 = 0x33649,
+	BNXT_ULP_CLASS_HID_477d = 0x477d,
+	BNXT_ULP_CLASS_HID_10021 = 0x10021,
+	BNXT_ULP_CLASS_HID_21621 = 0x21621,
+	BNXT_ULP_CLASS_HID_32c21 = 0x32c21,
+	BNXT_ULP_CLASS_HID_1081 = 0x1081,
+	BNXT_ULP_CLASS_HID_12681 = 0x12681,
+	BNXT_ULP_CLASS_HID_23c81 = 0x23c81,
+	BNXT_ULP_CLASS_HID_35281 = 0x35281,
+	BNXT_ULP_CLASS_HID_146d = 0x146d,
+	BNXT_ULP_CLASS_HID_12a6d = 0x12a6d,
+	BNXT_ULP_CLASS_HID_2406d = 0x2406d,
+	BNXT_ULP_CLASS_HID_3566d = 0x3566d,
+	BNXT_ULP_CLASS_HID_4ad9 = 0x4ad9,
+	BNXT_ULP_CLASS_HID_1038d = 0x1038d,
+	BNXT_ULP_CLASS_HID_2198d = 0x2198d,
+	BNXT_ULP_CLASS_HID_32f8d = 0x32f8d,
+	BNXT_ULP_CLASS_HID_40b1 = 0x40b1,
+	BNXT_ULP_CLASS_HID_156b1 = 0x156b1,
+	BNXT_ULP_CLASS_HID_21065 = 0x21065,
+	BNXT_ULP_CLASS_HID_32665 = 0x32665,
+	BNXT_ULP_CLASS_HID_0ac5 = 0x0ac5,
+	BNXT_ULP_CLASS_HID_120c5 = 0x120c5,
+	BNXT_ULP_CLASS_HID_236c5 = 0x236c5,
+	BNXT_ULP_CLASS_HID_34cc5 = 0x34cc5,
+	BNXT_ULP_CLASS_HID_0139 = 0x0139,
+	BNXT_ULP_CLASS_HID_11739 = 0x11739,
+	BNXT_ULP_CLASS_HID_22d39 = 0x22d39,
+	BNXT_ULP_CLASS_HID_34339 = 0x34339,
+	BNXT_ULP_CLASS_HID_3795 = 0x3795,
+	BNXT_ULP_CLASS_HID_14d95 = 0x14d95,
+	BNXT_ULP_CLASS_HID_20759 = 0x20759,
+	BNXT_ULP_CLASS_HID_31d59 = 0x31d59,
+	BNXT_ULP_CLASS_HID_2e0d = 0x2e0d,
+	BNXT_ULP_CLASS_HID_1440d = 0x1440d,
+	BNXT_ULP_CLASS_HID_25a0d = 0x25a0d,
+	BNXT_ULP_CLASS_HID_31331 = 0x31331,
+	BNXT_ULP_CLASS_HID_54ed = 0x54ed,
+	BNXT_ULP_CLASS_HID_10d91 = 0x10d91,
+	BNXT_ULP_CLASS_HID_22391 = 0x22391,
+	BNXT_ULP_CLASS_HID_33991 = 0x33991,
+	BNXT_ULP_CLASS_HID_5849 = 0x5849,
+	BNXT_ULP_CLASS_HID_1117d = 0x1117d,
+	BNXT_ULP_CLASS_HID_2277d = 0x2277d,
+	BNXT_ULP_CLASS_HID_33d7d = 0x33d7d,
+	BNXT_ULP_CLASS_HID_31e9 = 0x31e9,
+	BNXT_ULP_CLASS_HID_147e9 = 0x147e9,
+	BNXT_ULP_CLASS_HID_2009d = 0x2009d,
+	BNXT_ULP_CLASS_HID_3169d = 0x3169d,
+	BNXT_ULP_CLASS_HID_2841 = 0x2841,
+	BNXT_ULP_CLASS_HID_13e41 = 0x13e41,
+	BNXT_ULP_CLASS_HID_25441 = 0x25441,
+	BNXT_ULP_CLASS_HID_30d75 = 0x30d75,
+	BNXT_ULP_CLASS_HID_4e21 = 0x4e21,
+	BNXT_ULP_CLASS_HID_107d5 = 0x107d5,
+	BNXT_ULP_CLASS_HID_21dd5 = 0x21dd5,
+	BNXT_ULP_CLASS_HID_333d5 = 0x333d5,
+	BNXT_ULP_CLASS_HID_2521 = 0x2521,
+	BNXT_ULP_CLASS_HID_2bed = 0x2bed,
+	BNXT_ULP_CLASS_HID_1865 = 0x1865,
+	BNXT_ULP_CLASS_HID_389d = 0x389d,
+	BNXT_ULP_CLASS_HID_123d = 0x123d,
+	BNXT_ULP_CLASS_HID_4ef1 = 0x4ef1,
+	BNXT_ULP_CLASS_HID_1229 = 0x1229,
+	BNXT_ULP_CLASS_HID_3241 = 0x3241,
+	BNXT_ULP_CLASS_HID_0be1 = 0x0be1,
+	BNXT_ULP_CLASS_HID_48b5 = 0x48b5,
+	BNXT_ULP_CLASS_HID_0bed = 0x0bed,
+	BNXT_ULP_CLASS_HID_2c05 = 0x2c05,
+	BNXT_ULP_CLASS_HID_05a5 = 0x05a5,
+	BNXT_ULP_CLASS_HID_4279 = 0x4279,
+	BNXT_ULP_CLASS_HID_05d1 = 0x05d1,
+	BNXT_ULP_CLASS_HID_25c9 = 0x25c9,
+	BNXT_ULP_CLASS_HID_5c55 = 0x5c55,
+	BNXT_ULP_CLASS_HID_3c3d = 0x3c3d,
+	BNXT_ULP_CLASS_HID_4fc9 = 0x4fc9,
+	BNXT_ULP_CLASS_HID_1335 = 0x1335,
+	BNXT_ULP_CLASS_HID_4981 = 0x4981,
+	BNXT_ULP_CLASS_HID_2969 = 0x2969,
+	BNXT_ULP_CLASS_HID_498d = 0x498d,
+	BNXT_ULP_CLASS_HID_0cf9 = 0x0cf9,
+	BNXT_ULP_CLASS_HID_4345 = 0x4345,
+	BNXT_ULP_CLASS_HID_232d = 0x232d,
+	BNXT_ULP_CLASS_HID_2579 = 0x2579,
+	BNXT_ULP_CLASS_HID_2bb5 = 0x2bb5,
+	BNXT_ULP_CLASS_HID_1845 = 0x1845,
+	BNXT_ULP_CLASS_HID_1399 = 0x1399,
+	BNXT_ULP_CLASS_HID_0eed = 0x0eed,
+	BNXT_ULP_CLASS_HID_0a21 = 0x0a21,
+	BNXT_ULP_CLASS_HID_38bd = 0x38bd,
+	BNXT_ULP_CLASS_HID_33f1 = 0x33f1,
+	BNXT_ULP_CLASS_HID_2ec5 = 0x2ec5,
+	BNXT_ULP_CLASS_HID_2a19 = 0x2a19,
+	BNXT_ULP_CLASS_HID_121d = 0x121d,
+	BNXT_ULP_CLASS_HID_0d51 = 0x0d51,
+	BNXT_ULP_CLASS_HID_08a5 = 0x08a5,
+	BNXT_ULP_CLASS_HID_03f9 = 0x03f9,
+	BNXT_ULP_CLASS_HID_4ed1 = 0x4ed1,
+	BNXT_ULP_CLASS_HID_4a25 = 0x4a25,
+	BNXT_ULP_CLASS_HID_4579 = 0x4579,
+	BNXT_ULP_CLASS_HID_404d = 0x404d,
+	BNXT_ULP_CLASS_HID_1209 = 0x1209,
+	BNXT_ULP_CLASS_HID_0d5d = 0x0d5d,
+	BNXT_ULP_CLASS_HID_0891 = 0x0891,
+	BNXT_ULP_CLASS_HID_03e5 = 0x03e5,
+	BNXT_ULP_CLASS_HID_3261 = 0x3261,
+	BNXT_ULP_CLASS_HID_2db5 = 0x2db5,
+	BNXT_ULP_CLASS_HID_2889 = 0x2889,
+	BNXT_ULP_CLASS_HID_23dd = 0x23dd,
+	BNXT_ULP_CLASS_HID_0bc1 = 0x0bc1,
+	BNXT_ULP_CLASS_HID_0715 = 0x0715,
+	BNXT_ULP_CLASS_HID_0269 = 0x0269,
+	BNXT_ULP_CLASS_HID_5a69 = 0x5a69,
+	BNXT_ULP_CLASS_HID_4895 = 0x4895,
+	BNXT_ULP_CLASS_HID_43e9 = 0x43e9,
+	BNXT_ULP_CLASS_HID_3f3d = 0x3f3d,
+	BNXT_ULP_CLASS_HID_3a71 = 0x3a71,
+	BNXT_ULP_CLASS_HID_0bcd = 0x0bcd,
+	BNXT_ULP_CLASS_HID_0701 = 0x0701,
+	BNXT_ULP_CLASS_HID_0255 = 0x0255,
+	BNXT_ULP_CLASS_HID_5a55 = 0x5a55,
+	BNXT_ULP_CLASS_HID_2c25 = 0x2c25,
+	BNXT_ULP_CLASS_HID_2779 = 0x2779,
+	BNXT_ULP_CLASS_HID_224d = 0x224d,
+	BNXT_ULP_CLASS_HID_1d81 = 0x1d81,
+	BNXT_ULP_CLASS_HID_0585 = 0x0585,
+	BNXT_ULP_CLASS_HID_00d9 = 0x00d9,
+	BNXT_ULP_CLASS_HID_58d9 = 0x58d9,
+	BNXT_ULP_CLASS_HID_542d = 0x542d,
+	BNXT_ULP_CLASS_HID_4259 = 0x4259,
+	BNXT_ULP_CLASS_HID_3dad = 0x3dad,
+	BNXT_ULP_CLASS_HID_38e1 = 0x38e1,
+	BNXT_ULP_CLASS_HID_3435 = 0x3435,
+	BNXT_ULP_CLASS_HID_05f1 = 0x05f1,
+	BNXT_ULP_CLASS_HID_00c5 = 0x00c5,
+	BNXT_ULP_CLASS_HID_58c5 = 0x58c5,
+	BNXT_ULP_CLASS_HID_5419 = 0x5419,
+	BNXT_ULP_CLASS_HID_25e9 = 0x25e9,
+	BNXT_ULP_CLASS_HID_213d = 0x213d,
+	BNXT_ULP_CLASS_HID_1c71 = 0x1c71,
+	BNXT_ULP_CLASS_HID_1745 = 0x1745,
+	BNXT_ULP_CLASS_HID_5c75 = 0x5c75,
+	BNXT_ULP_CLASS_HID_5749 = 0x5749,
+	BNXT_ULP_CLASS_HID_529d = 0x529d,
+	BNXT_ULP_CLASS_HID_4dd1 = 0x4dd1,
+	BNXT_ULP_CLASS_HID_3c1d = 0x3c1d,
+	BNXT_ULP_CLASS_HID_3751 = 0x3751,
+	BNXT_ULP_CLASS_HID_32a5 = 0x32a5,
+	BNXT_ULP_CLASS_HID_2df9 = 0x2df9,
+	BNXT_ULP_CLASS_HID_4fe9 = 0x4fe9,
+	BNXT_ULP_CLASS_HID_4b3d = 0x4b3d,
+	BNXT_ULP_CLASS_HID_4671 = 0x4671,
+	BNXT_ULP_CLASS_HID_4145 = 0x4145,
+	BNXT_ULP_CLASS_HID_1315 = 0x1315,
+	BNXT_ULP_CLASS_HID_0e69 = 0x0e69,
+	BNXT_ULP_CLASS_HID_09bd = 0x09bd,
+	BNXT_ULP_CLASS_HID_04f1 = 0x04f1,
+	BNXT_ULP_CLASS_HID_49a1 = 0x49a1,
+	BNXT_ULP_CLASS_HID_44f5 = 0x44f5,
+	BNXT_ULP_CLASS_HID_3fc9 = 0x3fc9,
+	BNXT_ULP_CLASS_HID_3b1d = 0x3b1d,
+	BNXT_ULP_CLASS_HID_2949 = 0x2949,
+	BNXT_ULP_CLASS_HID_249d = 0x249d,
+	BNXT_ULP_CLASS_HID_1fd1 = 0x1fd1,
+	BNXT_ULP_CLASS_HID_1b25 = 0x1b25,
+	BNXT_ULP_CLASS_HID_49ad = 0x49ad,
+	BNXT_ULP_CLASS_HID_44e1 = 0x44e1,
+	BNXT_ULP_CLASS_HID_4035 = 0x4035,
+	BNXT_ULP_CLASS_HID_3b09 = 0x3b09,
+	BNXT_ULP_CLASS_HID_0cd9 = 0x0cd9,
+	BNXT_ULP_CLASS_HID_082d = 0x082d,
+	BNXT_ULP_CLASS_HID_0361 = 0x0361,
+	BNXT_ULP_CLASS_HID_5b61 = 0x5b61,
+	BNXT_ULP_CLASS_HID_4365 = 0x4365,
+	BNXT_ULP_CLASS_HID_3eb9 = 0x3eb9,
+	BNXT_ULP_CLASS_HID_398d = 0x398d,
+	BNXT_ULP_CLASS_HID_34c1 = 0x34c1,
+	BNXT_ULP_CLASS_HID_230d = 0x230d,
+	BNXT_ULP_CLASS_HID_1e41 = 0x1e41,
+	BNXT_ULP_CLASS_HID_1995 = 0x1995,
+	BNXT_ULP_CLASS_HID_14e9 = 0x14e9,
+	BNXT_ULP_CLASS_HID_2559 = 0x2559,
+	BNXT_ULP_CLASS_HID_2b95 = 0x2b95,
+	BNXT_ULP_CLASS_HID_1825 = 0x1825,
+	BNXT_ULP_CLASS_HID_13f9 = 0x13f9,
+	BNXT_ULP_CLASS_HID_0e8d = 0x0e8d,
+	BNXT_ULP_CLASS_HID_0a41 = 0x0a41,
+	BNXT_ULP_CLASS_HID_38dd = 0x38dd,
+	BNXT_ULP_CLASS_HID_3391 = 0x3391,
+	BNXT_ULP_CLASS_HID_2ea5 = 0x2ea5,
+	BNXT_ULP_CLASS_HID_2a79 = 0x2a79,
+	BNXT_ULP_CLASS_HID_127d = 0x127d,
+	BNXT_ULP_CLASS_HID_0d31 = 0x0d31,
+	BNXT_ULP_CLASS_HID_08c5 = 0x08c5,
+	BNXT_ULP_CLASS_HID_0399 = 0x0399,
+	BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1,
+	BNXT_ULP_CLASS_HID_4a45 = 0x4a45,
+	BNXT_ULP_CLASS_HID_4519 = 0x4519,
+	BNXT_ULP_CLASS_HID_402d = 0x402d,
+	BNXT_ULP_CLASS_HID_1269 = 0x1269,
+	BNXT_ULP_CLASS_HID_0d3d = 0x0d3d,
+	BNXT_ULP_CLASS_HID_08f1 = 0x08f1,
+	BNXT_ULP_CLASS_HID_0385 = 0x0385,
+	BNXT_ULP_CLASS_HID_3201 = 0x3201,
+	BNXT_ULP_CLASS_HID_2dd5 = 0x2dd5,
+	BNXT_ULP_CLASS_HID_28e9 = 0x28e9,
+	BNXT_ULP_CLASS_HID_23bd = 0x23bd,
+	BNXT_ULP_CLASS_HID_0ba1 = 0x0ba1,
+	BNXT_ULP_CLASS_HID_0775 = 0x0775,
+	BNXT_ULP_CLASS_HID_0209 = 0x0209,
+	BNXT_ULP_CLASS_HID_5a09 = 0x5a09,
+	BNXT_ULP_CLASS_HID_48f5 = 0x48f5,
+	BNXT_ULP_CLASS_HID_4389 = 0x4389,
+	BNXT_ULP_CLASS_HID_3f5d = 0x3f5d,
+	BNXT_ULP_CLASS_HID_3a11 = 0x3a11,
+	BNXT_ULP_CLASS_HID_0bad = 0x0bad,
+	BNXT_ULP_CLASS_HID_0761 = 0x0761,
+	BNXT_ULP_CLASS_HID_0235 = 0x0235,
+	BNXT_ULP_CLASS_HID_5a35 = 0x5a35,
+	BNXT_ULP_CLASS_HID_2c45 = 0x2c45,
+	BNXT_ULP_CLASS_HID_2719 = 0x2719,
+	BNXT_ULP_CLASS_HID_222d = 0x222d,
+	BNXT_ULP_CLASS_HID_1de1 = 0x1de1,
+	BNXT_ULP_CLASS_HID_05e5 = 0x05e5,
+	BNXT_ULP_CLASS_HID_00b9 = 0x00b9,
+	BNXT_ULP_CLASS_HID_58b9 = 0x58b9,
+	BNXT_ULP_CLASS_HID_544d = 0x544d,
+	BNXT_ULP_CLASS_HID_4239 = 0x4239,
+	BNXT_ULP_CLASS_HID_3dcd = 0x3dcd,
+	BNXT_ULP_CLASS_HID_3881 = 0x3881,
+	BNXT_ULP_CLASS_HID_3455 = 0x3455,
+	BNXT_ULP_CLASS_HID_0591 = 0x0591,
+	BNXT_ULP_CLASS_HID_00a5 = 0x00a5,
+	BNXT_ULP_CLASS_HID_58a5 = 0x58a5,
+	BNXT_ULP_CLASS_HID_5479 = 0x5479,
+	BNXT_ULP_CLASS_HID_2589 = 0x2589,
+	BNXT_ULP_CLASS_HID_215d = 0x215d,
+	BNXT_ULP_CLASS_HID_1c11 = 0x1c11,
+	BNXT_ULP_CLASS_HID_1725 = 0x1725,
+	BNXT_ULP_CLASS_HID_5c15 = 0x5c15,
+	BNXT_ULP_CLASS_HID_5729 = 0x5729,
+	BNXT_ULP_CLASS_HID_52fd = 0x52fd,
+	BNXT_ULP_CLASS_HID_4db1 = 0x4db1,
+	BNXT_ULP_CLASS_HID_3c7d = 0x3c7d,
+	BNXT_ULP_CLASS_HID_3731 = 0x3731,
+	BNXT_ULP_CLASS_HID_32c5 = 0x32c5,
+	BNXT_ULP_CLASS_HID_2d99 = 0x2d99,
+	BNXT_ULP_CLASS_HID_4f89 = 0x4f89,
+	BNXT_ULP_CLASS_HID_4b5d = 0x4b5d,
+	BNXT_ULP_CLASS_HID_4611 = 0x4611,
+	BNXT_ULP_CLASS_HID_4125 = 0x4125,
+	BNXT_ULP_CLASS_HID_1375 = 0x1375,
+	BNXT_ULP_CLASS_HID_0e09 = 0x0e09,
+	BNXT_ULP_CLASS_HID_09dd = 0x09dd,
+	BNXT_ULP_CLASS_HID_0491 = 0x0491,
+	BNXT_ULP_CLASS_HID_49c1 = 0x49c1,
+	BNXT_ULP_CLASS_HID_4495 = 0x4495,
+	BNXT_ULP_CLASS_HID_3fa9 = 0x3fa9,
+	BNXT_ULP_CLASS_HID_3b7d = 0x3b7d,
+	BNXT_ULP_CLASS_HID_2929 = 0x2929,
+	BNXT_ULP_CLASS_HID_24fd = 0x24fd,
+	BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1,
+	BNXT_ULP_CLASS_HID_1b45 = 0x1b45,
+	BNXT_ULP_CLASS_HID_49cd = 0x49cd,
+	BNXT_ULP_CLASS_HID_4481 = 0x4481,
+	BNXT_ULP_CLASS_HID_4055 = 0x4055,
+	BNXT_ULP_CLASS_HID_3b69 = 0x3b69,
+	BNXT_ULP_CLASS_HID_0cb9 = 0x0cb9,
+	BNXT_ULP_CLASS_HID_084d = 0x084d,
+	BNXT_ULP_CLASS_HID_0301 = 0x0301,
+	BNXT_ULP_CLASS_HID_5b01 = 0x5b01,
+	BNXT_ULP_CLASS_HID_4305 = 0x4305,
+	BNXT_ULP_CLASS_HID_3ed9 = 0x3ed9,
+	BNXT_ULP_CLASS_HID_39ed = 0x39ed,
+	BNXT_ULP_CLASS_HID_34a1 = 0x34a1,
+	BNXT_ULP_CLASS_HID_236d = 0x236d,
+	BNXT_ULP_CLASS_HID_1e21 = 0x1e21,
+	BNXT_ULP_CLASS_HID_19f5 = 0x19f5,
+	BNXT_ULP_CLASS_HID_1489 = 0x1489,
+	BNXT_ULP_CLASS_HID_2539 = 0x2539,
+	BNXT_ULP_CLASS_HID_2bf5 = 0x2bf5,
+	BNXT_ULP_CLASS_HID_b6af = 0xb6af,
+	BNXT_ULP_CLASS_HID_b1d3 = 0xb1d3,
+	BNXT_ULP_CLASS_HID_1c7d3 = 0x1c7d3,
+	BNXT_ULP_CLASS_HID_1ccaf = 0x1ccaf,
+	BNXT_ULP_CLASS_HID_da33 = 0xda33,
+	BNXT_ULP_CLASS_HID_d567 = 0xd567,
+	BNXT_ULP_CLASS_HID_18eab = 0x18eab,
+	BNXT_ULP_CLASS_HID_19367 = 0x19367,
+	BNXT_ULP_CLASS_HID_a10b = 0xa10b,
+	BNXT_ULP_CLASS_HID_9c3f = 0x9c3f,
+	BNXT_ULP_CLASS_HID_1b23f = 0x1b23f,
+	BNXT_ULP_CLASS_HID_1b70b = 0x1b70b,
+	BNXT_ULP_CLASS_HID_c49f = 0xc49f,
+	BNXT_ULP_CLASS_HID_bfc3 = 0xbfc3,
+	BNXT_ULP_CLASS_HID_1d5c3 = 0x1d5c3,
+	BNXT_ULP_CLASS_HID_1da9f = 0x1da9f,
+	BNXT_ULP_CLASS_HID_b063 = 0xb063,
+	BNXT_ULP_CLASS_HID_ab97 = 0xab97,
+	BNXT_ULP_CLASS_HID_1c197 = 0x1c197,
+	BNXT_ULP_CLASS_HID_1c663 = 0x1c663,
+	BNXT_ULP_CLASS_HID_d3f7 = 0xd3f7,
+	BNXT_ULP_CLASS_HID_cf3b = 0xcf3b,
+	BNXT_ULP_CLASS_HID_1886f = 0x1886f,
+	BNXT_ULP_CLASS_HID_18d3b = 0x18d3b,
+	BNXT_ULP_CLASS_HID_9acf = 0x9acf,
+	BNXT_ULP_CLASS_HID_95f3 = 0x95f3,
+	BNXT_ULP_CLASS_HID_1abf3 = 0x1abf3,
+	BNXT_ULP_CLASS_HID_1b0cf = 0x1b0cf,
+	BNXT_ULP_CLASS_HID_be53 = 0xbe53,
+	BNXT_ULP_CLASS_HID_b987 = 0xb987,
+	BNXT_ULP_CLASS_HID_1cf87 = 0x1cf87,
+	BNXT_ULP_CLASS_HID_1d453 = 0x1d453,
+	BNXT_ULP_CLASS_HID_aa27 = 0xaa27,
+	BNXT_ULP_CLASS_HID_a56b = 0xa56b,
+	BNXT_ULP_CLASS_HID_1bb6b = 0x1bb6b,
+	BNXT_ULP_CLASS_HID_1c027 = 0x1c027,
+	BNXT_ULP_CLASS_HID_cdcb = 0xcdcb,
+	BNXT_ULP_CLASS_HID_c8ff = 0xc8ff,
+	BNXT_ULP_CLASS_HID_18223 = 0x18223,
+	BNXT_ULP_CLASS_HID_186ff = 0x186ff,
+	BNXT_ULP_CLASS_HID_9483 = 0x9483,
+	BNXT_ULP_CLASS_HID_8fb7 = 0x8fb7,
+	BNXT_ULP_CLASS_HID_1a5b7 = 0x1a5b7,
+	BNXT_ULP_CLASS_HID_1aa83 = 0x1aa83,
+	BNXT_ULP_CLASS_HID_b817 = 0xb817,
+	BNXT_ULP_CLASS_HID_b35b = 0xb35b,
+	BNXT_ULP_CLASS_HID_1c95b = 0x1c95b,
+	BNXT_ULP_CLASS_HID_1ce17 = 0x1ce17,
+	BNXT_ULP_CLASS_HID_a3fb = 0xa3fb,
+	BNXT_ULP_CLASS_HID_9f2f = 0x9f2f,
+	BNXT_ULP_CLASS_HID_1b52f = 0x1b52f,
+	BNXT_ULP_CLASS_HID_1b9fb = 0x1b9fb,
+	BNXT_ULP_CLASS_HID_c78f = 0xc78f,
+	BNXT_ULP_CLASS_HID_c2b3 = 0xc2b3,
+	BNXT_ULP_CLASS_HID_1d8b3 = 0x1d8b3,
+	BNXT_ULP_CLASS_HID_180b3 = 0x180b3,
+	BNXT_ULP_CLASS_HID_8e47 = 0x8e47,
+	BNXT_ULP_CLASS_HID_898b = 0x898b,
+	BNXT_ULP_CLASS_HID_19f8b = 0x19f8b,
+	BNXT_ULP_CLASS_HID_1a447 = 0x1a447,
+	BNXT_ULP_CLASS_HID_b1eb = 0xb1eb,
+	BNXT_ULP_CLASS_HID_ad1f = 0xad1f,
+	BNXT_ULP_CLASS_HID_1c31f = 0x1c31f,
+	BNXT_ULP_CLASS_HID_1c7eb = 0x1c7eb,
+	BNXT_ULP_CLASS_HID_9137 = 0x9137,
+	BNXT_ULP_CLASS_HID_8c7b = 0x8c7b,
+	BNXT_ULP_CLASS_HID_1a27b = 0x1a27b,
+	BNXT_ULP_CLASS_HID_1a737 = 0x1a737,
+	BNXT_ULP_CLASS_HID_b4db = 0xb4db,
+	BNXT_ULP_CLASS_HID_b00f = 0xb00f,
+	BNXT_ULP_CLASS_HID_1c60f = 0x1c60f,
+	BNXT_ULP_CLASS_HID_1cadb = 0x1cadb,
+	BNXT_ULP_CLASS_HID_8b0b = 0x8b0b,
+	BNXT_ULP_CLASS_HID_863f = 0x863f,
+	BNXT_ULP_CLASS_HID_19c3f = 0x19c3f,
+	BNXT_ULP_CLASS_HID_1a10b = 0x1a10b,
+	BNXT_ULP_CLASS_HID_ae9f = 0xae9f,
+	BNXT_ULP_CLASS_HID_a9c3 = 0xa9c3,
+	BNXT_ULP_CLASS_HID_1bfc3 = 0x1bfc3,
+	BNXT_ULP_CLASS_HID_1c49f = 0x1c49f,
+	BNXT_ULP_CLASS_HID_2563 = 0x2563,
+	BNXT_ULP_CLASS_HID_2baf = 0x2baf,
+	BNXT_ULP_CLASS_HID_4f33 = 0x4f33,
+	BNXT_ULP_CLASS_HID_160b = 0x160b,
+	BNXT_ULP_CLASS_HID_399f = 0x399f,
+	BNXT_ULP_CLASS_HID_48f7 = 0x48f7,
+	BNXT_ULP_CLASS_HID_0fcf = 0x0fcf,
+	BNXT_ULP_CLASS_HID_3353 = 0x3353,
+	BNXT_ULP_CLASS_HID_b68f = 0xb68f,
+	BNXT_ULP_CLASS_HID_b94f = 0xb94f,
+	BNXT_ULP_CLASS_HID_fc0f = 0xfc0f,
+	BNXT_ULP_CLASS_HID_fecf = 0xfecf,
+	BNXT_ULP_CLASS_HID_b1f3 = 0xb1f3,
+	BNXT_ULP_CLASS_HID_b4b3 = 0xb4b3,
+	BNXT_ULP_CLASS_HID_f773 = 0xf773,
+	BNXT_ULP_CLASS_HID_fa33 = 0xfa33,
+	BNXT_ULP_CLASS_HID_1c7f3 = 0x1c7f3,
+	BNXT_ULP_CLASS_HID_1eab3 = 0x1eab3,
+	BNXT_ULP_CLASS_HID_1cd73 = 0x1cd73,
+	BNXT_ULP_CLASS_HID_1f033 = 0x1f033,
+	BNXT_ULP_CLASS_HID_1cc8f = 0x1cc8f,
+	BNXT_ULP_CLASS_HID_1ef4f = 0x1ef4f,
+	BNXT_ULP_CLASS_HID_1d20f = 0x1d20f,
+	BNXT_ULP_CLASS_HID_1f4cf = 0x1f4cf,
+	BNXT_ULP_CLASS_HID_da13 = 0xda13,
+	BNXT_ULP_CLASS_HID_a007 = 0xa007,
+	BNXT_ULP_CLASS_HID_c2c7 = 0xc2c7,
+	BNXT_ULP_CLASS_HID_e587 = 0xe587,
+	BNXT_ULP_CLASS_HID_d547 = 0xd547,
+	BNXT_ULP_CLASS_HID_f807 = 0xf807,
+	BNXT_ULP_CLASS_HID_dac7 = 0xdac7,
+	BNXT_ULP_CLASS_HID_e0cb = 0xe0cb,
+	BNXT_ULP_CLASS_HID_18e8b = 0x18e8b,
+	BNXT_ULP_CLASS_HID_1b14b = 0x1b14b,
+	BNXT_ULP_CLASS_HID_1d40b = 0x1d40b,
+	BNXT_ULP_CLASS_HID_1f6cb = 0x1f6cb,
+	BNXT_ULP_CLASS_HID_19347 = 0x19347,
+	BNXT_ULP_CLASS_HID_1b607 = 0x1b607,
+	BNXT_ULP_CLASS_HID_1d8c7 = 0x1d8c7,
+	BNXT_ULP_CLASS_HID_1fb87 = 0x1fb87,
+	BNXT_ULP_CLASS_HID_a12b = 0xa12b,
+	BNXT_ULP_CLASS_HID_a3eb = 0xa3eb,
+	BNXT_ULP_CLASS_HID_e6ab = 0xe6ab,
+	BNXT_ULP_CLASS_HID_e96b = 0xe96b,
+	BNXT_ULP_CLASS_HID_9c1f = 0x9c1f,
+	BNXT_ULP_CLASS_HID_bedf = 0xbedf,
+	BNXT_ULP_CLASS_HID_e19f = 0xe19f,
+	BNXT_ULP_CLASS_HID_e45f = 0xe45f,
+	BNXT_ULP_CLASS_HID_1b21f = 0x1b21f,
+	BNXT_ULP_CLASS_HID_1b4df = 0x1b4df,
+	BNXT_ULP_CLASS_HID_1f79f = 0x1f79f,
+	BNXT_ULP_CLASS_HID_1fa5f = 0x1fa5f,
+	BNXT_ULP_CLASS_HID_1b72b = 0x1b72b,
+	BNXT_ULP_CLASS_HID_1b9eb = 0x1b9eb,
+	BNXT_ULP_CLASS_HID_1fcab = 0x1fcab,
+	BNXT_ULP_CLASS_HID_1ff6b = 0x1ff6b,
+	BNXT_ULP_CLASS_HID_c4bf = 0xc4bf,
+	BNXT_ULP_CLASS_HID_e77f = 0xe77f,
+	BNXT_ULP_CLASS_HID_ca3f = 0xca3f,
+	BNXT_ULP_CLASS_HID_ecff = 0xecff,
+	BNXT_ULP_CLASS_HID_bfe3 = 0xbfe3,
+	BNXT_ULP_CLASS_HID_e2a3 = 0xe2a3,
+	BNXT_ULP_CLASS_HID_c563 = 0xc563,
+	BNXT_ULP_CLASS_HID_e823 = 0xe823,
+	BNXT_ULP_CLASS_HID_1d5e3 = 0x1d5e3,
+	BNXT_ULP_CLASS_HID_1f8a3 = 0x1f8a3,
+	BNXT_ULP_CLASS_HID_1db63 = 0x1db63,
+	BNXT_ULP_CLASS_HID_1e117 = 0x1e117,
+	BNXT_ULP_CLASS_HID_1dabf = 0x1dabf,
+	BNXT_ULP_CLASS_HID_1a0a3 = 0x1a0a3,
+	BNXT_ULP_CLASS_HID_1c363 = 0x1c363,
+	BNXT_ULP_CLASS_HID_1e623 = 0x1e623,
+	BNXT_ULP_CLASS_HID_b043 = 0xb043,
+	BNXT_ULP_CLASS_HID_b303 = 0xb303,
+	BNXT_ULP_CLASS_HID_f5c3 = 0xf5c3,
+	BNXT_ULP_CLASS_HID_f883 = 0xf883,
+	BNXT_ULP_CLASS_HID_abb7 = 0xabb7,
+	BNXT_ULP_CLASS_HID_ae77 = 0xae77,
+	BNXT_ULP_CLASS_HID_f137 = 0xf137,
+	BNXT_ULP_CLASS_HID_f3f7 = 0xf3f7,
+	BNXT_ULP_CLASS_HID_1c1b7 = 0x1c1b7,
+	BNXT_ULP_CLASS_HID_1e477 = 0x1e477,
+	BNXT_ULP_CLASS_HID_1c737 = 0x1c737,
+	BNXT_ULP_CLASS_HID_1e9f7 = 0x1e9f7,
+	BNXT_ULP_CLASS_HID_1c643 = 0x1c643,
+	BNXT_ULP_CLASS_HID_1e903 = 0x1e903,
+	BNXT_ULP_CLASS_HID_1cbc3 = 0x1cbc3,
+	BNXT_ULP_CLASS_HID_1ee83 = 0x1ee83,
+	BNXT_ULP_CLASS_HID_d3d7 = 0xd3d7,
+	BNXT_ULP_CLASS_HID_f697 = 0xf697,
+	BNXT_ULP_CLASS_HID_d957 = 0xd957,
+	BNXT_ULP_CLASS_HID_fc17 = 0xfc17,
+	BNXT_ULP_CLASS_HID_cf1b = 0xcf1b,
+	BNXT_ULP_CLASS_HID_f1db = 0xf1db,
+	BNXT_ULP_CLASS_HID_d49b = 0xd49b,
+	BNXT_ULP_CLASS_HID_f75b = 0xf75b,
+	BNXT_ULP_CLASS_HID_1884f = 0x1884f,
+	BNXT_ULP_CLASS_HID_1ab0f = 0x1ab0f,
+	BNXT_ULP_CLASS_HID_1cdcf = 0x1cdcf,
+	BNXT_ULP_CLASS_HID_1f08f = 0x1f08f,
+	BNXT_ULP_CLASS_HID_18d1b = 0x18d1b,
+	BNXT_ULP_CLASS_HID_1afdb = 0x1afdb,
+	BNXT_ULP_CLASS_HID_1d29b = 0x1d29b,
+	BNXT_ULP_CLASS_HID_1f55b = 0x1f55b,
+	BNXT_ULP_CLASS_HID_9aef = 0x9aef,
+	BNXT_ULP_CLASS_HID_bdaf = 0xbdaf,
+	BNXT_ULP_CLASS_HID_e06f = 0xe06f,
+	BNXT_ULP_CLASS_HID_e32f = 0xe32f,
+	BNXT_ULP_CLASS_HID_95d3 = 0x95d3,
+	BNXT_ULP_CLASS_HID_b893 = 0xb893,
+	BNXT_ULP_CLASS_HID_db53 = 0xdb53,
+	BNXT_ULP_CLASS_HID_fe13 = 0xfe13,
+	BNXT_ULP_CLASS_HID_1abd3 = 0x1abd3,
+	BNXT_ULP_CLASS_HID_1ae93 = 0x1ae93,
+	BNXT_ULP_CLASS_HID_1f153 = 0x1f153,
+	BNXT_ULP_CLASS_HID_1f413 = 0x1f413,
+	BNXT_ULP_CLASS_HID_1b0ef = 0x1b0ef,
+	BNXT_ULP_CLASS_HID_1b3af = 0x1b3af,
+	BNXT_ULP_CLASS_HID_1f66f = 0x1f66f,
+	BNXT_ULP_CLASS_HID_1f92f = 0x1f92f,
+	BNXT_ULP_CLASS_HID_be73 = 0xbe73,
+	BNXT_ULP_CLASS_HID_e133 = 0xe133,
+	BNXT_ULP_CLASS_HID_c3f3 = 0xc3f3,
+	BNXT_ULP_CLASS_HID_e6b3 = 0xe6b3,
+	BNXT_ULP_CLASS_HID_b9a7 = 0xb9a7,
+	BNXT_ULP_CLASS_HID_bc67 = 0xbc67,
+	BNXT_ULP_CLASS_HID_ff27 = 0xff27,
+	BNXT_ULP_CLASS_HID_e1e7 = 0xe1e7,
+	BNXT_ULP_CLASS_HID_1cfa7 = 0x1cfa7,
+	BNXT_ULP_CLASS_HID_1f267 = 0x1f267,
+	BNXT_ULP_CLASS_HID_1d527 = 0x1d527,
+	BNXT_ULP_CLASS_HID_1f7e7 = 0x1f7e7,
+	BNXT_ULP_CLASS_HID_1d473 = 0x1d473,
+	BNXT_ULP_CLASS_HID_1f733 = 0x1f733,
+	BNXT_ULP_CLASS_HID_1d9f3 = 0x1d9f3,
+	BNXT_ULP_CLASS_HID_1fcb3 = 0x1fcb3,
+	BNXT_ULP_CLASS_HID_aa07 = 0xaa07,
+	BNXT_ULP_CLASS_HID_acc7 = 0xacc7,
+	BNXT_ULP_CLASS_HID_ef87 = 0xef87,
+	BNXT_ULP_CLASS_HID_f247 = 0xf247,
+	BNXT_ULP_CLASS_HID_a54b = 0xa54b,
+	BNXT_ULP_CLASS_HID_a80b = 0xa80b,
+	BNXT_ULP_CLASS_HID_eacb = 0xeacb,
+	BNXT_ULP_CLASS_HID_ed8b = 0xed8b,
+	BNXT_ULP_CLASS_HID_1bb4b = 0x1bb4b,
+	BNXT_ULP_CLASS_HID_1be0b = 0x1be0b,
+	BNXT_ULP_CLASS_HID_1c0cb = 0x1c0cb,
+	BNXT_ULP_CLASS_HID_1e38b = 0x1e38b,
+	BNXT_ULP_CLASS_HID_1c007 = 0x1c007,
+	BNXT_ULP_CLASS_HID_1e2c7 = 0x1e2c7,
+	BNXT_ULP_CLASS_HID_1c587 = 0x1c587,
+	BNXT_ULP_CLASS_HID_1e847 = 0x1e847,
+	BNXT_ULP_CLASS_HID_cdeb = 0xcdeb,
+	BNXT_ULP_CLASS_HID_f0ab = 0xf0ab,
+	BNXT_ULP_CLASS_HID_d36b = 0xd36b,
+	BNXT_ULP_CLASS_HID_f62b = 0xf62b,
+	BNXT_ULP_CLASS_HID_c8df = 0xc8df,
+	BNXT_ULP_CLASS_HID_eb9f = 0xeb9f,
+	BNXT_ULP_CLASS_HID_ce5f = 0xce5f,
+	BNXT_ULP_CLASS_HID_f11f = 0xf11f,
+	BNXT_ULP_CLASS_HID_18203 = 0x18203,
+	BNXT_ULP_CLASS_HID_1a4c3 = 0x1a4c3,
+	BNXT_ULP_CLASS_HID_1c783 = 0x1c783,
+	BNXT_ULP_CLASS_HID_1ea43 = 0x1ea43,
+	BNXT_ULP_CLASS_HID_186df = 0x186df,
+	BNXT_ULP_CLASS_HID_1a99f = 0x1a99f,
+	BNXT_ULP_CLASS_HID_1cc5f = 0x1cc5f,
+	BNXT_ULP_CLASS_HID_1ef1f = 0x1ef1f,
+	BNXT_ULP_CLASS_HID_94a3 = 0x94a3,
+	BNXT_ULP_CLASS_HID_b763 = 0xb763,
+	BNXT_ULP_CLASS_HID_da23 = 0xda23,
+	BNXT_ULP_CLASS_HID_fce3 = 0xfce3,
+	BNXT_ULP_CLASS_HID_8f97 = 0x8f97,
+	BNXT_ULP_CLASS_HID_b257 = 0xb257,
+	BNXT_ULP_CLASS_HID_d517 = 0xd517,
+	BNXT_ULP_CLASS_HID_f7d7 = 0xf7d7,
+	BNXT_ULP_CLASS_HID_1a597 = 0x1a597,
+	BNXT_ULP_CLASS_HID_1a857 = 0x1a857,
+	BNXT_ULP_CLASS_HID_1eb17 = 0x1eb17,
+	BNXT_ULP_CLASS_HID_1edd7 = 0x1edd7,
+	BNXT_ULP_CLASS_HID_1aaa3 = 0x1aaa3,
+	BNXT_ULP_CLASS_HID_1ad63 = 0x1ad63,
+	BNXT_ULP_CLASS_HID_1f023 = 0x1f023,
+	BNXT_ULP_CLASS_HID_1f2e3 = 0x1f2e3,
+	BNXT_ULP_CLASS_HID_b837 = 0xb837,
+	BNXT_ULP_CLASS_HID_baf7 = 0xbaf7,
+	BNXT_ULP_CLASS_HID_fdb7 = 0xfdb7,
+	BNXT_ULP_CLASS_HID_e077 = 0xe077,
+	BNXT_ULP_CLASS_HID_b37b = 0xb37b,
+	BNXT_ULP_CLASS_HID_b63b = 0xb63b,
+	BNXT_ULP_CLASS_HID_f8fb = 0xf8fb,
+	BNXT_ULP_CLASS_HID_fbbb = 0xfbbb,
+	BNXT_ULP_CLASS_HID_1c97b = 0x1c97b,
+	BNXT_ULP_CLASS_HID_1ec3b = 0x1ec3b,
+	BNXT_ULP_CLASS_HID_1cefb = 0x1cefb,
+	BNXT_ULP_CLASS_HID_1f1bb = 0x1f1bb,
+	BNXT_ULP_CLASS_HID_1ce37 = 0x1ce37,
+	BNXT_ULP_CLASS_HID_1f0f7 = 0x1f0f7,
+	BNXT_ULP_CLASS_HID_1d3b7 = 0x1d3b7,
+	BNXT_ULP_CLASS_HID_1f677 = 0x1f677,
+	BNXT_ULP_CLASS_HID_a3db = 0xa3db,
+	BNXT_ULP_CLASS_HID_a69b = 0xa69b,
+	BNXT_ULP_CLASS_HID_e95b = 0xe95b,
+	BNXT_ULP_CLASS_HID_ec1b = 0xec1b,
+	BNXT_ULP_CLASS_HID_9f0f = 0x9f0f,
+	BNXT_ULP_CLASS_HID_a1cf = 0xa1cf,
+	BNXT_ULP_CLASS_HID_e48f = 0xe48f,
+	BNXT_ULP_CLASS_HID_e74f = 0xe74f,
+	BNXT_ULP_CLASS_HID_1b50f = 0x1b50f,
+	BNXT_ULP_CLASS_HID_1b7cf = 0x1b7cf,
+	BNXT_ULP_CLASS_HID_1fa8f = 0x1fa8f,
+	BNXT_ULP_CLASS_HID_1fd4f = 0x1fd4f,
+	BNXT_ULP_CLASS_HID_1b9db = 0x1b9db,
+	BNXT_ULP_CLASS_HID_1bc9b = 0x1bc9b,
+	BNXT_ULP_CLASS_HID_1ff5b = 0x1ff5b,
+	BNXT_ULP_CLASS_HID_1e21b = 0x1e21b,
+	BNXT_ULP_CLASS_HID_c7af = 0xc7af,
+	BNXT_ULP_CLASS_HID_ea6f = 0xea6f,
+	BNXT_ULP_CLASS_HID_cd2f = 0xcd2f,
+	BNXT_ULP_CLASS_HID_efef = 0xefef,
+	BNXT_ULP_CLASS_HID_c293 = 0xc293,
+	BNXT_ULP_CLASS_HID_e553 = 0xe553,
+	BNXT_ULP_CLASS_HID_c813 = 0xc813,
+	BNXT_ULP_CLASS_HID_ead3 = 0xead3,
+	BNXT_ULP_CLASS_HID_1d893 = 0x1d893,
+	BNXT_ULP_CLASS_HID_1fb53 = 0x1fb53,
+	BNXT_ULP_CLASS_HID_1c147 = 0x1c147,
+	BNXT_ULP_CLASS_HID_1e407 = 0x1e407,
+	BNXT_ULP_CLASS_HID_18093 = 0x18093,
+	BNXT_ULP_CLASS_HID_1a353 = 0x1a353,
+	BNXT_ULP_CLASS_HID_1c613 = 0x1c613,
+	BNXT_ULP_CLASS_HID_1e8d3 = 0x1e8d3,
+	BNXT_ULP_CLASS_HID_8e67 = 0x8e67,
+	BNXT_ULP_CLASS_HID_b127 = 0xb127,
+	BNXT_ULP_CLASS_HID_d3e7 = 0xd3e7,
+	BNXT_ULP_CLASS_HID_f6a7 = 0xf6a7,
+	BNXT_ULP_CLASS_HID_89ab = 0x89ab,
+	BNXT_ULP_CLASS_HID_ac6b = 0xac6b,
+	BNXT_ULP_CLASS_HID_cf2b = 0xcf2b,
+	BNXT_ULP_CLASS_HID_f1eb = 0xf1eb,
+	BNXT_ULP_CLASS_HID_19fab = 0x19fab,
+	BNXT_ULP_CLASS_HID_1a26b = 0x1a26b,
+	BNXT_ULP_CLASS_HID_1e52b = 0x1e52b,
+	BNXT_ULP_CLASS_HID_1e7eb = 0x1e7eb,
+	BNXT_ULP_CLASS_HID_1a467 = 0x1a467,
+	BNXT_ULP_CLASS_HID_1a727 = 0x1a727,
+	BNXT_ULP_CLASS_HID_1e9e7 = 0x1e9e7,
+	BNXT_ULP_CLASS_HID_1eca7 = 0x1eca7,
+	BNXT_ULP_CLASS_HID_b1cb = 0xb1cb,
+	BNXT_ULP_CLASS_HID_b48b = 0xb48b,
+	BNXT_ULP_CLASS_HID_f74b = 0xf74b,
+	BNXT_ULP_CLASS_HID_fa0b = 0xfa0b,
+	BNXT_ULP_CLASS_HID_ad3f = 0xad3f,
+	BNXT_ULP_CLASS_HID_afff = 0xafff,
+	BNXT_ULP_CLASS_HID_f2bf = 0xf2bf,
+	BNXT_ULP_CLASS_HID_f57f = 0xf57f,
+	BNXT_ULP_CLASS_HID_1c33f = 0x1c33f,
+	BNXT_ULP_CLASS_HID_1e5ff = 0x1e5ff,
+	BNXT_ULP_CLASS_HID_1c8bf = 0x1c8bf,
+	BNXT_ULP_CLASS_HID_1eb7f = 0x1eb7f,
+	BNXT_ULP_CLASS_HID_1c7cb = 0x1c7cb,
+	BNXT_ULP_CLASS_HID_1ea8b = 0x1ea8b,
+	BNXT_ULP_CLASS_HID_1cd4b = 0x1cd4b,
+	BNXT_ULP_CLASS_HID_1f00b = 0x1f00b,
+	BNXT_ULP_CLASS_HID_9117 = 0x9117,
+	BNXT_ULP_CLASS_HID_b3d7 = 0xb3d7,
+	BNXT_ULP_CLASS_HID_d697 = 0xd697,
+	BNXT_ULP_CLASS_HID_f957 = 0xf957,
+	BNXT_ULP_CLASS_HID_8c5b = 0x8c5b,
+	BNXT_ULP_CLASS_HID_af1b = 0xaf1b,
+	BNXT_ULP_CLASS_HID_d1db = 0xd1db,
+	BNXT_ULP_CLASS_HID_f49b = 0xf49b,
+	BNXT_ULP_CLASS_HID_1a25b = 0x1a25b,
+	BNXT_ULP_CLASS_HID_1a51b = 0x1a51b,
+	BNXT_ULP_CLASS_HID_1e7db = 0x1e7db,
+	BNXT_ULP_CLASS_HID_1ea9b = 0x1ea9b,
+	BNXT_ULP_CLASS_HID_1a717 = 0x1a717,
+	BNXT_ULP_CLASS_HID_1a9d7 = 0x1a9d7,
+	BNXT_ULP_CLASS_HID_1ec97 = 0x1ec97,
+	BNXT_ULP_CLASS_HID_1ef57 = 0x1ef57,
+	BNXT_ULP_CLASS_HID_b4fb = 0xb4fb,
+	BNXT_ULP_CLASS_HID_b7bb = 0xb7bb,
+	BNXT_ULP_CLASS_HID_fa7b = 0xfa7b,
+	BNXT_ULP_CLASS_HID_fd3b = 0xfd3b,
+	BNXT_ULP_CLASS_HID_b02f = 0xb02f,
+	BNXT_ULP_CLASS_HID_b2ef = 0xb2ef,
+	BNXT_ULP_CLASS_HID_f5af = 0xf5af,
+	BNXT_ULP_CLASS_HID_f86f = 0xf86f,
+	BNXT_ULP_CLASS_HID_1c62f = 0x1c62f,
+	BNXT_ULP_CLASS_HID_1e8ef = 0x1e8ef,
+	BNXT_ULP_CLASS_HID_1cbaf = 0x1cbaf,
+	BNXT_ULP_CLASS_HID_1ee6f = 0x1ee6f,
+	BNXT_ULP_CLASS_HID_1cafb = 0x1cafb,
+	BNXT_ULP_CLASS_HID_1edbb = 0x1edbb,
+	BNXT_ULP_CLASS_HID_1d07b = 0x1d07b,
+	BNXT_ULP_CLASS_HID_1f33b = 0x1f33b,
+	BNXT_ULP_CLASS_HID_8b2b = 0x8b2b,
+	BNXT_ULP_CLASS_HID_adeb = 0xadeb,
+	BNXT_ULP_CLASS_HID_d0ab = 0xd0ab,
+	BNXT_ULP_CLASS_HID_f36b = 0xf36b,
+	BNXT_ULP_CLASS_HID_861f = 0x861f,
+	BNXT_ULP_CLASS_HID_a8df = 0xa8df,
+	BNXT_ULP_CLASS_HID_cb9f = 0xcb9f,
+	BNXT_ULP_CLASS_HID_ee5f = 0xee5f,
+	BNXT_ULP_CLASS_HID_19c1f = 0x19c1f,
+	BNXT_ULP_CLASS_HID_1bedf = 0x1bedf,
+	BNXT_ULP_CLASS_HID_1e19f = 0x1e19f,
+	BNXT_ULP_CLASS_HID_1e45f = 0x1e45f,
+	BNXT_ULP_CLASS_HID_1a12b = 0x1a12b,
+	BNXT_ULP_CLASS_HID_1a3eb = 0x1a3eb,
+	BNXT_ULP_CLASS_HID_1e6ab = 0x1e6ab,
+	BNXT_ULP_CLASS_HID_1e96b = 0x1e96b,
+	BNXT_ULP_CLASS_HID_aebf = 0xaebf,
+	BNXT_ULP_CLASS_HID_b17f = 0xb17f,
+	BNXT_ULP_CLASS_HID_f43f = 0xf43f,
+	BNXT_ULP_CLASS_HID_f6ff = 0xf6ff,
+	BNXT_ULP_CLASS_HID_a9e3 = 0xa9e3,
+	BNXT_ULP_CLASS_HID_aca3 = 0xaca3,
+	BNXT_ULP_CLASS_HID_ef63 = 0xef63,
+	BNXT_ULP_CLASS_HID_f223 = 0xf223,
+	BNXT_ULP_CLASS_HID_1bfe3 = 0x1bfe3,
+	BNXT_ULP_CLASS_HID_1e2a3 = 0x1e2a3,
+	BNXT_ULP_CLASS_HID_1c563 = 0x1c563,
+	BNXT_ULP_CLASS_HID_1e823 = 0x1e823,
+	BNXT_ULP_CLASS_HID_1c4bf = 0x1c4bf,
+	BNXT_ULP_CLASS_HID_1e77f = 0x1e77f,
+	BNXT_ULP_CLASS_HID_1ca3f = 0x1ca3f,
+	BNXT_ULP_CLASS_HID_1ecff = 0x1ecff,
+	BNXT_ULP_CLASS_HID_2543 = 0x2543,
+	BNXT_ULP_CLASS_HID_2b8f = 0x2b8f,
+	BNXT_ULP_CLASS_HID_4f13 = 0x4f13,
+	BNXT_ULP_CLASS_HID_162b = 0x162b,
+	BNXT_ULP_CLASS_HID_39bf = 0x39bf,
+	BNXT_ULP_CLASS_HID_48d7 = 0x48d7,
+	BNXT_ULP_CLASS_HID_0fef = 0x0fef,
+	BNXT_ULP_CLASS_HID_3373 = 0x3373,
+	BNXT_ULP_CLASS_HID_b6ef = 0xb6ef,
+	BNXT_ULP_CLASS_HID_b92f = 0xb92f,
+	BNXT_ULP_CLASS_HID_fc6f = 0xfc6f,
+	BNXT_ULP_CLASS_HID_feaf = 0xfeaf,
+	BNXT_ULP_CLASS_HID_b193 = 0xb193,
+	BNXT_ULP_CLASS_HID_b4d3 = 0xb4d3,
+	BNXT_ULP_CLASS_HID_f713 = 0xf713,
+	BNXT_ULP_CLASS_HID_fa53 = 0xfa53,
+	BNXT_ULP_CLASS_HID_1c793 = 0x1c793,
+	BNXT_ULP_CLASS_HID_1ead3 = 0x1ead3,
+	BNXT_ULP_CLASS_HID_1cd13 = 0x1cd13,
+	BNXT_ULP_CLASS_HID_1f053 = 0x1f053,
+	BNXT_ULP_CLASS_HID_1ccef = 0x1ccef,
+	BNXT_ULP_CLASS_HID_1ef2f = 0x1ef2f,
+	BNXT_ULP_CLASS_HID_1d26f = 0x1d26f,
+	BNXT_ULP_CLASS_HID_1f4af = 0x1f4af,
+	BNXT_ULP_CLASS_HID_da73 = 0xda73,
+	BNXT_ULP_CLASS_HID_a067 = 0xa067,
+	BNXT_ULP_CLASS_HID_c2a7 = 0xc2a7,
+	BNXT_ULP_CLASS_HID_e5e7 = 0xe5e7,
+	BNXT_ULP_CLASS_HID_d527 = 0xd527,
+	BNXT_ULP_CLASS_HID_f867 = 0xf867,
+	BNXT_ULP_CLASS_HID_daa7 = 0xdaa7,
+	BNXT_ULP_CLASS_HID_e0ab = 0xe0ab,
+	BNXT_ULP_CLASS_HID_18eeb = 0x18eeb,
+	BNXT_ULP_CLASS_HID_1b12b = 0x1b12b,
+	BNXT_ULP_CLASS_HID_1d46b = 0x1d46b,
+	BNXT_ULP_CLASS_HID_1f6ab = 0x1f6ab,
+	BNXT_ULP_CLASS_HID_19327 = 0x19327,
+	BNXT_ULP_CLASS_HID_1b667 = 0x1b667,
+	BNXT_ULP_CLASS_HID_1d8a7 = 0x1d8a7,
+	BNXT_ULP_CLASS_HID_1fbe7 = 0x1fbe7,
+	BNXT_ULP_CLASS_HID_a14b = 0xa14b,
+	BNXT_ULP_CLASS_HID_a38b = 0xa38b,
+	BNXT_ULP_CLASS_HID_e6cb = 0xe6cb,
+	BNXT_ULP_CLASS_HID_e90b = 0xe90b,
+	BNXT_ULP_CLASS_HID_9c7f = 0x9c7f,
+	BNXT_ULP_CLASS_HID_bebf = 0xbebf,
+	BNXT_ULP_CLASS_HID_e1ff = 0xe1ff,
+	BNXT_ULP_CLASS_HID_e43f = 0xe43f,
+	BNXT_ULP_CLASS_HID_1b27f = 0x1b27f,
+	BNXT_ULP_CLASS_HID_1b4bf = 0x1b4bf,
+	BNXT_ULP_CLASS_HID_1f7ff = 0x1f7ff,
+	BNXT_ULP_CLASS_HID_1fa3f = 0x1fa3f,
+	BNXT_ULP_CLASS_HID_1b74b = 0x1b74b,
+	BNXT_ULP_CLASS_HID_1b98b = 0x1b98b,
+	BNXT_ULP_CLASS_HID_1fccb = 0x1fccb,
+	BNXT_ULP_CLASS_HID_1ff0b = 0x1ff0b,
+	BNXT_ULP_CLASS_HID_c4df = 0xc4df,
+	BNXT_ULP_CLASS_HID_e71f = 0xe71f,
+	BNXT_ULP_CLASS_HID_ca5f = 0xca5f,
+	BNXT_ULP_CLASS_HID_ec9f = 0xec9f,
+	BNXT_ULP_CLASS_HID_bf83 = 0xbf83,
+	BNXT_ULP_CLASS_HID_e2c3 = 0xe2c3,
+	BNXT_ULP_CLASS_HID_c503 = 0xc503,
+	BNXT_ULP_CLASS_HID_e843 = 0xe843,
+	BNXT_ULP_CLASS_HID_1d583 = 0x1d583,
+	BNXT_ULP_CLASS_HID_1f8c3 = 0x1f8c3,
+	BNXT_ULP_CLASS_HID_1db03 = 0x1db03,
+	BNXT_ULP_CLASS_HID_1e177 = 0x1e177,
+	BNXT_ULP_CLASS_HID_1dadf = 0x1dadf,
+	BNXT_ULP_CLASS_HID_1a0c3 = 0x1a0c3,
+	BNXT_ULP_CLASS_HID_1c303 = 0x1c303,
+	BNXT_ULP_CLASS_HID_1e643 = 0x1e643,
+	BNXT_ULP_CLASS_HID_b023 = 0xb023,
+	BNXT_ULP_CLASS_HID_b363 = 0xb363,
+	BNXT_ULP_CLASS_HID_f5a3 = 0xf5a3,
+	BNXT_ULP_CLASS_HID_f8e3 = 0xf8e3,
+	BNXT_ULP_CLASS_HID_abd7 = 0xabd7,
+	BNXT_ULP_CLASS_HID_ae17 = 0xae17,
+	BNXT_ULP_CLASS_HID_f157 = 0xf157,
+	BNXT_ULP_CLASS_HID_f397 = 0xf397,
+	BNXT_ULP_CLASS_HID_1c1d7 = 0x1c1d7,
+	BNXT_ULP_CLASS_HID_1e417 = 0x1e417,
+	BNXT_ULP_CLASS_HID_1c757 = 0x1c757,
+	BNXT_ULP_CLASS_HID_1e997 = 0x1e997,
+	BNXT_ULP_CLASS_HID_1c623 = 0x1c623,
+	BNXT_ULP_CLASS_HID_1e963 = 0x1e963,
+	BNXT_ULP_CLASS_HID_1cba3 = 0x1cba3,
+	BNXT_ULP_CLASS_HID_1eee3 = 0x1eee3,
+	BNXT_ULP_CLASS_HID_d3b7 = 0xd3b7,
+	BNXT_ULP_CLASS_HID_f6f7 = 0xf6f7,
+	BNXT_ULP_CLASS_HID_d937 = 0xd937,
+	BNXT_ULP_CLASS_HID_fc77 = 0xfc77,
+	BNXT_ULP_CLASS_HID_cf7b = 0xcf7b,
+	BNXT_ULP_CLASS_HID_f1bb = 0xf1bb,
+	BNXT_ULP_CLASS_HID_d4fb = 0xd4fb,
+	BNXT_ULP_CLASS_HID_f73b = 0xf73b,
+	BNXT_ULP_CLASS_HID_1882f = 0x1882f,
+	BNXT_ULP_CLASS_HID_1ab6f = 0x1ab6f,
+	BNXT_ULP_CLASS_HID_1cdaf = 0x1cdaf,
+	BNXT_ULP_CLASS_HID_1f0ef = 0x1f0ef,
+	BNXT_ULP_CLASS_HID_18d7b = 0x18d7b,
+	BNXT_ULP_CLASS_HID_1afbb = 0x1afbb,
+	BNXT_ULP_CLASS_HID_1d2fb = 0x1d2fb,
+	BNXT_ULP_CLASS_HID_1f53b = 0x1f53b,
+	BNXT_ULP_CLASS_HID_9a8f = 0x9a8f,
+	BNXT_ULP_CLASS_HID_bdcf = 0xbdcf,
+	BNXT_ULP_CLASS_HID_e00f = 0xe00f,
+	BNXT_ULP_CLASS_HID_e34f = 0xe34f,
+	BNXT_ULP_CLASS_HID_95b3 = 0x95b3,
+	BNXT_ULP_CLASS_HID_b8f3 = 0xb8f3,
+	BNXT_ULP_CLASS_HID_db33 = 0xdb33,
+	BNXT_ULP_CLASS_HID_fe73 = 0xfe73,
+	BNXT_ULP_CLASS_HID_1abb3 = 0x1abb3,
+	BNXT_ULP_CLASS_HID_1aef3 = 0x1aef3,
+	BNXT_ULP_CLASS_HID_1f133 = 0x1f133,
+	BNXT_ULP_CLASS_HID_1f473 = 0x1f473,
+	BNXT_ULP_CLASS_HID_1b08f = 0x1b08f,
+	BNXT_ULP_CLASS_HID_1b3cf = 0x1b3cf,
+	BNXT_ULP_CLASS_HID_1f60f = 0x1f60f,
+	BNXT_ULP_CLASS_HID_1f94f = 0x1f94f,
+	BNXT_ULP_CLASS_HID_be13 = 0xbe13,
+	BNXT_ULP_CLASS_HID_e153 = 0xe153,
+	BNXT_ULP_CLASS_HID_c393 = 0xc393,
+	BNXT_ULP_CLASS_HID_e6d3 = 0xe6d3,
+	BNXT_ULP_CLASS_HID_b9c7 = 0xb9c7,
+	BNXT_ULP_CLASS_HID_bc07 = 0xbc07,
+	BNXT_ULP_CLASS_HID_ff47 = 0xff47,
+	BNXT_ULP_CLASS_HID_e187 = 0xe187,
+	BNXT_ULP_CLASS_HID_1cfc7 = 0x1cfc7,
+	BNXT_ULP_CLASS_HID_1f207 = 0x1f207,
+	BNXT_ULP_CLASS_HID_1d547 = 0x1d547,
+	BNXT_ULP_CLASS_HID_1f787 = 0x1f787,
+	BNXT_ULP_CLASS_HID_1d413 = 0x1d413,
+	BNXT_ULP_CLASS_HID_1f753 = 0x1f753,
+	BNXT_ULP_CLASS_HID_1d993 = 0x1d993,
+	BNXT_ULP_CLASS_HID_1fcd3 = 0x1fcd3,
+	BNXT_ULP_CLASS_HID_aa67 = 0xaa67,
+	BNXT_ULP_CLASS_HID_aca7 = 0xaca7,
+	BNXT_ULP_CLASS_HID_efe7 = 0xefe7,
+	BNXT_ULP_CLASS_HID_f227 = 0xf227,
+	BNXT_ULP_CLASS_HID_a52b = 0xa52b,
+	BNXT_ULP_CLASS_HID_a86b = 0xa86b,
+	BNXT_ULP_CLASS_HID_eaab = 0xeaab,
+	BNXT_ULP_CLASS_HID_edeb = 0xedeb,
+	BNXT_ULP_CLASS_HID_1bb2b = 0x1bb2b,
+	BNXT_ULP_CLASS_HID_1be6b = 0x1be6b,
+	BNXT_ULP_CLASS_HID_1c0ab = 0x1c0ab,
+	BNXT_ULP_CLASS_HID_1e3eb = 0x1e3eb,
+	BNXT_ULP_CLASS_HID_1c067 = 0x1c067,
+	BNXT_ULP_CLASS_HID_1e2a7 = 0x1e2a7,
+	BNXT_ULP_CLASS_HID_1c5e7 = 0x1c5e7,
+	BNXT_ULP_CLASS_HID_1e827 = 0x1e827,
+	BNXT_ULP_CLASS_HID_cd8b = 0xcd8b,
+	BNXT_ULP_CLASS_HID_f0cb = 0xf0cb,
+	BNXT_ULP_CLASS_HID_d30b = 0xd30b,
+	BNXT_ULP_CLASS_HID_f64b = 0xf64b,
+	BNXT_ULP_CLASS_HID_c8bf = 0xc8bf,
+	BNXT_ULP_CLASS_HID_ebff = 0xebff,
+	BNXT_ULP_CLASS_HID_ce3f = 0xce3f,
+	BNXT_ULP_CLASS_HID_f17f = 0xf17f,
+	BNXT_ULP_CLASS_HID_18263 = 0x18263,
+	BNXT_ULP_CLASS_HID_1a4a3 = 0x1a4a3,
+	BNXT_ULP_CLASS_HID_1c7e3 = 0x1c7e3,
+	BNXT_ULP_CLASS_HID_1ea23 = 0x1ea23,
+	BNXT_ULP_CLASS_HID_186bf = 0x186bf,
+	BNXT_ULP_CLASS_HID_1a9ff = 0x1a9ff,
+	BNXT_ULP_CLASS_HID_1cc3f = 0x1cc3f,
+	BNXT_ULP_CLASS_HID_1ef7f = 0x1ef7f,
+	BNXT_ULP_CLASS_HID_94c3 = 0x94c3,
+	BNXT_ULP_CLASS_HID_b703 = 0xb703,
+	BNXT_ULP_CLASS_HID_da43 = 0xda43,
+	BNXT_ULP_CLASS_HID_fc83 = 0xfc83,
+	BNXT_ULP_CLASS_HID_8ff7 = 0x8ff7,
+	BNXT_ULP_CLASS_HID_b237 = 0xb237,
+	BNXT_ULP_CLASS_HID_d577 = 0xd577,
+	BNXT_ULP_CLASS_HID_f7b7 = 0xf7b7,
+	BNXT_ULP_CLASS_HID_1a5f7 = 0x1a5f7,
+	BNXT_ULP_CLASS_HID_1a837 = 0x1a837,
+	BNXT_ULP_CLASS_HID_1eb77 = 0x1eb77,
+	BNXT_ULP_CLASS_HID_1edb7 = 0x1edb7,
+	BNXT_ULP_CLASS_HID_1aac3 = 0x1aac3,
+	BNXT_ULP_CLASS_HID_1ad03 = 0x1ad03,
+	BNXT_ULP_CLASS_HID_1f043 = 0x1f043,
+	BNXT_ULP_CLASS_HID_1f283 = 0x1f283,
+	BNXT_ULP_CLASS_HID_b857 = 0xb857,
+	BNXT_ULP_CLASS_HID_ba97 = 0xba97,
+	BNXT_ULP_CLASS_HID_fdd7 = 0xfdd7,
+	BNXT_ULP_CLASS_HID_e017 = 0xe017,
+	BNXT_ULP_CLASS_HID_b31b = 0xb31b,
+	BNXT_ULP_CLASS_HID_b65b = 0xb65b,
+	BNXT_ULP_CLASS_HID_f89b = 0xf89b,
+	BNXT_ULP_CLASS_HID_fbdb = 0xfbdb,
+	BNXT_ULP_CLASS_HID_1c91b = 0x1c91b,
+	BNXT_ULP_CLASS_HID_1ec5b = 0x1ec5b,
+	BNXT_ULP_CLASS_HID_1ce9b = 0x1ce9b,
+	BNXT_ULP_CLASS_HID_1f1db = 0x1f1db,
+	BNXT_ULP_CLASS_HID_1ce57 = 0x1ce57,
+	BNXT_ULP_CLASS_HID_1f097 = 0x1f097,
+	BNXT_ULP_CLASS_HID_1d3d7 = 0x1d3d7,
+	BNXT_ULP_CLASS_HID_1f617 = 0x1f617,
+	BNXT_ULP_CLASS_HID_a3bb = 0xa3bb,
+	BNXT_ULP_CLASS_HID_a6fb = 0xa6fb,
+	BNXT_ULP_CLASS_HID_e93b = 0xe93b,
+	BNXT_ULP_CLASS_HID_ec7b = 0xec7b,
+	BNXT_ULP_CLASS_HID_9f6f = 0x9f6f,
+	BNXT_ULP_CLASS_HID_a1af = 0xa1af,
+	BNXT_ULP_CLASS_HID_e4ef = 0xe4ef,
+	BNXT_ULP_CLASS_HID_e72f = 0xe72f,
+	BNXT_ULP_CLASS_HID_1b56f = 0x1b56f,
+	BNXT_ULP_CLASS_HID_1b7af = 0x1b7af,
+	BNXT_ULP_CLASS_HID_1faef = 0x1faef,
+	BNXT_ULP_CLASS_HID_1fd2f = 0x1fd2f,
+	BNXT_ULP_CLASS_HID_1b9bb = 0x1b9bb,
+	BNXT_ULP_CLASS_HID_1bcfb = 0x1bcfb,
+	BNXT_ULP_CLASS_HID_1ff3b = 0x1ff3b,
+	BNXT_ULP_CLASS_HID_1e27b = 0x1e27b,
+	BNXT_ULP_CLASS_HID_c7cf = 0xc7cf,
+	BNXT_ULP_CLASS_HID_ea0f = 0xea0f,
+	BNXT_ULP_CLASS_HID_cd4f = 0xcd4f,
+	BNXT_ULP_CLASS_HID_ef8f = 0xef8f,
+	BNXT_ULP_CLASS_HID_c2f3 = 0xc2f3,
+	BNXT_ULP_CLASS_HID_e533 = 0xe533,
+	BNXT_ULP_CLASS_HID_c873 = 0xc873,
+	BNXT_ULP_CLASS_HID_eab3 = 0xeab3,
+	BNXT_ULP_CLASS_HID_1d8f3 = 0x1d8f3,
+	BNXT_ULP_CLASS_HID_1fb33 = 0x1fb33,
+	BNXT_ULP_CLASS_HID_1c127 = 0x1c127,
+	BNXT_ULP_CLASS_HID_1e467 = 0x1e467,
+	BNXT_ULP_CLASS_HID_180f3 = 0x180f3,
+	BNXT_ULP_CLASS_HID_1a333 = 0x1a333,
+	BNXT_ULP_CLASS_HID_1c673 = 0x1c673,
+	BNXT_ULP_CLASS_HID_1e8b3 = 0x1e8b3,
+	BNXT_ULP_CLASS_HID_8e07 = 0x8e07,
+	BNXT_ULP_CLASS_HID_b147 = 0xb147,
+	BNXT_ULP_CLASS_HID_d387 = 0xd387,
+	BNXT_ULP_CLASS_HID_f6c7 = 0xf6c7,
+	BNXT_ULP_CLASS_HID_89cb = 0x89cb,
+	BNXT_ULP_CLASS_HID_ac0b = 0xac0b,
+	BNXT_ULP_CLASS_HID_cf4b = 0xcf4b,
+	BNXT_ULP_CLASS_HID_f18b = 0xf18b,
+	BNXT_ULP_CLASS_HID_19fcb = 0x19fcb,
+	BNXT_ULP_CLASS_HID_1a20b = 0x1a20b,
+	BNXT_ULP_CLASS_HID_1e54b = 0x1e54b,
+	BNXT_ULP_CLASS_HID_1e78b = 0x1e78b,
+	BNXT_ULP_CLASS_HID_1a407 = 0x1a407,
+	BNXT_ULP_CLASS_HID_1a747 = 0x1a747,
+	BNXT_ULP_CLASS_HID_1e987 = 0x1e987,
+	BNXT_ULP_CLASS_HID_1ecc7 = 0x1ecc7,
+	BNXT_ULP_CLASS_HID_b1ab = 0xb1ab,
+	BNXT_ULP_CLASS_HID_b4eb = 0xb4eb,
+	BNXT_ULP_CLASS_HID_f72b = 0xf72b,
+	BNXT_ULP_CLASS_HID_fa6b = 0xfa6b,
+	BNXT_ULP_CLASS_HID_ad5f = 0xad5f,
+	BNXT_ULP_CLASS_HID_af9f = 0xaf9f,
+	BNXT_ULP_CLASS_HID_f2df = 0xf2df,
+	BNXT_ULP_CLASS_HID_f51f = 0xf51f,
+	BNXT_ULP_CLASS_HID_1c35f = 0x1c35f,
+	BNXT_ULP_CLASS_HID_1e59f = 0x1e59f,
+	BNXT_ULP_CLASS_HID_1c8df = 0x1c8df,
+	BNXT_ULP_CLASS_HID_1eb1f = 0x1eb1f,
+	BNXT_ULP_CLASS_HID_1c7ab = 0x1c7ab,
+	BNXT_ULP_CLASS_HID_1eaeb = 0x1eaeb,
+	BNXT_ULP_CLASS_HID_1cd2b = 0x1cd2b,
+	BNXT_ULP_CLASS_HID_1f06b = 0x1f06b,
+	BNXT_ULP_CLASS_HID_9177 = 0x9177,
+	BNXT_ULP_CLASS_HID_b3b7 = 0xb3b7,
+	BNXT_ULP_CLASS_HID_d6f7 = 0xd6f7,
+	BNXT_ULP_CLASS_HID_f937 = 0xf937,
+	BNXT_ULP_CLASS_HID_8c3b = 0x8c3b,
+	BNXT_ULP_CLASS_HID_af7b = 0xaf7b,
+	BNXT_ULP_CLASS_HID_d1bb = 0xd1bb,
+	BNXT_ULP_CLASS_HID_f4fb = 0xf4fb,
+	BNXT_ULP_CLASS_HID_1a23b = 0x1a23b,
+	BNXT_ULP_CLASS_HID_1a57b = 0x1a57b,
+	BNXT_ULP_CLASS_HID_1e7bb = 0x1e7bb,
+	BNXT_ULP_CLASS_HID_1eafb = 0x1eafb,
+	BNXT_ULP_CLASS_HID_1a777 = 0x1a777,
+	BNXT_ULP_CLASS_HID_1a9b7 = 0x1a9b7,
+	BNXT_ULP_CLASS_HID_1ecf7 = 0x1ecf7,
+	BNXT_ULP_CLASS_HID_1ef37 = 0x1ef37,
+	BNXT_ULP_CLASS_HID_b49b = 0xb49b,
+	BNXT_ULP_CLASS_HID_b7db = 0xb7db,
+	BNXT_ULP_CLASS_HID_fa1b = 0xfa1b,
+	BNXT_ULP_CLASS_HID_fd5b = 0xfd5b,
+	BNXT_ULP_CLASS_HID_b04f = 0xb04f,
+	BNXT_ULP_CLASS_HID_b28f = 0xb28f,
+	BNXT_ULP_CLASS_HID_f5cf = 0xf5cf,
+	BNXT_ULP_CLASS_HID_f80f = 0xf80f,
+	BNXT_ULP_CLASS_HID_1c64f = 0x1c64f,
+	BNXT_ULP_CLASS_HID_1e88f = 0x1e88f,
+	BNXT_ULP_CLASS_HID_1cbcf = 0x1cbcf,
+	BNXT_ULP_CLASS_HID_1ee0f = 0x1ee0f,
+	BNXT_ULP_CLASS_HID_1ca9b = 0x1ca9b,
+	BNXT_ULP_CLASS_HID_1eddb = 0x1eddb,
+	BNXT_ULP_CLASS_HID_1d01b = 0x1d01b,
+	BNXT_ULP_CLASS_HID_1f35b = 0x1f35b,
+	BNXT_ULP_CLASS_HID_8b4b = 0x8b4b,
+	BNXT_ULP_CLASS_HID_ad8b = 0xad8b,
+	BNXT_ULP_CLASS_HID_d0cb = 0xd0cb,
+	BNXT_ULP_CLASS_HID_f30b = 0xf30b,
+	BNXT_ULP_CLASS_HID_867f = 0x867f,
+	BNXT_ULP_CLASS_HID_a8bf = 0xa8bf,
+	BNXT_ULP_CLASS_HID_cbff = 0xcbff,
+	BNXT_ULP_CLASS_HID_ee3f = 0xee3f,
+	BNXT_ULP_CLASS_HID_19c7f = 0x19c7f,
+	BNXT_ULP_CLASS_HID_1bebf = 0x1bebf,
+	BNXT_ULP_CLASS_HID_1e1ff = 0x1e1ff,
+	BNXT_ULP_CLASS_HID_1e43f = 0x1e43f,
+	BNXT_ULP_CLASS_HID_1a14b = 0x1a14b,
+	BNXT_ULP_CLASS_HID_1a38b = 0x1a38b,
+	BNXT_ULP_CLASS_HID_1e6cb = 0x1e6cb,
+	BNXT_ULP_CLASS_HID_1e90b = 0x1e90b,
+	BNXT_ULP_CLASS_HID_aedf = 0xaedf,
+	BNXT_ULP_CLASS_HID_b11f = 0xb11f,
+	BNXT_ULP_CLASS_HID_f45f = 0xf45f,
+	BNXT_ULP_CLASS_HID_f69f = 0xf69f,
+	BNXT_ULP_CLASS_HID_a983 = 0xa983,
+	BNXT_ULP_CLASS_HID_acc3 = 0xacc3,
+	BNXT_ULP_CLASS_HID_ef03 = 0xef03,
+	BNXT_ULP_CLASS_HID_f243 = 0xf243,
+	BNXT_ULP_CLASS_HID_1bf83 = 0x1bf83,
+	BNXT_ULP_CLASS_HID_1e2c3 = 0x1e2c3,
+	BNXT_ULP_CLASS_HID_1c503 = 0x1c503,
+	BNXT_ULP_CLASS_HID_1e843 = 0x1e843,
+	BNXT_ULP_CLASS_HID_1c4df = 0x1c4df,
+	BNXT_ULP_CLASS_HID_1e71f = 0x1e71f,
+	BNXT_ULP_CLASS_HID_1ca5f = 0x1ca5f,
+	BNXT_ULP_CLASS_HID_1ec9f = 0x1ec9f,
+	BNXT_ULP_CLASS_HID_2523 = 0x2523,
+	BNXT_ULP_CLASS_HID_2bef = 0x2bef,
+	BNXT_ULP_CLASS_HID_4f73 = 0x4f73,
+	BNXT_ULP_CLASS_HID_164b = 0x164b,
+	BNXT_ULP_CLASS_HID_39df = 0x39df,
+	BNXT_ULP_CLASS_HID_48b7 = 0x48b7,
+	BNXT_ULP_CLASS_HID_0f8f = 0x0f8f,
+	BNXT_ULP_CLASS_HID_3313 = 0x3313,
+	BNXT_ULP_CLASS_HID_257b7 = 0x257b7,
+	BNXT_ULP_CLASS_HID_24467 = 0x24467,
+	BNXT_ULP_CLASS_HID_23fbb = 0x23fbb,
+	BNXT_ULP_CLASS_HID_252cb = 0x252cb,
+	BNXT_ULP_CLASS_HID_21e7f = 0x21e7f,
+	BNXT_ULP_CLASS_HID_20b2f = 0x20b2f,
+	BNXT_ULP_CLASS_HID_20663 = 0x20663,
+	BNXT_ULP_CLASS_HID_219b3 = 0x219b3,
+	BNXT_ULP_CLASS_HID_24213 = 0x24213,
+	BNXT_ULP_CLASS_HID_22ec3 = 0x22ec3,
+	BNXT_ULP_CLASS_HID_22a17 = 0x22a17,
+	BNXT_ULP_CLASS_HID_23d27 = 0x23d27,
+	BNXT_ULP_CLASS_HID_208db = 0x208db,
+	BNXT_ULP_CLASS_HID_25277 = 0x25277,
+	BNXT_ULP_CLASS_HID_24d8b = 0x24d8b,
+	BNXT_ULP_CLASS_HID_203ef = 0x203ef,
+	BNXT_ULP_CLASS_HID_2517b = 0x2517b,
+	BNXT_ULP_CLASS_HID_23e2b = 0x23e2b,
+	BNXT_ULP_CLASS_HID_2397f = 0x2397f,
+	BNXT_ULP_CLASS_HID_24c8f = 0x24c8f,
+	BNXT_ULP_CLASS_HID_21823 = 0x21823,
+	BNXT_ULP_CLASS_HID_20513 = 0x20513,
+	BNXT_ULP_CLASS_HID_20027 = 0x20027,
+	BNXT_ULP_CLASS_HID_21377 = 0x21377,
+	BNXT_ULP_CLASS_HID_23bd7 = 0x23bd7,
+	BNXT_ULP_CLASS_HID_22887 = 0x22887,
+	BNXT_ULP_CLASS_HID_223db = 0x223db,
+	BNXT_ULP_CLASS_HID_236eb = 0x236eb,
+	BNXT_ULP_CLASS_HID_2029f = 0x2029f,
+	BNXT_ULP_CLASS_HID_24c3b = 0x24c3b,
+	BNXT_ULP_CLASS_HID_2474f = 0x2474f,
+	BNXT_ULP_CLASS_HID_25a9f = 0x25a9f,
+	BNXT_ULP_CLASS_HID_24b3f = 0x24b3f,
+	BNXT_ULP_CLASS_HID_237ef = 0x237ef,
+	BNXT_ULP_CLASS_HID_23323 = 0x23323,
+	BNXT_ULP_CLASS_HID_24673 = 0x24673,
+	BNXT_ULP_CLASS_HID_211e7 = 0x211e7,
+	BNXT_ULP_CLASS_HID_25b83 = 0x25b83,
+	BNXT_ULP_CLASS_HID_256d7 = 0x256d7,
+	BNXT_ULP_CLASS_HID_20d3b = 0x20d3b,
+	BNXT_ULP_CLASS_HID_2359b = 0x2359b,
+	BNXT_ULP_CLASS_HID_2224b = 0x2224b,
+	BNXT_ULP_CLASS_HID_21d9f = 0x21d9f,
+	BNXT_ULP_CLASS_HID_230af = 0x230af,
+	BNXT_ULP_CLASS_HID_2590f = 0x2590f,
+	BNXT_ULP_CLASS_HID_245ff = 0x245ff,
+	BNXT_ULP_CLASS_HID_24133 = 0x24133,
+	BNXT_ULP_CLASS_HID_25443 = 0x25443,
+	BNXT_ULP_CLASS_HID_244e3 = 0x244e3,
+	BNXT_ULP_CLASS_HID_231d3 = 0x231d3,
+	BNXT_ULP_CLASS_HID_22ce7 = 0x22ce7,
+	BNXT_ULP_CLASS_HID_24037 = 0x24037,
+	BNXT_ULP_CLASS_HID_20bab = 0x20bab,
+	BNXT_ULP_CLASS_HID_25547 = 0x25547,
+	BNXT_ULP_CLASS_HID_2509b = 0x2509b,
+	BNXT_ULP_CLASS_HID_206ff = 0x206ff,
+	BNXT_ULP_CLASS_HID_22f5f = 0x22f5f,
+	BNXT_ULP_CLASS_HID_21c0f = 0x21c0f,
+	BNXT_ULP_CLASS_HID_21743 = 0x21743,
+	BNXT_ULP_CLASS_HID_22a93 = 0x22a93,
+	BNXT_ULP_CLASS_HID_252f3 = 0x252f3,
+	BNXT_ULP_CLASS_HID_23fa3 = 0x23fa3,
+	BNXT_ULP_CLASS_HID_23af7 = 0x23af7,
+	BNXT_ULP_CLASS_HID_24e07 = 0x24e07,
+	BNXT_ULP_CLASS_HID_2322f = 0x2322f,
+	BNXT_ULP_CLASS_HID_21f1f = 0x21f1f,
+	BNXT_ULP_CLASS_HID_21a53 = 0x21a53,
+	BNXT_ULP_CLASS_HID_22d63 = 0x22d63,
+	BNXT_ULP_CLASS_HID_255c3 = 0x255c3,
+	BNXT_ULP_CLASS_HID_242b3 = 0x242b3,
+	BNXT_ULP_CLASS_HID_23dc7 = 0x23dc7,
+	BNXT_ULP_CLASS_HID_25117 = 0x25117,
+	BNXT_ULP_CLASS_HID_22c13 = 0x22c13,
+	BNXT_ULP_CLASS_HID_218c3 = 0x218c3,
+	BNXT_ULP_CLASS_HID_21417 = 0x21417,
+	BNXT_ULP_CLASS_HID_22727 = 0x22727,
+	BNXT_ULP_CLASS_HID_24f87 = 0x24f87,
+	BNXT_ULP_CLASS_HID_23c77 = 0x23c77,
+	BNXT_ULP_CLASS_HID_2378b = 0x2378b,
+	BNXT_ULP_CLASS_HID_24adb = 0x24adb,
+	BNXT_ULP_CLASS_HID_257b = 0x257b,
+	BNXT_ULP_CLASS_HID_2bb7 = 0x2bb7,
+	BNXT_ULP_CLASS_HID_4f2b = 0x4f2b,
+	BNXT_ULP_CLASS_HID_1613 = 0x1613,
+	BNXT_ULP_CLASS_HID_3987 = 0x3987,
+	BNXT_ULP_CLASS_HID_48ef = 0x48ef,
+	BNXT_ULP_CLASS_HID_0fd7 = 0x0fd7,
+	BNXT_ULP_CLASS_HID_334b = 0x334b,
+	BNXT_ULP_CLASS_HID_25797 = 0x25797,
+	BNXT_ULP_CLASS_HID_285eb = 0x285eb,
+	BNXT_ULP_CLASS_HID_310eb = 0x310eb,
+	BNXT_ULP_CLASS_HID_39beb = 0x39beb,
+	BNXT_ULP_CLASS_HID_24447 = 0x24447,
+	BNXT_ULP_CLASS_HID_2cf47 = 0x2cf47,
+	BNXT_ULP_CLASS_HID_35a47 = 0x35a47,
+	BNXT_ULP_CLASS_HID_3889b = 0x3889b,
+	BNXT_ULP_CLASS_HID_23f9b = 0x23f9b,
+	BNXT_ULP_CLASS_HID_2ca9b = 0x2ca9b,
+	BNXT_ULP_CLASS_HID_3559b = 0x3559b,
+	BNXT_ULP_CLASS_HID_383ef = 0x383ef,
+	BNXT_ULP_CLASS_HID_252eb = 0x252eb,
+	BNXT_ULP_CLASS_HID_2813f = 0x2813f,
+	BNXT_ULP_CLASS_HID_30c3f = 0x30c3f,
+	BNXT_ULP_CLASS_HID_3973f = 0x3973f,
+	BNXT_ULP_CLASS_HID_21e5f = 0x21e5f,
+	BNXT_ULP_CLASS_HID_2a95f = 0x2a95f,
+	BNXT_ULP_CLASS_HID_3345f = 0x3345f,
+	BNXT_ULP_CLASS_HID_3bf5f = 0x3bf5f,
+	BNXT_ULP_CLASS_HID_20b0f = 0x20b0f,
+	BNXT_ULP_CLASS_HID_2960f = 0x2960f,
+	BNXT_ULP_CLASS_HID_3210f = 0x3210f,
+	BNXT_ULP_CLASS_HID_3ac0f = 0x3ac0f,
+	BNXT_ULP_CLASS_HID_20643 = 0x20643,
+	BNXT_ULP_CLASS_HID_29143 = 0x29143,
+	BNXT_ULP_CLASS_HID_31c43 = 0x31c43,
+	BNXT_ULP_CLASS_HID_3a743 = 0x3a743,
+	BNXT_ULP_CLASS_HID_21993 = 0x21993,
+	BNXT_ULP_CLASS_HID_2a493 = 0x2a493,
+	BNXT_ULP_CLASS_HID_32f93 = 0x32f93,
+	BNXT_ULP_CLASS_HID_3ba93 = 0x3ba93,
+	BNXT_ULP_CLASS_HID_24233 = 0x24233,
+	BNXT_ULP_CLASS_HID_2cd33 = 0x2cd33,
+	BNXT_ULP_CLASS_HID_35833 = 0x35833,
+	BNXT_ULP_CLASS_HID_38607 = 0x38607,
+	BNXT_ULP_CLASS_HID_22ee3 = 0x22ee3,
+	BNXT_ULP_CLASS_HID_2b9e3 = 0x2b9e3,
+	BNXT_ULP_CLASS_HID_344e3 = 0x344e3,
+	BNXT_ULP_CLASS_HID_3cfe3 = 0x3cfe3,
+	BNXT_ULP_CLASS_HID_22a37 = 0x22a37,
+	BNXT_ULP_CLASS_HID_2b537 = 0x2b537,
+	BNXT_ULP_CLASS_HID_34037 = 0x34037,
+	BNXT_ULP_CLASS_HID_3cb37 = 0x3cb37,
+	BNXT_ULP_CLASS_HID_23d07 = 0x23d07,
+	BNXT_ULP_CLASS_HID_2c807 = 0x2c807,
+	BNXT_ULP_CLASS_HID_35307 = 0x35307,
+	BNXT_ULP_CLASS_HID_3815b = 0x3815b,
+	BNXT_ULP_CLASS_HID_208fb = 0x208fb,
+	BNXT_ULP_CLASS_HID_293fb = 0x293fb,
+	BNXT_ULP_CLASS_HID_31efb = 0x31efb,
+	BNXT_ULP_CLASS_HID_3a9fb = 0x3a9fb,
+	BNXT_ULP_CLASS_HID_25257 = 0x25257,
+	BNXT_ULP_CLASS_HID_280ab = 0x280ab,
+	BNXT_ULP_CLASS_HID_30bab = 0x30bab,
+	BNXT_ULP_CLASS_HID_396ab = 0x396ab,
+	BNXT_ULP_CLASS_HID_24dab = 0x24dab,
+	BNXT_ULP_CLASS_HID_2d8ab = 0x2d8ab,
+	BNXT_ULP_CLASS_HID_306ff = 0x306ff,
+	BNXT_ULP_CLASS_HID_391ff = 0x391ff,
+	BNXT_ULP_CLASS_HID_203cf = 0x203cf,
+	BNXT_ULP_CLASS_HID_28ecf = 0x28ecf,
+	BNXT_ULP_CLASS_HID_319cf = 0x319cf,
+	BNXT_ULP_CLASS_HID_3a4cf = 0x3a4cf,
+	BNXT_ULP_CLASS_HID_2515b = 0x2515b,
+	BNXT_ULP_CLASS_HID_2dc5b = 0x2dc5b,
+	BNXT_ULP_CLASS_HID_30aaf = 0x30aaf,
+	BNXT_ULP_CLASS_HID_395af = 0x395af,
+	BNXT_ULP_CLASS_HID_23e0b = 0x23e0b,
+	BNXT_ULP_CLASS_HID_2c90b = 0x2c90b,
+	BNXT_ULP_CLASS_HID_3540b = 0x3540b,
+	BNXT_ULP_CLASS_HID_3825f = 0x3825f,
+	BNXT_ULP_CLASS_HID_2395f = 0x2395f,
+	BNXT_ULP_CLASS_HID_2c45f = 0x2c45f,
+	BNXT_ULP_CLASS_HID_34f5f = 0x34f5f,
+	BNXT_ULP_CLASS_HID_3da5f = 0x3da5f,
+	BNXT_ULP_CLASS_HID_24caf = 0x24caf,
+	BNXT_ULP_CLASS_HID_2d7af = 0x2d7af,
+	BNXT_ULP_CLASS_HID_305e3 = 0x305e3,
+	BNXT_ULP_CLASS_HID_390e3 = 0x390e3,
+	BNXT_ULP_CLASS_HID_21803 = 0x21803,
+	BNXT_ULP_CLASS_HID_2a303 = 0x2a303,
+	BNXT_ULP_CLASS_HID_32e03 = 0x32e03,
+	BNXT_ULP_CLASS_HID_3b903 = 0x3b903,
+	BNXT_ULP_CLASS_HID_20533 = 0x20533,
+	BNXT_ULP_CLASS_HID_29033 = 0x29033,
+	BNXT_ULP_CLASS_HID_31b33 = 0x31b33,
+	BNXT_ULP_CLASS_HID_3a633 = 0x3a633,
+	BNXT_ULP_CLASS_HID_20007 = 0x20007,
+	BNXT_ULP_CLASS_HID_28b07 = 0x28b07,
+	BNXT_ULP_CLASS_HID_31607 = 0x31607,
+	BNXT_ULP_CLASS_HID_3a107 = 0x3a107,
+	BNXT_ULP_CLASS_HID_21357 = 0x21357,
+	BNXT_ULP_CLASS_HID_29e57 = 0x29e57,
+	BNXT_ULP_CLASS_HID_32957 = 0x32957,
+	BNXT_ULP_CLASS_HID_3b457 = 0x3b457,
+	BNXT_ULP_CLASS_HID_23bf7 = 0x23bf7,
+	BNXT_ULP_CLASS_HID_2c6f7 = 0x2c6f7,
+	BNXT_ULP_CLASS_HID_351f7 = 0x351f7,
+	BNXT_ULP_CLASS_HID_3dcf7 = 0x3dcf7,
+	BNXT_ULP_CLASS_HID_228a7 = 0x228a7,
+	BNXT_ULP_CLASS_HID_2b3a7 = 0x2b3a7,
+	BNXT_ULP_CLASS_HID_33ea7 = 0x33ea7,
+	BNXT_ULP_CLASS_HID_3c9a7 = 0x3c9a7,
+	BNXT_ULP_CLASS_HID_223fb = 0x223fb,
+	BNXT_ULP_CLASS_HID_2aefb = 0x2aefb,
+	BNXT_ULP_CLASS_HID_339fb = 0x339fb,
+	BNXT_ULP_CLASS_HID_3c4fb = 0x3c4fb,
+	BNXT_ULP_CLASS_HID_236cb = 0x236cb,
+	BNXT_ULP_CLASS_HID_2c1cb = 0x2c1cb,
+	BNXT_ULP_CLASS_HID_34ccb = 0x34ccb,
+	BNXT_ULP_CLASS_HID_3d7cb = 0x3d7cb,
+	BNXT_ULP_CLASS_HID_202bf = 0x202bf,
+	BNXT_ULP_CLASS_HID_28dbf = 0x28dbf,
+	BNXT_ULP_CLASS_HID_318bf = 0x318bf,
+	BNXT_ULP_CLASS_HID_3a3bf = 0x3a3bf,
+	BNXT_ULP_CLASS_HID_24c1b = 0x24c1b,
+	BNXT_ULP_CLASS_HID_2d71b = 0x2d71b,
+	BNXT_ULP_CLASS_HID_3056f = 0x3056f,
+	BNXT_ULP_CLASS_HID_3906f = 0x3906f,
+	BNXT_ULP_CLASS_HID_2476f = 0x2476f,
+	BNXT_ULP_CLASS_HID_2d26f = 0x2d26f,
+	BNXT_ULP_CLASS_HID_300a3 = 0x300a3,
+	BNXT_ULP_CLASS_HID_38ba3 = 0x38ba3,
+	BNXT_ULP_CLASS_HID_25abf = 0x25abf,
+	BNXT_ULP_CLASS_HID_288f3 = 0x288f3,
+	BNXT_ULP_CLASS_HID_313f3 = 0x313f3,
+	BNXT_ULP_CLASS_HID_39ef3 = 0x39ef3,
+	BNXT_ULP_CLASS_HID_24b1f = 0x24b1f,
+	BNXT_ULP_CLASS_HID_2d61f = 0x2d61f,
+	BNXT_ULP_CLASS_HID_30453 = 0x30453,
+	BNXT_ULP_CLASS_HID_38f53 = 0x38f53,
+	BNXT_ULP_CLASS_HID_237cf = 0x237cf,
+	BNXT_ULP_CLASS_HID_2c2cf = 0x2c2cf,
+	BNXT_ULP_CLASS_HID_34dcf = 0x34dcf,
+	BNXT_ULP_CLASS_HID_3d8cf = 0x3d8cf,
+	BNXT_ULP_CLASS_HID_23303 = 0x23303,
+	BNXT_ULP_CLASS_HID_2be03 = 0x2be03,
+	BNXT_ULP_CLASS_HID_34903 = 0x34903,
+	BNXT_ULP_CLASS_HID_3d403 = 0x3d403,
+	BNXT_ULP_CLASS_HID_24653 = 0x24653,
+	BNXT_ULP_CLASS_HID_2d153 = 0x2d153,
+	BNXT_ULP_CLASS_HID_35c53 = 0x35c53,
+	BNXT_ULP_CLASS_HID_38aa7 = 0x38aa7,
+	BNXT_ULP_CLASS_HID_211c7 = 0x211c7,
+	BNXT_ULP_CLASS_HID_29cc7 = 0x29cc7,
+	BNXT_ULP_CLASS_HID_327c7 = 0x327c7,
+	BNXT_ULP_CLASS_HID_3b2c7 = 0x3b2c7,
+	BNXT_ULP_CLASS_HID_25ba3 = 0x25ba3,
+	BNXT_ULP_CLASS_HID_289f7 = 0x289f7,
+	BNXT_ULP_CLASS_HID_314f7 = 0x314f7,
+	BNXT_ULP_CLASS_HID_39ff7 = 0x39ff7,
+	BNXT_ULP_CLASS_HID_256f7 = 0x256f7,
+	BNXT_ULP_CLASS_HID_284cb = 0x284cb,
+	BNXT_ULP_CLASS_HID_30fcb = 0x30fcb,
+	BNXT_ULP_CLASS_HID_39acb = 0x39acb,
+	BNXT_ULP_CLASS_HID_20d1b = 0x20d1b,
+	BNXT_ULP_CLASS_HID_2981b = 0x2981b,
+	BNXT_ULP_CLASS_HID_3231b = 0x3231b,
+	BNXT_ULP_CLASS_HID_3ae1b = 0x3ae1b,
+	BNXT_ULP_CLASS_HID_235bb = 0x235bb,
+	BNXT_ULP_CLASS_HID_2c0bb = 0x2c0bb,
+	BNXT_ULP_CLASS_HID_34bbb = 0x34bbb,
+	BNXT_ULP_CLASS_HID_3d6bb = 0x3d6bb,
+	BNXT_ULP_CLASS_HID_2226b = 0x2226b,
+	BNXT_ULP_CLASS_HID_2ad6b = 0x2ad6b,
+	BNXT_ULP_CLASS_HID_3386b = 0x3386b,
+	BNXT_ULP_CLASS_HID_3c36b = 0x3c36b,
+	BNXT_ULP_CLASS_HID_21dbf = 0x21dbf,
+	BNXT_ULP_CLASS_HID_2a8bf = 0x2a8bf,
+	BNXT_ULP_CLASS_HID_333bf = 0x333bf,
+	BNXT_ULP_CLASS_HID_3bebf = 0x3bebf,
+	BNXT_ULP_CLASS_HID_2308f = 0x2308f,
+	BNXT_ULP_CLASS_HID_2bb8f = 0x2bb8f,
+	BNXT_ULP_CLASS_HID_3468f = 0x3468f,
+	BNXT_ULP_CLASS_HID_3d18f = 0x3d18f,
+	BNXT_ULP_CLASS_HID_2592f = 0x2592f,
+	BNXT_ULP_CLASS_HID_28763 = 0x28763,
+	BNXT_ULP_CLASS_HID_31263 = 0x31263,
+	BNXT_ULP_CLASS_HID_39d63 = 0x39d63,
+	BNXT_ULP_CLASS_HID_245df = 0x245df,
+	BNXT_ULP_CLASS_HID_2d0df = 0x2d0df,
+	BNXT_ULP_CLASS_HID_35bdf = 0x35bdf,
+	BNXT_ULP_CLASS_HID_38a13 = 0x38a13,
+	BNXT_ULP_CLASS_HID_24113 = 0x24113,
+	BNXT_ULP_CLASS_HID_2cc13 = 0x2cc13,
+	BNXT_ULP_CLASS_HID_35713 = 0x35713,
+	BNXT_ULP_CLASS_HID_38567 = 0x38567,
+	BNXT_ULP_CLASS_HID_25463 = 0x25463,
+	BNXT_ULP_CLASS_HID_282b7 = 0x282b7,
+	BNXT_ULP_CLASS_HID_30db7 = 0x30db7,
+	BNXT_ULP_CLASS_HID_398b7 = 0x398b7,
+	BNXT_ULP_CLASS_HID_244c3 = 0x244c3,
+	BNXT_ULP_CLASS_HID_2cfc3 = 0x2cfc3,
+	BNXT_ULP_CLASS_HID_35ac3 = 0x35ac3,
+	BNXT_ULP_CLASS_HID_38917 = 0x38917,
+	BNXT_ULP_CLASS_HID_231f3 = 0x231f3,
+	BNXT_ULP_CLASS_HID_2bcf3 = 0x2bcf3,
+	BNXT_ULP_CLASS_HID_347f3 = 0x347f3,
+	BNXT_ULP_CLASS_HID_3d2f3 = 0x3d2f3,
+	BNXT_ULP_CLASS_HID_22cc7 = 0x22cc7,
+	BNXT_ULP_CLASS_HID_2b7c7 = 0x2b7c7,
+	BNXT_ULP_CLASS_HID_342c7 = 0x342c7,
+	BNXT_ULP_CLASS_HID_3cdc7 = 0x3cdc7,
+	BNXT_ULP_CLASS_HID_24017 = 0x24017,
+	BNXT_ULP_CLASS_HID_2cb17 = 0x2cb17,
+	BNXT_ULP_CLASS_HID_35617 = 0x35617,
+	BNXT_ULP_CLASS_HID_3846b = 0x3846b,
+	BNXT_ULP_CLASS_HID_20b8b = 0x20b8b,
+	BNXT_ULP_CLASS_HID_2968b = 0x2968b,
+	BNXT_ULP_CLASS_HID_3218b = 0x3218b,
+	BNXT_ULP_CLASS_HID_3ac8b = 0x3ac8b,
+	BNXT_ULP_CLASS_HID_25567 = 0x25567,
+	BNXT_ULP_CLASS_HID_283bb = 0x283bb,
+	BNXT_ULP_CLASS_HID_30ebb = 0x30ebb,
+	BNXT_ULP_CLASS_HID_399bb = 0x399bb,
+	BNXT_ULP_CLASS_HID_250bb = 0x250bb,
+	BNXT_ULP_CLASS_HID_2dbbb = 0x2dbbb,
+	BNXT_ULP_CLASS_HID_3098f = 0x3098f,
+	BNXT_ULP_CLASS_HID_3948f = 0x3948f,
+	BNXT_ULP_CLASS_HID_206df = 0x206df,
+	BNXT_ULP_CLASS_HID_291df = 0x291df,
+	BNXT_ULP_CLASS_HID_31cdf = 0x31cdf,
+	BNXT_ULP_CLASS_HID_3a7df = 0x3a7df,
+	BNXT_ULP_CLASS_HID_22f7f = 0x22f7f,
+	BNXT_ULP_CLASS_HID_2ba7f = 0x2ba7f,
+	BNXT_ULP_CLASS_HID_3457f = 0x3457f,
+	BNXT_ULP_CLASS_HID_3d07f = 0x3d07f,
+	BNXT_ULP_CLASS_HID_21c2f = 0x21c2f,
+	BNXT_ULP_CLASS_HID_2a72f = 0x2a72f,
+	BNXT_ULP_CLASS_HID_3322f = 0x3322f,
+	BNXT_ULP_CLASS_HID_3bd2f = 0x3bd2f,
+	BNXT_ULP_CLASS_HID_21763 = 0x21763,
+	BNXT_ULP_CLASS_HID_2a263 = 0x2a263,
+	BNXT_ULP_CLASS_HID_32d63 = 0x32d63,
+	BNXT_ULP_CLASS_HID_3b863 = 0x3b863,
+	BNXT_ULP_CLASS_HID_22ab3 = 0x22ab3,
+	BNXT_ULP_CLASS_HID_2b5b3 = 0x2b5b3,
+	BNXT_ULP_CLASS_HID_340b3 = 0x340b3,
+	BNXT_ULP_CLASS_HID_3cbb3 = 0x3cbb3,
+	BNXT_ULP_CLASS_HID_252d3 = 0x252d3,
+	BNXT_ULP_CLASS_HID_28127 = 0x28127,
+	BNXT_ULP_CLASS_HID_30c27 = 0x30c27,
+	BNXT_ULP_CLASS_HID_39727 = 0x39727,
+	BNXT_ULP_CLASS_HID_23f83 = 0x23f83,
+	BNXT_ULP_CLASS_HID_2ca83 = 0x2ca83,
+	BNXT_ULP_CLASS_HID_35583 = 0x35583,
+	BNXT_ULP_CLASS_HID_383d7 = 0x383d7,
+	BNXT_ULP_CLASS_HID_23ad7 = 0x23ad7,
+	BNXT_ULP_CLASS_HID_2c5d7 = 0x2c5d7,
+	BNXT_ULP_CLASS_HID_350d7 = 0x350d7,
+	BNXT_ULP_CLASS_HID_3dbd7 = 0x3dbd7,
+	BNXT_ULP_CLASS_HID_24e27 = 0x24e27,
+	BNXT_ULP_CLASS_HID_2d927 = 0x2d927,
+	BNXT_ULP_CLASS_HID_3077b = 0x3077b,
+	BNXT_ULP_CLASS_HID_3927b = 0x3927b,
+	BNXT_ULP_CLASS_HID_2320f = 0x2320f,
+	BNXT_ULP_CLASS_HID_2bd0f = 0x2bd0f,
+	BNXT_ULP_CLASS_HID_3480f = 0x3480f,
+	BNXT_ULP_CLASS_HID_3d30f = 0x3d30f,
+	BNXT_ULP_CLASS_HID_21f3f = 0x21f3f,
+	BNXT_ULP_CLASS_HID_2aa3f = 0x2aa3f,
+	BNXT_ULP_CLASS_HID_3353f = 0x3353f,
+	BNXT_ULP_CLASS_HID_3c03f = 0x3c03f,
+	BNXT_ULP_CLASS_HID_21a73 = 0x21a73,
+	BNXT_ULP_CLASS_HID_2a573 = 0x2a573,
+	BNXT_ULP_CLASS_HID_33073 = 0x33073,
+	BNXT_ULP_CLASS_HID_3bb73 = 0x3bb73,
+	BNXT_ULP_CLASS_HID_22d43 = 0x22d43,
+	BNXT_ULP_CLASS_HID_2b843 = 0x2b843,
+	BNXT_ULP_CLASS_HID_34343 = 0x34343,
+	BNXT_ULP_CLASS_HID_3ce43 = 0x3ce43,
+	BNXT_ULP_CLASS_HID_255e3 = 0x255e3,
+	BNXT_ULP_CLASS_HID_28437 = 0x28437,
+	BNXT_ULP_CLASS_HID_30f37 = 0x30f37,
+	BNXT_ULP_CLASS_HID_39a37 = 0x39a37,
+	BNXT_ULP_CLASS_HID_24293 = 0x24293,
+	BNXT_ULP_CLASS_HID_2cd93 = 0x2cd93,
+	BNXT_ULP_CLASS_HID_35893 = 0x35893,
+	BNXT_ULP_CLASS_HID_386e7 = 0x386e7,
+	BNXT_ULP_CLASS_HID_23de7 = 0x23de7,
+	BNXT_ULP_CLASS_HID_2c8e7 = 0x2c8e7,
+	BNXT_ULP_CLASS_HID_353e7 = 0x353e7,
+	BNXT_ULP_CLASS_HID_3823b = 0x3823b,
+	BNXT_ULP_CLASS_HID_25137 = 0x25137,
+	BNXT_ULP_CLASS_HID_2dc37 = 0x2dc37,
+	BNXT_ULP_CLASS_HID_30a0b = 0x30a0b,
+	BNXT_ULP_CLASS_HID_3950b = 0x3950b,
+	BNXT_ULP_CLASS_HID_22c33 = 0x22c33,
+	BNXT_ULP_CLASS_HID_2b733 = 0x2b733,
+	BNXT_ULP_CLASS_HID_34233 = 0x34233,
+	BNXT_ULP_CLASS_HID_3cd33 = 0x3cd33,
+	BNXT_ULP_CLASS_HID_218e3 = 0x218e3,
+	BNXT_ULP_CLASS_HID_2a3e3 = 0x2a3e3,
+	BNXT_ULP_CLASS_HID_32ee3 = 0x32ee3,
+	BNXT_ULP_CLASS_HID_3b9e3 = 0x3b9e3,
+	BNXT_ULP_CLASS_HID_21437 = 0x21437,
+	BNXT_ULP_CLASS_HID_29f37 = 0x29f37,
+	BNXT_ULP_CLASS_HID_32a37 = 0x32a37,
+	BNXT_ULP_CLASS_HID_3b537 = 0x3b537,
+	BNXT_ULP_CLASS_HID_22707 = 0x22707,
+	BNXT_ULP_CLASS_HID_2b207 = 0x2b207,
+	BNXT_ULP_CLASS_HID_33d07 = 0x33d07,
+	BNXT_ULP_CLASS_HID_3c807 = 0x3c807,
+	BNXT_ULP_CLASS_HID_24fa7 = 0x24fa7,
+	BNXT_ULP_CLASS_HID_2daa7 = 0x2daa7,
+	BNXT_ULP_CLASS_HID_308fb = 0x308fb,
+	BNXT_ULP_CLASS_HID_393fb = 0x393fb,
+	BNXT_ULP_CLASS_HID_23c57 = 0x23c57,
+	BNXT_ULP_CLASS_HID_2c757 = 0x2c757,
+	BNXT_ULP_CLASS_HID_35257 = 0x35257,
+	BNXT_ULP_CLASS_HID_380ab = 0x380ab,
+	BNXT_ULP_CLASS_HID_237ab = 0x237ab,
+	BNXT_ULP_CLASS_HID_2c2ab = 0x2c2ab,
+	BNXT_ULP_CLASS_HID_34dab = 0x34dab,
+	BNXT_ULP_CLASS_HID_3d8ab = 0x3d8ab,
+	BNXT_ULP_CLASS_HID_24afb = 0x24afb,
+	BNXT_ULP_CLASS_HID_2d5fb = 0x2d5fb,
+	BNXT_ULP_CLASS_HID_303cf = 0x303cf,
+	BNXT_ULP_CLASS_HID_38ecf = 0x38ecf,
+	BNXT_ULP_CLASS_HID_255b = 0x255b,
+	BNXT_ULP_CLASS_HID_2b97 = 0x2b97,
+	BNXT_ULP_CLASS_HID_4f0b = 0x4f0b,
+	BNXT_ULP_CLASS_HID_1633 = 0x1633,
+	BNXT_ULP_CLASS_HID_39a7 = 0x39a7,
+	BNXT_ULP_CLASS_HID_48cf = 0x48cf,
+	BNXT_ULP_CLASS_HID_0ff7 = 0x0ff7,
+	BNXT_ULP_CLASS_HID_336b = 0x336b,
+	BNXT_ULP_CLASS_HID_257f7 = 0x257f7,
+	BNXT_ULP_CLASS_HID_2858b = 0x2858b,
+	BNXT_ULP_CLASS_HID_3108b = 0x3108b,
+	BNXT_ULP_CLASS_HID_39b8b = 0x39b8b,
+	BNXT_ULP_CLASS_HID_24427 = 0x24427,
+	BNXT_ULP_CLASS_HID_2cf27 = 0x2cf27,
+	BNXT_ULP_CLASS_HID_35a27 = 0x35a27,
+	BNXT_ULP_CLASS_HID_388fb = 0x388fb,
+	BNXT_ULP_CLASS_HID_23ffb = 0x23ffb,
+	BNXT_ULP_CLASS_HID_2cafb = 0x2cafb,
+	BNXT_ULP_CLASS_HID_355fb = 0x355fb,
+	BNXT_ULP_CLASS_HID_3838f = 0x3838f,
+	BNXT_ULP_CLASS_HID_2528b = 0x2528b,
+	BNXT_ULP_CLASS_HID_2815f = 0x2815f,
+	BNXT_ULP_CLASS_HID_30c5f = 0x30c5f,
+	BNXT_ULP_CLASS_HID_3975f = 0x3975f,
+	BNXT_ULP_CLASS_HID_21e3f = 0x21e3f,
+	BNXT_ULP_CLASS_HID_2a93f = 0x2a93f,
+	BNXT_ULP_CLASS_HID_3343f = 0x3343f,
+	BNXT_ULP_CLASS_HID_3bf3f = 0x3bf3f,
+	BNXT_ULP_CLASS_HID_20b6f = 0x20b6f,
+	BNXT_ULP_CLASS_HID_2966f = 0x2966f,
+	BNXT_ULP_CLASS_HID_3216f = 0x3216f,
+	BNXT_ULP_CLASS_HID_3ac6f = 0x3ac6f,
+	BNXT_ULP_CLASS_HID_20623 = 0x20623,
+	BNXT_ULP_CLASS_HID_29123 = 0x29123,
+	BNXT_ULP_CLASS_HID_31c23 = 0x31c23,
+	BNXT_ULP_CLASS_HID_3a723 = 0x3a723,
+	BNXT_ULP_CLASS_HID_219f3 = 0x219f3,
+	BNXT_ULP_CLASS_HID_2a4f3 = 0x2a4f3,
+	BNXT_ULP_CLASS_HID_32ff3 = 0x32ff3,
+	BNXT_ULP_CLASS_HID_3baf3 = 0x3baf3,
+	BNXT_ULP_CLASS_HID_24253 = 0x24253,
+	BNXT_ULP_CLASS_HID_2cd53 = 0x2cd53,
+	BNXT_ULP_CLASS_HID_35853 = 0x35853,
+	BNXT_ULP_CLASS_HID_38667 = 0x38667,
+	BNXT_ULP_CLASS_HID_22e83 = 0x22e83,
+	BNXT_ULP_CLASS_HID_2b983 = 0x2b983,
+	BNXT_ULP_CLASS_HID_34483 = 0x34483,
+	BNXT_ULP_CLASS_HID_3cf83 = 0x3cf83,
+	BNXT_ULP_CLASS_HID_22a57 = 0x22a57,
+	BNXT_ULP_CLASS_HID_2b557 = 0x2b557,
+	BNXT_ULP_CLASS_HID_34057 = 0x34057,
+	BNXT_ULP_CLASS_HID_3cb57 = 0x3cb57,
+	BNXT_ULP_CLASS_HID_23d67 = 0x23d67,
+	BNXT_ULP_CLASS_HID_2c867 = 0x2c867,
+	BNXT_ULP_CLASS_HID_35367 = 0x35367,
+	BNXT_ULP_CLASS_HID_3813b = 0x3813b,
+	BNXT_ULP_CLASS_HID_2089b = 0x2089b,
+	BNXT_ULP_CLASS_HID_2939b = 0x2939b,
+	BNXT_ULP_CLASS_HID_31e9b = 0x31e9b,
+	BNXT_ULP_CLASS_HID_3a99b = 0x3a99b,
+	BNXT_ULP_CLASS_HID_25237 = 0x25237,
+	BNXT_ULP_CLASS_HID_280cb = 0x280cb,
+	BNXT_ULP_CLASS_HID_30bcb = 0x30bcb,
+	BNXT_ULP_CLASS_HID_396cb = 0x396cb,
+	BNXT_ULP_CLASS_HID_24dcb = 0x24dcb,
+	BNXT_ULP_CLASS_HID_2d8cb = 0x2d8cb,
+	BNXT_ULP_CLASS_HID_3069f = 0x3069f,
+	BNXT_ULP_CLASS_HID_3919f = 0x3919f,
+	BNXT_ULP_CLASS_HID_203af = 0x203af,
+	BNXT_ULP_CLASS_HID_28eaf = 0x28eaf,
+	BNXT_ULP_CLASS_HID_319af = 0x319af,
+	BNXT_ULP_CLASS_HID_3a4af = 0x3a4af,
+	BNXT_ULP_CLASS_HID_2513b = 0x2513b,
+	BNXT_ULP_CLASS_HID_2dc3b = 0x2dc3b,
+	BNXT_ULP_CLASS_HID_30acf = 0x30acf,
+	BNXT_ULP_CLASS_HID_395cf = 0x395cf,
+	BNXT_ULP_CLASS_HID_23e6b = 0x23e6b,
+	BNXT_ULP_CLASS_HID_2c96b = 0x2c96b,
+	BNXT_ULP_CLASS_HID_3546b = 0x3546b,
+	BNXT_ULP_CLASS_HID_3823f = 0x3823f,
+	BNXT_ULP_CLASS_HID_2393f = 0x2393f,
+	BNXT_ULP_CLASS_HID_2c43f = 0x2c43f,
+	BNXT_ULP_CLASS_HID_34f3f = 0x34f3f,
+	BNXT_ULP_CLASS_HID_3da3f = 0x3da3f,
+	BNXT_ULP_CLASS_HID_24ccf = 0x24ccf,
+	BNXT_ULP_CLASS_HID_2d7cf = 0x2d7cf,
+	BNXT_ULP_CLASS_HID_30583 = 0x30583,
+	BNXT_ULP_CLASS_HID_39083 = 0x39083,
+	BNXT_ULP_CLASS_HID_21863 = 0x21863,
+	BNXT_ULP_CLASS_HID_2a363 = 0x2a363,
+	BNXT_ULP_CLASS_HID_32e63 = 0x32e63,
+	BNXT_ULP_CLASS_HID_3b963 = 0x3b963,
+	BNXT_ULP_CLASS_HID_20553 = 0x20553,
+	BNXT_ULP_CLASS_HID_29053 = 0x29053,
+	BNXT_ULP_CLASS_HID_31b53 = 0x31b53,
+	BNXT_ULP_CLASS_HID_3a653 = 0x3a653,
+	BNXT_ULP_CLASS_HID_20067 = 0x20067,
+	BNXT_ULP_CLASS_HID_28b67 = 0x28b67,
+	BNXT_ULP_CLASS_HID_31667 = 0x31667,
+	BNXT_ULP_CLASS_HID_3a167 = 0x3a167,
+	BNXT_ULP_CLASS_HID_21337 = 0x21337,
+	BNXT_ULP_CLASS_HID_29e37 = 0x29e37,
+	BNXT_ULP_CLASS_HID_32937 = 0x32937,
+	BNXT_ULP_CLASS_HID_3b437 = 0x3b437,
+	BNXT_ULP_CLASS_HID_23b97 = 0x23b97,
+	BNXT_ULP_CLASS_HID_2c697 = 0x2c697,
+	BNXT_ULP_CLASS_HID_35197 = 0x35197,
+	BNXT_ULP_CLASS_HID_3dc97 = 0x3dc97,
+	BNXT_ULP_CLASS_HID_228c7 = 0x228c7,
+	BNXT_ULP_CLASS_HID_2b3c7 = 0x2b3c7,
+	BNXT_ULP_CLASS_HID_33ec7 = 0x33ec7,
+	BNXT_ULP_CLASS_HID_3c9c7 = 0x3c9c7,
+	BNXT_ULP_CLASS_HID_2239b = 0x2239b,
+	BNXT_ULP_CLASS_HID_2ae9b = 0x2ae9b,
+	BNXT_ULP_CLASS_HID_3399b = 0x3399b,
+	BNXT_ULP_CLASS_HID_3c49b = 0x3c49b,
+	BNXT_ULP_CLASS_HID_236ab = 0x236ab,
+	BNXT_ULP_CLASS_HID_2c1ab = 0x2c1ab,
+	BNXT_ULP_CLASS_HID_34cab = 0x34cab,
+	BNXT_ULP_CLASS_HID_3d7ab = 0x3d7ab,
+	BNXT_ULP_CLASS_HID_202df = 0x202df,
+	BNXT_ULP_CLASS_HID_28ddf = 0x28ddf,
+	BNXT_ULP_CLASS_HID_318df = 0x318df,
+	BNXT_ULP_CLASS_HID_3a3df = 0x3a3df,
+	BNXT_ULP_CLASS_HID_24c7b = 0x24c7b,
+	BNXT_ULP_CLASS_HID_2d77b = 0x2d77b,
+	BNXT_ULP_CLASS_HID_3050f = 0x3050f,
+	BNXT_ULP_CLASS_HID_3900f = 0x3900f,
+	BNXT_ULP_CLASS_HID_2470f = 0x2470f,
+	BNXT_ULP_CLASS_HID_2d20f = 0x2d20f,
+	BNXT_ULP_CLASS_HID_300c3 = 0x300c3,
+	BNXT_ULP_CLASS_HID_38bc3 = 0x38bc3,
+	BNXT_ULP_CLASS_HID_25adf = 0x25adf,
+	BNXT_ULP_CLASS_HID_28893 = 0x28893,
+	BNXT_ULP_CLASS_HID_31393 = 0x31393,
+	BNXT_ULP_CLASS_HID_39e93 = 0x39e93,
+	BNXT_ULP_CLASS_HID_24b7f = 0x24b7f,
+	BNXT_ULP_CLASS_HID_2d67f = 0x2d67f,
+	BNXT_ULP_CLASS_HID_30433 = 0x30433,
+	BNXT_ULP_CLASS_HID_38f33 = 0x38f33,
+	BNXT_ULP_CLASS_HID_237af = 0x237af,
+	BNXT_ULP_CLASS_HID_2c2af = 0x2c2af,
+	BNXT_ULP_CLASS_HID_34daf = 0x34daf,
+	BNXT_ULP_CLASS_HID_3d8af = 0x3d8af,
+	BNXT_ULP_CLASS_HID_23363 = 0x23363,
+	BNXT_ULP_CLASS_HID_2be63 = 0x2be63,
+	BNXT_ULP_CLASS_HID_34963 = 0x34963,
+	BNXT_ULP_CLASS_HID_3d463 = 0x3d463,
+	BNXT_ULP_CLASS_HID_24633 = 0x24633,
+	BNXT_ULP_CLASS_HID_2d133 = 0x2d133,
+	BNXT_ULP_CLASS_HID_35c33 = 0x35c33,
+	BNXT_ULP_CLASS_HID_38ac7 = 0x38ac7,
+	BNXT_ULP_CLASS_HID_211a7 = 0x211a7,
+	BNXT_ULP_CLASS_HID_29ca7 = 0x29ca7,
+	BNXT_ULP_CLASS_HID_327a7 = 0x327a7,
+	BNXT_ULP_CLASS_HID_3b2a7 = 0x3b2a7,
+	BNXT_ULP_CLASS_HID_25bc3 = 0x25bc3,
+	BNXT_ULP_CLASS_HID_28997 = 0x28997,
+	BNXT_ULP_CLASS_HID_31497 = 0x31497,
+	BNXT_ULP_CLASS_HID_39f97 = 0x39f97,
+	BNXT_ULP_CLASS_HID_25697 = 0x25697,
+	BNXT_ULP_CLASS_HID_284ab = 0x284ab,
+	BNXT_ULP_CLASS_HID_30fab = 0x30fab,
+	BNXT_ULP_CLASS_HID_39aab = 0x39aab,
+	BNXT_ULP_CLASS_HID_20d7b = 0x20d7b,
+	BNXT_ULP_CLASS_HID_2987b = 0x2987b,
+	BNXT_ULP_CLASS_HID_3237b = 0x3237b,
+	BNXT_ULP_CLASS_HID_3ae7b = 0x3ae7b,
+	BNXT_ULP_CLASS_HID_235db = 0x235db,
+	BNXT_ULP_CLASS_HID_2c0db = 0x2c0db,
+	BNXT_ULP_CLASS_HID_34bdb = 0x34bdb,
+	BNXT_ULP_CLASS_HID_3d6db = 0x3d6db,
+	BNXT_ULP_CLASS_HID_2220b = 0x2220b,
+	BNXT_ULP_CLASS_HID_2ad0b = 0x2ad0b,
+	BNXT_ULP_CLASS_HID_3380b = 0x3380b,
+	BNXT_ULP_CLASS_HID_3c30b = 0x3c30b,
+	BNXT_ULP_CLASS_HID_21ddf = 0x21ddf,
+	BNXT_ULP_CLASS_HID_2a8df = 0x2a8df,
+	BNXT_ULP_CLASS_HID_333df = 0x333df,
+	BNXT_ULP_CLASS_HID_3bedf = 0x3bedf,
+	BNXT_ULP_CLASS_HID_230ef = 0x230ef,
+	BNXT_ULP_CLASS_HID_2bbef = 0x2bbef,
+	BNXT_ULP_CLASS_HID_346ef = 0x346ef,
+	BNXT_ULP_CLASS_HID_3d1ef = 0x3d1ef,
+	BNXT_ULP_CLASS_HID_2594f = 0x2594f,
+	BNXT_ULP_CLASS_HID_28703 = 0x28703,
+	BNXT_ULP_CLASS_HID_31203 = 0x31203,
+	BNXT_ULP_CLASS_HID_39d03 = 0x39d03,
+	BNXT_ULP_CLASS_HID_245bf = 0x245bf,
+	BNXT_ULP_CLASS_HID_2d0bf = 0x2d0bf,
+	BNXT_ULP_CLASS_HID_35bbf = 0x35bbf,
+	BNXT_ULP_CLASS_HID_38a73 = 0x38a73,
+	BNXT_ULP_CLASS_HID_24173 = 0x24173,
+	BNXT_ULP_CLASS_HID_2cc73 = 0x2cc73,
+	BNXT_ULP_CLASS_HID_35773 = 0x35773,
+	BNXT_ULP_CLASS_HID_38507 = 0x38507,
+	BNXT_ULP_CLASS_HID_25403 = 0x25403,
+	BNXT_ULP_CLASS_HID_282d7 = 0x282d7,
+	BNXT_ULP_CLASS_HID_30dd7 = 0x30dd7,
+	BNXT_ULP_CLASS_HID_398d7 = 0x398d7,
+	BNXT_ULP_CLASS_HID_244a3 = 0x244a3,
+	BNXT_ULP_CLASS_HID_2cfa3 = 0x2cfa3,
+	BNXT_ULP_CLASS_HID_35aa3 = 0x35aa3,
+	BNXT_ULP_CLASS_HID_38977 = 0x38977,
+	BNXT_ULP_CLASS_HID_23193 = 0x23193,
+	BNXT_ULP_CLASS_HID_2bc93 = 0x2bc93,
+	BNXT_ULP_CLASS_HID_34793 = 0x34793,
+	BNXT_ULP_CLASS_HID_3d293 = 0x3d293,
+	BNXT_ULP_CLASS_HID_22ca7 = 0x22ca7,
+	BNXT_ULP_CLASS_HID_2b7a7 = 0x2b7a7,
+	BNXT_ULP_CLASS_HID_342a7 = 0x342a7,
+	BNXT_ULP_CLASS_HID_3cda7 = 0x3cda7,
+	BNXT_ULP_CLASS_HID_24077 = 0x24077,
+	BNXT_ULP_CLASS_HID_2cb77 = 0x2cb77,
+	BNXT_ULP_CLASS_HID_35677 = 0x35677,
+	BNXT_ULP_CLASS_HID_3840b = 0x3840b,
+	BNXT_ULP_CLASS_HID_20beb = 0x20beb,
+	BNXT_ULP_CLASS_HID_296eb = 0x296eb,
+	BNXT_ULP_CLASS_HID_321eb = 0x321eb,
+	BNXT_ULP_CLASS_HID_3aceb = 0x3aceb,
+	BNXT_ULP_CLASS_HID_25507 = 0x25507,
+	BNXT_ULP_CLASS_HID_283db = 0x283db,
+	BNXT_ULP_CLASS_HID_30edb = 0x30edb,
+	BNXT_ULP_CLASS_HID_399db = 0x399db,
+	BNXT_ULP_CLASS_HID_250db = 0x250db,
+	BNXT_ULP_CLASS_HID_2dbdb = 0x2dbdb,
+	BNXT_ULP_CLASS_HID_309ef = 0x309ef,
+	BNXT_ULP_CLASS_HID_394ef = 0x394ef,
+	BNXT_ULP_CLASS_HID_206bf = 0x206bf,
+	BNXT_ULP_CLASS_HID_291bf = 0x291bf,
+	BNXT_ULP_CLASS_HID_31cbf = 0x31cbf,
+	BNXT_ULP_CLASS_HID_3a7bf = 0x3a7bf,
+	BNXT_ULP_CLASS_HID_22f1f = 0x22f1f,
+	BNXT_ULP_CLASS_HID_2ba1f = 0x2ba1f,
+	BNXT_ULP_CLASS_HID_3451f = 0x3451f,
+	BNXT_ULP_CLASS_HID_3d01f = 0x3d01f,
+	BNXT_ULP_CLASS_HID_21c4f = 0x21c4f,
+	BNXT_ULP_CLASS_HID_2a74f = 0x2a74f,
+	BNXT_ULP_CLASS_HID_3324f = 0x3324f,
+	BNXT_ULP_CLASS_HID_3bd4f = 0x3bd4f,
+	BNXT_ULP_CLASS_HID_21703 = 0x21703,
+	BNXT_ULP_CLASS_HID_2a203 = 0x2a203,
+	BNXT_ULP_CLASS_HID_32d03 = 0x32d03,
+	BNXT_ULP_CLASS_HID_3b803 = 0x3b803,
+	BNXT_ULP_CLASS_HID_22ad3 = 0x22ad3,
+	BNXT_ULP_CLASS_HID_2b5d3 = 0x2b5d3,
+	BNXT_ULP_CLASS_HID_340d3 = 0x340d3,
+	BNXT_ULP_CLASS_HID_3cbd3 = 0x3cbd3,
+	BNXT_ULP_CLASS_HID_252b3 = 0x252b3,
+	BNXT_ULP_CLASS_HID_28147 = 0x28147,
+	BNXT_ULP_CLASS_HID_30c47 = 0x30c47,
+	BNXT_ULP_CLASS_HID_39747 = 0x39747,
+	BNXT_ULP_CLASS_HID_23fe3 = 0x23fe3,
+	BNXT_ULP_CLASS_HID_2cae3 = 0x2cae3,
+	BNXT_ULP_CLASS_HID_355e3 = 0x355e3,
+	BNXT_ULP_CLASS_HID_383b7 = 0x383b7,
+	BNXT_ULP_CLASS_HID_23ab7 = 0x23ab7,
+	BNXT_ULP_CLASS_HID_2c5b7 = 0x2c5b7,
+	BNXT_ULP_CLASS_HID_350b7 = 0x350b7,
+	BNXT_ULP_CLASS_HID_3dbb7 = 0x3dbb7,
+	BNXT_ULP_CLASS_HID_24e47 = 0x24e47,
+	BNXT_ULP_CLASS_HID_2d947 = 0x2d947,
+	BNXT_ULP_CLASS_HID_3071b = 0x3071b,
+	BNXT_ULP_CLASS_HID_3921b = 0x3921b,
+	BNXT_ULP_CLASS_HID_2326f = 0x2326f,
+	BNXT_ULP_CLASS_HID_2bd6f = 0x2bd6f,
+	BNXT_ULP_CLASS_HID_3486f = 0x3486f,
+	BNXT_ULP_CLASS_HID_3d36f = 0x3d36f,
+	BNXT_ULP_CLASS_HID_21f5f = 0x21f5f,
+	BNXT_ULP_CLASS_HID_2aa5f = 0x2aa5f,
+	BNXT_ULP_CLASS_HID_3355f = 0x3355f,
+	BNXT_ULP_CLASS_HID_3c05f = 0x3c05f,
+	BNXT_ULP_CLASS_HID_21a13 = 0x21a13,
+	BNXT_ULP_CLASS_HID_2a513 = 0x2a513,
+	BNXT_ULP_CLASS_HID_33013 = 0x33013,
+	BNXT_ULP_CLASS_HID_3bb13 = 0x3bb13,
+	BNXT_ULP_CLASS_HID_22d23 = 0x22d23,
+	BNXT_ULP_CLASS_HID_2b823 = 0x2b823,
+	BNXT_ULP_CLASS_HID_34323 = 0x34323,
+	BNXT_ULP_CLASS_HID_3ce23 = 0x3ce23,
+	BNXT_ULP_CLASS_HID_25583 = 0x25583,
+	BNXT_ULP_CLASS_HID_28457 = 0x28457,
+	BNXT_ULP_CLASS_HID_30f57 = 0x30f57,
+	BNXT_ULP_CLASS_HID_39a57 = 0x39a57,
+	BNXT_ULP_CLASS_HID_242f3 = 0x242f3,
+	BNXT_ULP_CLASS_HID_2cdf3 = 0x2cdf3,
+	BNXT_ULP_CLASS_HID_358f3 = 0x358f3,
+	BNXT_ULP_CLASS_HID_38687 = 0x38687,
+	BNXT_ULP_CLASS_HID_23d87 = 0x23d87,
+	BNXT_ULP_CLASS_HID_2c887 = 0x2c887,
+	BNXT_ULP_CLASS_HID_35387 = 0x35387,
+	BNXT_ULP_CLASS_HID_3825b = 0x3825b,
+	BNXT_ULP_CLASS_HID_25157 = 0x25157,
+	BNXT_ULP_CLASS_HID_2dc57 = 0x2dc57,
+	BNXT_ULP_CLASS_HID_30a6b = 0x30a6b,
+	BNXT_ULP_CLASS_HID_3956b = 0x3956b,
+	BNXT_ULP_CLASS_HID_22c53 = 0x22c53,
+	BNXT_ULP_CLASS_HID_2b753 = 0x2b753,
+	BNXT_ULP_CLASS_HID_34253 = 0x34253,
+	BNXT_ULP_CLASS_HID_3cd53 = 0x3cd53,
+	BNXT_ULP_CLASS_HID_21883 = 0x21883,
+	BNXT_ULP_CLASS_HID_2a383 = 0x2a383,
+	BNXT_ULP_CLASS_HID_32e83 = 0x32e83,
+	BNXT_ULP_CLASS_HID_3b983 = 0x3b983,
+	BNXT_ULP_CLASS_HID_21457 = 0x21457,
+	BNXT_ULP_CLASS_HID_29f57 = 0x29f57,
+	BNXT_ULP_CLASS_HID_32a57 = 0x32a57,
+	BNXT_ULP_CLASS_HID_3b557 = 0x3b557,
+	BNXT_ULP_CLASS_HID_22767 = 0x22767,
+	BNXT_ULP_CLASS_HID_2b267 = 0x2b267,
+	BNXT_ULP_CLASS_HID_33d67 = 0x33d67,
+	BNXT_ULP_CLASS_HID_3c867 = 0x3c867,
+	BNXT_ULP_CLASS_HID_24fc7 = 0x24fc7,
+	BNXT_ULP_CLASS_HID_2dac7 = 0x2dac7,
+	BNXT_ULP_CLASS_HID_3089b = 0x3089b,
+	BNXT_ULP_CLASS_HID_3939b = 0x3939b,
+	BNXT_ULP_CLASS_HID_23c37 = 0x23c37,
+	BNXT_ULP_CLASS_HID_2c737 = 0x2c737,
+	BNXT_ULP_CLASS_HID_35237 = 0x35237,
+	BNXT_ULP_CLASS_HID_380cb = 0x380cb,
+	BNXT_ULP_CLASS_HID_237cb = 0x237cb,
+	BNXT_ULP_CLASS_HID_2c2cb = 0x2c2cb,
+	BNXT_ULP_CLASS_HID_34dcb = 0x34dcb,
+	BNXT_ULP_CLASS_HID_3d8cb = 0x3d8cb,
+	BNXT_ULP_CLASS_HID_24a9b = 0x24a9b,
+	BNXT_ULP_CLASS_HID_2d59b = 0x2d59b,
+	BNXT_ULP_CLASS_HID_303af = 0x303af,
+	BNXT_ULP_CLASS_HID_38eaf = 0x38eaf,
+	BNXT_ULP_CLASS_HID_253b = 0x253b,
+	BNXT_ULP_CLASS_HID_2bf7 = 0x2bf7,
+	BNXT_ULP_CLASS_HID_4f6b = 0x4f6b,
+	BNXT_ULP_CLASS_HID_1653 = 0x1653,
+	BNXT_ULP_CLASS_HID_39c7 = 0x39c7,
+	BNXT_ULP_CLASS_HID_48af = 0x48af,
+	BNXT_ULP_CLASS_HID_0f97 = 0x0f97,
+	BNXT_ULP_CLASS_HID_330b = 0x330b,
+	BNXT_ULP_CLASS_HID_374e = 0x374e,
+	BNXT_ULP_CLASS_HID_11ee = 0x11ee,
+	BNXT_ULP_CLASS_HID_423a = 0x423a,
+	BNXT_ULP_CLASS_HID_0cd6 = 0x0cd6,
+	BNXT_ULP_CLASS_HID_310a = 0x310a,
+	BNXT_ULP_CLASS_HID_469e = 0x469e,
+	BNXT_ULP_CLASS_HID_5ce6 = 0x5ce6,
+	BNXT_ULP_CLASS_HID_0692 = 0x0692,
+	BNXT_ULP_CLASS_HID_1c7e = 0x1c7e,
+	BNXT_ULP_CLASS_HID_55c2 = 0x55c2,
+	BNXT_ULP_CLASS_HID_2b2a = 0x2b2a,
+	BNXT_ULP_CLASS_HID_15c6 = 0x15c6,
+	BNXT_ULP_CLASS_HID_163a = 0x163a,
+	BNXT_ULP_CLASS_HID_2f8e = 0x2f8e,
+	BNXT_ULP_CLASS_HID_2516 = 0x2516,
+	BNXT_ULP_CLASS_HID_4b76 = 0x4b76,
+	BNXT_ULP_CLASS_HID_10e6 = 0x10e6,
+	BNXT_ULP_CLASS_HID_264a = 0x264a,
+	BNXT_ULP_CLASS_HID_3fd2 = 0x3fd2,
+	BNXT_ULP_CLASS_HID_4532 = 0x4532,
+	BNXT_ULP_CLASS_HID_4996 = 0x4996,
+	BNXT_ULP_CLASS_HID_2036 = 0x2036,
+	BNXT_ULP_CLASS_HID_399e = 0x399e,
+	BNXT_ULP_CLASS_HID_5ffe = 0x5ffe,
+	BNXT_ULP_CLASS_HID_34fe = 0x34fe,
+	BNXT_ULP_CLASS_HID_3a32 = 0x3a32,
+	BNXT_ULP_CLASS_HID_376e = 0x376e,
+	BNXT_ULP_CLASS_HID_12d6e = 0x12d6e,
+	BNXT_ULP_CLASS_HID_2436e = 0x2436e,
+	BNXT_ULP_CLASS_HID_31dba = 0x31dba,
+	BNXT_ULP_CLASS_HID_11ce = 0x11ce,
+	BNXT_ULP_CLASS_HID_107ce = 0x107ce,
+	BNXT_ULP_CLASS_HID_23dce = 0x23dce,
+	BNXT_ULP_CLASS_HID_353ce = 0x353ce,
+	BNXT_ULP_CLASS_HID_421a = 0x421a,
+	BNXT_ULP_CLASS_HID_11d56 = 0x11d56,
+	BNXT_ULP_CLASS_HID_23356 = 0x23356,
+	BNXT_ULP_CLASS_HID_32956 = 0x32956,
+	BNXT_ULP_CLASS_HID_0cf6 = 0x0cf6,
+	BNXT_ULP_CLASS_HID_122f6 = 0x122f6,
+	BNXT_ULP_CLASS_HID_258f6 = 0x258f6,
+	BNXT_ULP_CLASS_HID_313c2 = 0x313c2,
+	BNXT_ULP_CLASS_HID_312a = 0x312a,
+	BNXT_ULP_CLASS_HID_1272a = 0x1272a,
+	BNXT_ULP_CLASS_HID_25d2a = 0x25d2a,
+	BNXT_ULP_CLASS_HID_31466 = 0x31466,
+	BNXT_ULP_CLASS_HID_46be = 0x46be,
+	BNXT_ULP_CLASS_HID_1018a = 0x1018a,
+	BNXT_ULP_CLASS_HID_2378a = 0x2378a,
+	BNXT_ULP_CLASS_HID_32d8a = 0x32d8a,
+	BNXT_ULP_CLASS_HID_5cc6 = 0x5cc6,
+	BNXT_ULP_CLASS_HID_11712 = 0x11712,
+	BNXT_ULP_CLASS_HID_20d12 = 0x20d12,
+	BNXT_ULP_CLASS_HID_32312 = 0x32312,
+	BNXT_ULP_CLASS_HID_06b2 = 0x06b2,
+	BNXT_ULP_CLASS_HID_13cb2 = 0x13cb2,
+	BNXT_ULP_CLASS_HID_252b2 = 0x252b2,
+	BNXT_ULP_CLASS_HID_348b2 = 0x348b2,
+	BNXT_ULP_CLASS_HID_1c5e = 0x1c5e,
+	BNXT_ULP_CLASS_HID_1325e = 0x1325e,
+	BNXT_ULP_CLASS_HID_2285e = 0x2285e,
+	BNXT_ULP_CLASS_HID_35e5e = 0x35e5e,
+	BNXT_ULP_CLASS_HID_55e2 = 0x55e2,
+	BNXT_ULP_CLASS_HID_14be2 = 0x14be2,
+	BNXT_ULP_CLASS_HID_2023e = 0x2023e,
+	BNXT_ULP_CLASS_HID_3383e = 0x3383e,
+	BNXT_ULP_CLASS_HID_2b0a = 0x2b0a,
+	BNXT_ULP_CLASS_HID_1410a = 0x1410a,
+	BNXT_ULP_CLASS_HID_21846 = 0x21846,
+	BNXT_ULP_CLASS_HID_30e46 = 0x30e46,
+	BNXT_ULP_CLASS_HID_15e6 = 0x15e6,
+	BNXT_ULP_CLASS_HID_10be6 = 0x10be6,
+	BNXT_ULP_CLASS_HID_221e6 = 0x221e6,
+	BNXT_ULP_CLASS_HID_357e6 = 0x357e6,
+	BNXT_ULP_CLASS_HID_161a = 0x161a,
+	BNXT_ULP_CLASS_HID_10c1a = 0x10c1a,
+	BNXT_ULP_CLASS_HID_2221a = 0x2221a,
+	BNXT_ULP_CLASS_HID_3581a = 0x3581a,
+	BNXT_ULP_CLASS_HID_2fae = 0x2fae,
+	BNXT_ULP_CLASS_HID_145ae = 0x145ae,
+	BNXT_ULP_CLASS_HID_21cfa = 0x21cfa,
+	BNXT_ULP_CLASS_HID_332fa = 0x332fa,
+	BNXT_ULP_CLASS_HID_2536 = 0x2536,
+	BNXT_ULP_CLASS_HID_15b36 = 0x15b36,
+	BNXT_ULP_CLASS_HID_21202 = 0x21202,
+	BNXT_ULP_CLASS_HID_30802 = 0x30802,
+	BNXT_ULP_CLASS_HID_4b56 = 0x4b56,
+	BNXT_ULP_CLASS_HID_105a2 = 0x105a2,
+	BNXT_ULP_CLASS_HID_23ba2 = 0x23ba2,
+	BNXT_ULP_CLASS_HID_351a2 = 0x351a2,
+	BNXT_ULP_CLASS_HID_10c6 = 0x10c6,
+	BNXT_ULP_CLASS_HID_106c6 = 0x106c6,
+	BNXT_ULP_CLASS_HID_23cc6 = 0x23cc6,
+	BNXT_ULP_CLASS_HID_352c6 = 0x352c6,
+	BNXT_ULP_CLASS_HID_266a = 0x266a,
+	BNXT_ULP_CLASS_HID_15c6a = 0x15c6a,
+	BNXT_ULP_CLASS_HID_216a6 = 0x216a6,
+	BNXT_ULP_CLASS_HID_30ca6 = 0x30ca6,
+	BNXT_ULP_CLASS_HID_3ff2 = 0x3ff2,
+	BNXT_ULP_CLASS_HID_155f2 = 0x155f2,
+	BNXT_ULP_CLASS_HID_24bf2 = 0x24bf2,
+	BNXT_ULP_CLASS_HID_302ce = 0x302ce,
+	BNXT_ULP_CLASS_HID_4512 = 0x4512,
+	BNXT_ULP_CLASS_HID_11c6e = 0x11c6e,
+	BNXT_ULP_CLASS_HID_2326e = 0x2326e,
+	BNXT_ULP_CLASS_HID_3286e = 0x3286e,
+	BNXT_ULP_CLASS_HID_49b6 = 0x49b6,
+	BNXT_ULP_CLASS_HID_10082 = 0x10082,
+	BNXT_ULP_CLASS_HID_23682 = 0x23682,
+	BNXT_ULP_CLASS_HID_32c82 = 0x32c82,
+	BNXT_ULP_CLASS_HID_2016 = 0x2016,
+	BNXT_ULP_CLASS_HID_15616 = 0x15616,
+	BNXT_ULP_CLASS_HID_21162 = 0x21162,
+	BNXT_ULP_CLASS_HID_30762 = 0x30762,
+	BNXT_ULP_CLASS_HID_39be = 0x39be,
+	BNXT_ULP_CLASS_HID_12fbe = 0x12fbe,
+	BNXT_ULP_CLASS_HID_245be = 0x245be,
+	BNXT_ULP_CLASS_HID_31c8a = 0x31c8a,
+	BNXT_ULP_CLASS_HID_5fde = 0x5fde,
+	BNXT_ULP_CLASS_HID_1162a = 0x1162a,
+	BNXT_ULP_CLASS_HID_20c2a = 0x20c2a,
+	BNXT_ULP_CLASS_HID_3222a = 0x3222a,
+	BNXT_ULP_CLASS_HID_34de = 0x34de,
+	BNXT_ULP_CLASS_HID_3a12 = 0x3a12,
+	BNXT_ULP_CLASS_HID_370e = 0x370e,
+	BNXT_ULP_CLASS_HID_12d0e = 0x12d0e,
+	BNXT_ULP_CLASS_HID_2430e = 0x2430e,
+	BNXT_ULP_CLASS_HID_31dda = 0x31dda,
+	BNXT_ULP_CLASS_HID_11ae = 0x11ae,
+	BNXT_ULP_CLASS_HID_107ae = 0x107ae,
+	BNXT_ULP_CLASS_HID_23dae = 0x23dae,
+	BNXT_ULP_CLASS_HID_353ae = 0x353ae,
+	BNXT_ULP_CLASS_HID_427a = 0x427a,
+	BNXT_ULP_CLASS_HID_11d36 = 0x11d36,
+	BNXT_ULP_CLASS_HID_23336 = 0x23336,
+	BNXT_ULP_CLASS_HID_32936 = 0x32936,
+	BNXT_ULP_CLASS_HID_0c96 = 0x0c96,
+	BNXT_ULP_CLASS_HID_12296 = 0x12296,
+	BNXT_ULP_CLASS_HID_25896 = 0x25896,
+	BNXT_ULP_CLASS_HID_313a2 = 0x313a2,
+	BNXT_ULP_CLASS_HID_314a = 0x314a,
+	BNXT_ULP_CLASS_HID_1274a = 0x1274a,
+	BNXT_ULP_CLASS_HID_25d4a = 0x25d4a,
+	BNXT_ULP_CLASS_HID_31406 = 0x31406,
+	BNXT_ULP_CLASS_HID_46de = 0x46de,
+	BNXT_ULP_CLASS_HID_101ea = 0x101ea,
+	BNXT_ULP_CLASS_HID_237ea = 0x237ea,
+	BNXT_ULP_CLASS_HID_32dea = 0x32dea,
+	BNXT_ULP_CLASS_HID_5ca6 = 0x5ca6,
+	BNXT_ULP_CLASS_HID_11772 = 0x11772,
+	BNXT_ULP_CLASS_HID_20d72 = 0x20d72,
+	BNXT_ULP_CLASS_HID_32372 = 0x32372,
+	BNXT_ULP_CLASS_HID_06d2 = 0x06d2,
+	BNXT_ULP_CLASS_HID_13cd2 = 0x13cd2,
+	BNXT_ULP_CLASS_HID_252d2 = 0x252d2,
+	BNXT_ULP_CLASS_HID_348d2 = 0x348d2,
+	BNXT_ULP_CLASS_HID_1c3e = 0x1c3e,
+	BNXT_ULP_CLASS_HID_1323e = 0x1323e,
+	BNXT_ULP_CLASS_HID_2283e = 0x2283e,
+	BNXT_ULP_CLASS_HID_35e3e = 0x35e3e,
+	BNXT_ULP_CLASS_HID_5582 = 0x5582,
+	BNXT_ULP_CLASS_HID_14b82 = 0x14b82,
+	BNXT_ULP_CLASS_HID_2025e = 0x2025e,
+	BNXT_ULP_CLASS_HID_3385e = 0x3385e,
+	BNXT_ULP_CLASS_HID_2b6a = 0x2b6a,
+	BNXT_ULP_CLASS_HID_1416a = 0x1416a,
+	BNXT_ULP_CLASS_HID_21826 = 0x21826,
+	BNXT_ULP_CLASS_HID_30e26 = 0x30e26,
+	BNXT_ULP_CLASS_HID_1586 = 0x1586,
+	BNXT_ULP_CLASS_HID_10b86 = 0x10b86,
+	BNXT_ULP_CLASS_HID_22186 = 0x22186,
+	BNXT_ULP_CLASS_HID_35786 = 0x35786,
+	BNXT_ULP_CLASS_HID_167a = 0x167a,
+	BNXT_ULP_CLASS_HID_10c7a = 0x10c7a,
+	BNXT_ULP_CLASS_HID_2227a = 0x2227a,
+	BNXT_ULP_CLASS_HID_3587a = 0x3587a,
+	BNXT_ULP_CLASS_HID_2fce = 0x2fce,
+	BNXT_ULP_CLASS_HID_145ce = 0x145ce,
+	BNXT_ULP_CLASS_HID_21c9a = 0x21c9a,
+	BNXT_ULP_CLASS_HID_3329a = 0x3329a,
+	BNXT_ULP_CLASS_HID_2556 = 0x2556,
+	BNXT_ULP_CLASS_HID_15b56 = 0x15b56,
+	BNXT_ULP_CLASS_HID_21262 = 0x21262,
+	BNXT_ULP_CLASS_HID_30862 = 0x30862,
+	BNXT_ULP_CLASS_HID_4b36 = 0x4b36,
+	BNXT_ULP_CLASS_HID_105c2 = 0x105c2,
+	BNXT_ULP_CLASS_HID_23bc2 = 0x23bc2,
+	BNXT_ULP_CLASS_HID_351c2 = 0x351c2,
+	BNXT_ULP_CLASS_HID_10a6 = 0x10a6,
+	BNXT_ULP_CLASS_HID_106a6 = 0x106a6,
+	BNXT_ULP_CLASS_HID_23ca6 = 0x23ca6,
+	BNXT_ULP_CLASS_HID_352a6 = 0x352a6,
+	BNXT_ULP_CLASS_HID_260a = 0x260a,
+	BNXT_ULP_CLASS_HID_15c0a = 0x15c0a,
+	BNXT_ULP_CLASS_HID_216c6 = 0x216c6,
+	BNXT_ULP_CLASS_HID_30cc6 = 0x30cc6,
+	BNXT_ULP_CLASS_HID_3f92 = 0x3f92,
+	BNXT_ULP_CLASS_HID_15592 = 0x15592,
+	BNXT_ULP_CLASS_HID_24b92 = 0x24b92,
+	BNXT_ULP_CLASS_HID_302ae = 0x302ae,
+	BNXT_ULP_CLASS_HID_4572 = 0x4572,
+	BNXT_ULP_CLASS_HID_11c0e = 0x11c0e,
+	BNXT_ULP_CLASS_HID_2320e = 0x2320e,
+	BNXT_ULP_CLASS_HID_3280e = 0x3280e,
+	BNXT_ULP_CLASS_HID_49d6 = 0x49d6,
+	BNXT_ULP_CLASS_HID_100e2 = 0x100e2,
+	BNXT_ULP_CLASS_HID_236e2 = 0x236e2,
+	BNXT_ULP_CLASS_HID_32ce2 = 0x32ce2,
+	BNXT_ULP_CLASS_HID_2076 = 0x2076,
+	BNXT_ULP_CLASS_HID_15676 = 0x15676,
+	BNXT_ULP_CLASS_HID_21102 = 0x21102,
+	BNXT_ULP_CLASS_HID_30702 = 0x30702,
+	BNXT_ULP_CLASS_HID_39de = 0x39de,
+	BNXT_ULP_CLASS_HID_12fde = 0x12fde,
+	BNXT_ULP_CLASS_HID_245de = 0x245de,
+	BNXT_ULP_CLASS_HID_31cea = 0x31cea,
+	BNXT_ULP_CLASS_HID_5fbe = 0x5fbe,
+	BNXT_ULP_CLASS_HID_1164a = 0x1164a,
+	BNXT_ULP_CLASS_HID_20c4a = 0x20c4a,
+	BNXT_ULP_CLASS_HID_3224a = 0x3224a,
+	BNXT_ULP_CLASS_HID_34be = 0x34be,
+	BNXT_ULP_CLASS_HID_3a72 = 0x3a72,
+	BNXT_ULP_CLASS_HID_09ea = 0x09ea,
+	BNXT_ULP_CLASS_HID_2912 = 0x2912,
+	BNXT_ULP_CLASS_HID_03b2 = 0x03b2,
+	BNXT_ULP_CLASS_HID_5f7e = 0x5f7e,
+	BNXT_ULP_CLASS_HID_03a6 = 0x03a6,
+	BNXT_ULP_CLASS_HID_23ce = 0x23ce,
+	BNXT_ULP_CLASS_HID_1a6e = 0x1a6e,
+	BNXT_ULP_CLASS_HID_593a = 0x593a,
+	BNXT_ULP_CLASS_HID_4dce = 0x4dce,
+	BNXT_ULP_CLASS_HID_0e02 = 0x0e02,
+	BNXT_ULP_CLASS_HID_4796 = 0x4796,
+	BNXT_ULP_CLASS_HID_246e = 0x246e,
+	BNXT_ULP_CLASS_HID_478a = 0x478a,
+	BNXT_ULP_CLASS_HID_08fe = 0x08fe,
+	BNXT_ULP_CLASS_HID_5e52 = 0x5e52,
+	BNXT_ULP_CLASS_HID_3e2a = 0x3e2a,
+	BNXT_ULP_CLASS_HID_5e46 = 0x5e46,
+	BNXT_ULP_CLASS_HID_02ba = 0x02ba,
+	BNXT_ULP_CLASS_HID_580e = 0x580e,
+	BNXT_ULP_CLASS_HID_38e6 = 0x38e6,
+	BNXT_ULP_CLASS_HID_5802 = 0x5802,
+	BNXT_ULP_CLASS_HID_1d76 = 0x1d76,
+	BNXT_ULP_CLASS_HID_52ca = 0x52ca,
+	BNXT_ULP_CLASS_HID_32a2 = 0x32a2,
+	BNXT_ULP_CLASS_HID_34f6 = 0x34f6,
+	BNXT_ULP_CLASS_HID_3a3a = 0x3a3a,
+	BNXT_ULP_CLASS_HID_09ca = 0x09ca,
+	BNXT_ULP_CLASS_HID_0216 = 0x0216,
+	BNXT_ULP_CLASS_HID_1f62 = 0x1f62,
+	BNXT_ULP_CLASS_HID_1bae = 0x1bae,
+	BNXT_ULP_CLASS_HID_2932 = 0x2932,
+	BNXT_ULP_CLASS_HID_227e = 0x227e,
+	BNXT_ULP_CLASS_HID_3f4a = 0x3f4a,
+	BNXT_ULP_CLASS_HID_3b96 = 0x3b96,
+	BNXT_ULP_CLASS_HID_0392 = 0x0392,
+	BNXT_ULP_CLASS_HID_1cde = 0x1cde,
+	BNXT_ULP_CLASS_HID_192a = 0x192a,
+	BNXT_ULP_CLASS_HID_1276 = 0x1276,
+	BNXT_ULP_CLASS_HID_5f5e = 0x5f5e,
+	BNXT_ULP_CLASS_HID_5baa = 0x5baa,
+	BNXT_ULP_CLASS_HID_54f6 = 0x54f6,
+	BNXT_ULP_CLASS_HID_51c2 = 0x51c2,
+	BNXT_ULP_CLASS_HID_0386 = 0x0386,
+	BNXT_ULP_CLASS_HID_1cd2 = 0x1cd2,
+	BNXT_ULP_CLASS_HID_191e = 0x191e,
+	BNXT_ULP_CLASS_HID_126a = 0x126a,
+	BNXT_ULP_CLASS_HID_23ee = 0x23ee,
+	BNXT_ULP_CLASS_HID_3c3a = 0x3c3a,
+	BNXT_ULP_CLASS_HID_3906 = 0x3906,
+	BNXT_ULP_CLASS_HID_3252 = 0x3252,
+	BNXT_ULP_CLASS_HID_1a4e = 0x1a4e,
+	BNXT_ULP_CLASS_HID_169a = 0x169a,
+	BNXT_ULP_CLASS_HID_13e6 = 0x13e6,
+	BNXT_ULP_CLASS_HID_4be6 = 0x4be6,
+	BNXT_ULP_CLASS_HID_591a = 0x591a,
+	BNXT_ULP_CLASS_HID_5266 = 0x5266,
+	BNXT_ULP_CLASS_HID_2eb2 = 0x2eb2,
+	BNXT_ULP_CLASS_HID_2bfe = 0x2bfe,
+	BNXT_ULP_CLASS_HID_4dee = 0x4dee,
+	BNXT_ULP_CLASS_HID_463a = 0x463a,
+	BNXT_ULP_CLASS_HID_4306 = 0x4306,
+	BNXT_ULP_CLASS_HID_5c52 = 0x5c52,
+	BNXT_ULP_CLASS_HID_0e22 = 0x0e22,
+	BNXT_ULP_CLASS_HID_0b6e = 0x0b6e,
+	BNXT_ULP_CLASS_HID_07ba = 0x07ba,
+	BNXT_ULP_CLASS_HID_0086 = 0x0086,
+	BNXT_ULP_CLASS_HID_47b6 = 0x47b6,
+	BNXT_ULP_CLASS_HID_4082 = 0x4082,
+	BNXT_ULP_CLASS_HID_5dce = 0x5dce,
+	BNXT_ULP_CLASS_HID_561a = 0x561a,
+	BNXT_ULP_CLASS_HID_244e = 0x244e,
+	BNXT_ULP_CLASS_HID_209a = 0x209a,
+	BNXT_ULP_CLASS_HID_3de6 = 0x3de6,
+	BNXT_ULP_CLASS_HID_3632 = 0x3632,
+	BNXT_ULP_CLASS_HID_47aa = 0x47aa,
+	BNXT_ULP_CLASS_HID_40f6 = 0x40f6,
+	BNXT_ULP_CLASS_HID_5dc2 = 0x5dc2,
+	BNXT_ULP_CLASS_HID_560e = 0x560e,
+	BNXT_ULP_CLASS_HID_08de = 0x08de,
+	BNXT_ULP_CLASS_HID_052a = 0x052a,
+	BNXT_ULP_CLASS_HID_1e76 = 0x1e76,
+	BNXT_ULP_CLASS_HID_1b42 = 0x1b42,
+	BNXT_ULP_CLASS_HID_5e72 = 0x5e72,
+	BNXT_ULP_CLASS_HID_5abe = 0x5abe,
+	BNXT_ULP_CLASS_HID_578a = 0x578a,
+	BNXT_ULP_CLASS_HID_50d6 = 0x50d6,
+	BNXT_ULP_CLASS_HID_3e0a = 0x3e0a,
+	BNXT_ULP_CLASS_HID_3b56 = 0x3b56,
+	BNXT_ULP_CLASS_HID_37a2 = 0x37a2,
+	BNXT_ULP_CLASS_HID_30ee = 0x30ee,
+	BNXT_ULP_CLASS_HID_5e66 = 0x5e66,
+	BNXT_ULP_CLASS_HID_5ab2 = 0x5ab2,
+	BNXT_ULP_CLASS_HID_57fe = 0x57fe,
+	BNXT_ULP_CLASS_HID_50ca = 0x50ca,
+	BNXT_ULP_CLASS_HID_029a = 0x029a,
+	BNXT_ULP_CLASS_HID_1fe6 = 0x1fe6,
+	BNXT_ULP_CLASS_HID_1832 = 0x1832,
+	BNXT_ULP_CLASS_HID_157e = 0x157e,
+	BNXT_ULP_CLASS_HID_582e = 0x582e,
+	BNXT_ULP_CLASS_HID_557a = 0x557a,
+	BNXT_ULP_CLASS_HID_2e46 = 0x2e46,
+	BNXT_ULP_CLASS_HID_2a92 = 0x2a92,
+	BNXT_ULP_CLASS_HID_38c6 = 0x38c6,
+	BNXT_ULP_CLASS_HID_3512 = 0x3512,
+	BNXT_ULP_CLASS_HID_0e5e = 0x0e5e,
+	BNXT_ULP_CLASS_HID_0aaa = 0x0aaa,
+	BNXT_ULP_CLASS_HID_5822 = 0x5822,
+	BNXT_ULP_CLASS_HID_556e = 0x556e,
+	BNXT_ULP_CLASS_HID_51ba = 0x51ba,
+	BNXT_ULP_CLASS_HID_2a86 = 0x2a86,
+	BNXT_ULP_CLASS_HID_1d56 = 0x1d56,
+	BNXT_ULP_CLASS_HID_19a2 = 0x19a2,
+	BNXT_ULP_CLASS_HID_12ee = 0x12ee,
+	BNXT_ULP_CLASS_HID_4aee = 0x4aee,
+	BNXT_ULP_CLASS_HID_52ea = 0x52ea,
+	BNXT_ULP_CLASS_HID_2f36 = 0x2f36,
+	BNXT_ULP_CLASS_HID_2802 = 0x2802,
+	BNXT_ULP_CLASS_HID_254e = 0x254e,
+	BNXT_ULP_CLASS_HID_3282 = 0x3282,
+	BNXT_ULP_CLASS_HID_0fce = 0x0fce,
+	BNXT_ULP_CLASS_HID_081a = 0x081a,
+	BNXT_ULP_CLASS_HID_0566 = 0x0566,
+	BNXT_ULP_CLASS_HID_34d6 = 0x34d6,
+	BNXT_ULP_CLASS_HID_3a1a = 0x3a1a,
+	BNXT_ULP_CLASS_HID_09aa = 0x09aa,
+	BNXT_ULP_CLASS_HID_0276 = 0x0276,
+	BNXT_ULP_CLASS_HID_1f02 = 0x1f02,
+	BNXT_ULP_CLASS_HID_1bce = 0x1bce,
+	BNXT_ULP_CLASS_HID_2952 = 0x2952,
+	BNXT_ULP_CLASS_HID_221e = 0x221e,
+	BNXT_ULP_CLASS_HID_3f2a = 0x3f2a,
+	BNXT_ULP_CLASS_HID_3bf6 = 0x3bf6,
+	BNXT_ULP_CLASS_HID_03f2 = 0x03f2,
+	BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
+	BNXT_ULP_CLASS_HID_194a = 0x194a,
+	BNXT_ULP_CLASS_HID_1216 = 0x1216,
+	BNXT_ULP_CLASS_HID_5f3e = 0x5f3e,
+	BNXT_ULP_CLASS_HID_5bca = 0x5bca,
+	BNXT_ULP_CLASS_HID_5496 = 0x5496,
+	BNXT_ULP_CLASS_HID_51a2 = 0x51a2,
+	BNXT_ULP_CLASS_HID_03e6 = 0x03e6,
+	BNXT_ULP_CLASS_HID_1cb2 = 0x1cb2,
+	BNXT_ULP_CLASS_HID_197e = 0x197e,
+	BNXT_ULP_CLASS_HID_120a = 0x120a,
+	BNXT_ULP_CLASS_HID_238e = 0x238e,
+	BNXT_ULP_CLASS_HID_3c5a = 0x3c5a,
+	BNXT_ULP_CLASS_HID_3966 = 0x3966,
+	BNXT_ULP_CLASS_HID_3232 = 0x3232,
+	BNXT_ULP_CLASS_HID_1a2e = 0x1a2e,
+	BNXT_ULP_CLASS_HID_16fa = 0x16fa,
+	BNXT_ULP_CLASS_HID_1386 = 0x1386,
+	BNXT_ULP_CLASS_HID_4b86 = 0x4b86,
+	BNXT_ULP_CLASS_HID_597a = 0x597a,
+	BNXT_ULP_CLASS_HID_5206 = 0x5206,
+	BNXT_ULP_CLASS_HID_2ed2 = 0x2ed2,
+	BNXT_ULP_CLASS_HID_2b9e = 0x2b9e,
+	BNXT_ULP_CLASS_HID_4d8e = 0x4d8e,
+	BNXT_ULP_CLASS_HID_465a = 0x465a,
+	BNXT_ULP_CLASS_HID_4366 = 0x4366,
+	BNXT_ULP_CLASS_HID_5c32 = 0x5c32,
+	BNXT_ULP_CLASS_HID_0e42 = 0x0e42,
+	BNXT_ULP_CLASS_HID_0b0e = 0x0b0e,
+	BNXT_ULP_CLASS_HID_07da = 0x07da,
 	BNXT_ULP_CLASS_HID_00e6 = 0x00e6,
-	BNXT_ULP_CLASS_HID_009c = 0x009c,
-	BNXT_ULP_CLASS_HID_005e = 0x005e,
-	BNXT_ULP_CLASS_HID_01f4 = 0x01f4,
-	BNXT_ULP_CLASS_HID_01b6 = 0x01b6
+	BNXT_ULP_CLASS_HID_47d6 = 0x47d6,
+	BNXT_ULP_CLASS_HID_40e2 = 0x40e2,
+	BNXT_ULP_CLASS_HID_5dae = 0x5dae,
+	BNXT_ULP_CLASS_HID_567a = 0x567a,
+	BNXT_ULP_CLASS_HID_242e = 0x242e,
+	BNXT_ULP_CLASS_HID_20fa = 0x20fa,
+	BNXT_ULP_CLASS_HID_3d86 = 0x3d86,
+	BNXT_ULP_CLASS_HID_3652 = 0x3652,
+	BNXT_ULP_CLASS_HID_47ca = 0x47ca,
+	BNXT_ULP_CLASS_HID_4096 = 0x4096,
+	BNXT_ULP_CLASS_HID_5da2 = 0x5da2,
+	BNXT_ULP_CLASS_HID_566e = 0x566e,
+	BNXT_ULP_CLASS_HID_08be = 0x08be,
+	BNXT_ULP_CLASS_HID_054a = 0x054a,
+	BNXT_ULP_CLASS_HID_1e16 = 0x1e16,
+	BNXT_ULP_CLASS_HID_1b22 = 0x1b22,
+	BNXT_ULP_CLASS_HID_5e12 = 0x5e12,
+	BNXT_ULP_CLASS_HID_5ade = 0x5ade,
+	BNXT_ULP_CLASS_HID_57ea = 0x57ea,
+	BNXT_ULP_CLASS_HID_50b6 = 0x50b6,
+	BNXT_ULP_CLASS_HID_3e6a = 0x3e6a,
+	BNXT_ULP_CLASS_HID_3b36 = 0x3b36,
+	BNXT_ULP_CLASS_HID_37c2 = 0x37c2,
+	BNXT_ULP_CLASS_HID_308e = 0x308e,
+	BNXT_ULP_CLASS_HID_5e06 = 0x5e06,
+	BNXT_ULP_CLASS_HID_5ad2 = 0x5ad2,
+	BNXT_ULP_CLASS_HID_579e = 0x579e,
+	BNXT_ULP_CLASS_HID_50aa = 0x50aa,
+	BNXT_ULP_CLASS_HID_02fa = 0x02fa,
+	BNXT_ULP_CLASS_HID_1f86 = 0x1f86,
+	BNXT_ULP_CLASS_HID_1852 = 0x1852,
+	BNXT_ULP_CLASS_HID_151e = 0x151e,
+	BNXT_ULP_CLASS_HID_584e = 0x584e,
+	BNXT_ULP_CLASS_HID_551a = 0x551a,
+	BNXT_ULP_CLASS_HID_2e26 = 0x2e26,
+	BNXT_ULP_CLASS_HID_2af2 = 0x2af2,
+	BNXT_ULP_CLASS_HID_38a6 = 0x38a6,
+	BNXT_ULP_CLASS_HID_3572 = 0x3572,
+	BNXT_ULP_CLASS_HID_0e3e = 0x0e3e,
+	BNXT_ULP_CLASS_HID_0aca = 0x0aca,
+	BNXT_ULP_CLASS_HID_5842 = 0x5842,
+	BNXT_ULP_CLASS_HID_550e = 0x550e,
+	BNXT_ULP_CLASS_HID_51da = 0x51da,
+	BNXT_ULP_CLASS_HID_2ae6 = 0x2ae6,
+	BNXT_ULP_CLASS_HID_1d36 = 0x1d36,
+	BNXT_ULP_CLASS_HID_19c2 = 0x19c2,
+	BNXT_ULP_CLASS_HID_128e = 0x128e,
+	BNXT_ULP_CLASS_HID_4a8e = 0x4a8e,
+	BNXT_ULP_CLASS_HID_528a = 0x528a,
+	BNXT_ULP_CLASS_HID_2f56 = 0x2f56,
+	BNXT_ULP_CLASS_HID_2862 = 0x2862,
+	BNXT_ULP_CLASS_HID_252e = 0x252e,
+	BNXT_ULP_CLASS_HID_32e2 = 0x32e2,
+	BNXT_ULP_CLASS_HID_0fae = 0x0fae,
+	BNXT_ULP_CLASS_HID_087a = 0x087a,
+	BNXT_ULP_CLASS_HID_0506 = 0x0506,
+	BNXT_ULP_CLASS_HID_34b6 = 0x34b6,
+	BNXT_ULP_CLASS_HID_3a7a = 0x3a7a,
+	BNXT_ULP_CLASS_HID_a73c = 0xa73c,
+	BNXT_ULP_CLASS_HID_a040 = 0xa040,
+	BNXT_ULP_CLASS_HID_1d640 = 0x1d640,
+	BNXT_ULP_CLASS_HID_1dd3c = 0x1dd3c,
+	BNXT_ULP_CLASS_HID_cba0 = 0xcba0,
+	BNXT_ULP_CLASS_HID_c4f4 = 0xc4f4,
+	BNXT_ULP_CLASS_HID_19f38 = 0x19f38,
+	BNXT_ULP_CLASS_HID_182f4 = 0x182f4,
+	BNXT_ULP_CLASS_HID_b098 = 0xb098,
+	BNXT_ULP_CLASS_HID_8dac = 0x8dac,
+	BNXT_ULP_CLASS_HID_1a3ac = 0x1a3ac,
+	BNXT_ULP_CLASS_HID_1a698 = 0x1a698,
+	BNXT_ULP_CLASS_HID_d50c = 0xd50c,
+	BNXT_ULP_CLASS_HID_ae50 = 0xae50,
+	BNXT_ULP_CLASS_HID_1c450 = 0x1c450,
+	BNXT_ULP_CLASS_HID_1cb0c = 0x1cb0c,
+	BNXT_ULP_CLASS_HID_a1f0 = 0xa1f0,
+	BNXT_ULP_CLASS_HID_ba04 = 0xba04,
+	BNXT_ULP_CLASS_HID_1d004 = 0x1d004,
+	BNXT_ULP_CLASS_HID_1d7f0 = 0x1d7f0,
+	BNXT_ULP_CLASS_HID_c264 = 0xc264,
+	BNXT_ULP_CLASS_HID_dea8 = 0xdea8,
+	BNXT_ULP_CLASS_HID_199fc = 0x199fc,
+	BNXT_ULP_CLASS_HID_19ca8 = 0x19ca8,
+	BNXT_ULP_CLASS_HID_8b5c = 0x8b5c,
+	BNXT_ULP_CLASS_HID_8460 = 0x8460,
+	BNXT_ULP_CLASS_HID_1ba60 = 0x1ba60,
+	BNXT_ULP_CLASS_HID_1a15c = 0x1a15c,
+	BNXT_ULP_CLASS_HID_afc0 = 0xafc0,
+	BNXT_ULP_CLASS_HID_a814 = 0xa814,
+	BNXT_ULP_CLASS_HID_1de14 = 0x1de14,
+	BNXT_ULP_CLASS_HID_1c5c0 = 0x1c5c0,
+	BNXT_ULP_CLASS_HID_8c2c = 0x8c2c,
+	BNXT_ULP_CLASS_HID_8970 = 0x8970,
+	BNXT_ULP_CLASS_HID_1bf70 = 0x1bf70,
+	BNXT_ULP_CLASS_HID_1a22c = 0x1a22c,
+	BNXT_ULP_CLASS_HID_d0d0 = 0xd0d0,
+	BNXT_ULP_CLASS_HID_ade4 = 0xade4,
+	BNXT_ULP_CLASS_HID_1c3e4 = 0x1c3e4,
+	BNXT_ULP_CLASS_HID_1c6d0 = 0x1c6d0,
+	BNXT_ULP_CLASS_HID_9988 = 0x9988,
+	BNXT_ULP_CLASS_HID_92dc = 0x92dc,
+	BNXT_ULP_CLASS_HID_188dc = 0x188dc,
+	BNXT_ULP_CLASS_HID_18f88 = 0x18f88,
+	BNXT_ULP_CLASS_HID_ba3c = 0xba3c,
+	BNXT_ULP_CLASS_HID_b740 = 0xb740,
+	BNXT_ULP_CLASS_HID_1ad40 = 0x1ad40,
+	BNXT_ULP_CLASS_HID_1d03c = 0x1d03c,
+	BNXT_ULP_CLASS_HID_86e0 = 0x86e0,
+	BNXT_ULP_CLASS_HID_8334 = 0x8334,
+	BNXT_ULP_CLASS_HID_1b934 = 0x1b934,
+	BNXT_ULP_CLASS_HID_1bce0 = 0x1bce0,
+	BNXT_ULP_CLASS_HID_aa94 = 0xaa94,
+	BNXT_ULP_CLASS_HID_a7d8 = 0xa7d8,
+	BNXT_ULP_CLASS_HID_1ddd8 = 0x1ddd8,
+	BNXT_ULP_CLASS_HID_1c094 = 0x1c094,
+	BNXT_ULP_CLASS_HID_904c = 0x904c,
+	BNXT_ULP_CLASS_HID_c84c = 0xc84c,
+	BNXT_ULP_CLASS_HID_18290 = 0x18290,
+	BNXT_ULP_CLASS_HID_1864c = 0x1864c,
+	BNXT_ULP_CLASS_HID_b4f0 = 0xb4f0,
+	BNXT_ULP_CLASS_HID_b104 = 0xb104,
+	BNXT_ULP_CLASS_HID_1a704 = 0x1a704,
+	BNXT_ULP_CLASS_HID_1aaf0 = 0x1aaf0,
+	BNXT_ULP_CLASS_HID_80a4 = 0x80a4,
+	BNXT_ULP_CLASS_HID_9de8 = 0x9de8,
+	BNXT_ULP_CLASS_HID_1b3e8 = 0x1b3e8,
+	BNXT_ULP_CLASS_HID_1b6a4 = 0x1b6a4,
+	BNXT_ULP_CLASS_HID_a548 = 0xa548,
+	BNXT_ULP_CLASS_HID_a19c = 0xa19c,
+	BNXT_ULP_CLASS_HID_1d79c = 0x1d79c,
+	BNXT_ULP_CLASS_HID_1db48 = 0x1db48,
+	BNXT_ULP_CLASS_HID_9a98 = 0x9a98,
+	BNXT_ULP_CLASS_HID_97ac = 0x97ac,
+	BNXT_ULP_CLASS_HID_18dac = 0x18dac,
+	BNXT_ULP_CLASS_HID_1b098 = 0x1b098,
+	BNXT_ULP_CLASS_HID_bf0c = 0xbf0c,
+	BNXT_ULP_CLASS_HID_b850 = 0xb850,
+	BNXT_ULP_CLASS_HID_1ae50 = 0x1ae50,
+	BNXT_ULP_CLASS_HID_1d50c = 0x1d50c,
+	BNXT_ULP_CLASS_HID_34f0 = 0x34f0,
+	BNXT_ULP_CLASS_HID_3a3c = 0x3a3c,
+	BNXT_ULP_CLASS_HID_5ea0 = 0x5ea0,
+	BNXT_ULP_CLASS_HID_0798 = 0x0798,
+	BNXT_ULP_CLASS_HID_280c = 0x280c,
+	BNXT_ULP_CLASS_HID_5964 = 0x5964,
+	BNXT_ULP_CLASS_HID_1e5c = 0x1e5c,
+	BNXT_ULP_CLASS_HID_22c0 = 0x22c0,
+	BNXT_ULP_CLASS_HID_a71c = 0xa71c,
+	BNXT_ULP_CLASS_HID_a8dc = 0xa8dc,
+	BNXT_ULP_CLASS_HID_ed9c = 0xed9c,
+	BNXT_ULP_CLASS_HID_ef5c = 0xef5c,
+	BNXT_ULP_CLASS_HID_a060 = 0xa060,
+	BNXT_ULP_CLASS_HID_a520 = 0xa520,
+	BNXT_ULP_CLASS_HID_e6e0 = 0xe6e0,
+	BNXT_ULP_CLASS_HID_eba0 = 0xeba0,
+	BNXT_ULP_CLASS_HID_1d660 = 0x1d660,
+	BNXT_ULP_CLASS_HID_1fb20 = 0x1fb20,
+	BNXT_ULP_CLASS_HID_1dce0 = 0x1dce0,
+	BNXT_ULP_CLASS_HID_1e1a0 = 0x1e1a0,
+	BNXT_ULP_CLASS_HID_1dd1c = 0x1dd1c,
+	BNXT_ULP_CLASS_HID_1fedc = 0x1fedc,
+	BNXT_ULP_CLASS_HID_1c39c = 0x1c39c,
+	BNXT_ULP_CLASS_HID_1e55c = 0x1e55c,
+	BNXT_ULP_CLASS_HID_cb80 = 0xcb80,
+	BNXT_ULP_CLASS_HID_b194 = 0xb194,
+	BNXT_ULP_CLASS_HID_d354 = 0xd354,
+	BNXT_ULP_CLASS_HID_f414 = 0xf414,
+	BNXT_ULP_CLASS_HID_c4d4 = 0xc4d4,
+	BNXT_ULP_CLASS_HID_e994 = 0xe994,
+	BNXT_ULP_CLASS_HID_cb54 = 0xcb54,
+	BNXT_ULP_CLASS_HID_f158 = 0xf158,
+	BNXT_ULP_CLASS_HID_19f18 = 0x19f18,
+	BNXT_ULP_CLASS_HID_1a0d8 = 0x1a0d8,
+	BNXT_ULP_CLASS_HID_1c598 = 0x1c598,
+	BNXT_ULP_CLASS_HID_1e758 = 0x1e758,
+	BNXT_ULP_CLASS_HID_182d4 = 0x182d4,
+	BNXT_ULP_CLASS_HID_1a794 = 0x1a794,
+	BNXT_ULP_CLASS_HID_1c954 = 0x1c954,
+	BNXT_ULP_CLASS_HID_1ea14 = 0x1ea14,
+	BNXT_ULP_CLASS_HID_b0b8 = 0xb0b8,
+	BNXT_ULP_CLASS_HID_b278 = 0xb278,
+	BNXT_ULP_CLASS_HID_f738 = 0xf738,
+	BNXT_ULP_CLASS_HID_f8f8 = 0xf8f8,
+	BNXT_ULP_CLASS_HID_8d8c = 0x8d8c,
+	BNXT_ULP_CLASS_HID_af4c = 0xaf4c,
+	BNXT_ULP_CLASS_HID_f00c = 0xf00c,
+	BNXT_ULP_CLASS_HID_f5cc = 0xf5cc,
+	BNXT_ULP_CLASS_HID_1a38c = 0x1a38c,
+	BNXT_ULP_CLASS_HID_1a54c = 0x1a54c,
+	BNXT_ULP_CLASS_HID_1e60c = 0x1e60c,
+	BNXT_ULP_CLASS_HID_1ebcc = 0x1ebcc,
+	BNXT_ULP_CLASS_HID_1a6b8 = 0x1a6b8,
+	BNXT_ULP_CLASS_HID_1a878 = 0x1a878,
+	BNXT_ULP_CLASS_HID_1ed38 = 0x1ed38,
+	BNXT_ULP_CLASS_HID_1eef8 = 0x1eef8,
+	BNXT_ULP_CLASS_HID_d52c = 0xd52c,
+	BNXT_ULP_CLASS_HID_f6ec = 0xf6ec,
+	BNXT_ULP_CLASS_HID_dbac = 0xdbac,
+	BNXT_ULP_CLASS_HID_fd6c = 0xfd6c,
+	BNXT_ULP_CLASS_HID_ae70 = 0xae70,
+	BNXT_ULP_CLASS_HID_f330 = 0xf330,
+	BNXT_ULP_CLASS_HID_d4f0 = 0xd4f0,
+	BNXT_ULP_CLASS_HID_f9b0 = 0xf9b0,
+	BNXT_ULP_CLASS_HID_1c470 = 0x1c470,
+	BNXT_ULP_CLASS_HID_1e930 = 0x1e930,
+	BNXT_ULP_CLASS_HID_1caf0 = 0x1caf0,
+	BNXT_ULP_CLASS_HID_1f084 = 0x1f084,
+	BNXT_ULP_CLASS_HID_1cb2c = 0x1cb2c,
+	BNXT_ULP_CLASS_HID_1b130 = 0x1b130,
+	BNXT_ULP_CLASS_HID_1d2f0 = 0x1d2f0,
+	BNXT_ULP_CLASS_HID_1f7b0 = 0x1f7b0,
+	BNXT_ULP_CLASS_HID_a1d0 = 0xa1d0,
+	BNXT_ULP_CLASS_HID_a290 = 0xa290,
+	BNXT_ULP_CLASS_HID_e450 = 0xe450,
+	BNXT_ULP_CLASS_HID_e910 = 0xe910,
+	BNXT_ULP_CLASS_HID_ba24 = 0xba24,
+	BNXT_ULP_CLASS_HID_bfe4 = 0xbfe4,
+	BNXT_ULP_CLASS_HID_e0a4 = 0xe0a4,
+	BNXT_ULP_CLASS_HID_e264 = 0xe264,
+	BNXT_ULP_CLASS_HID_1d024 = 0x1d024,
+	BNXT_ULP_CLASS_HID_1f5e4 = 0x1f5e4,
+	BNXT_ULP_CLASS_HID_1d6a4 = 0x1d6a4,
+	BNXT_ULP_CLASS_HID_1f864 = 0x1f864,
+	BNXT_ULP_CLASS_HID_1d7d0 = 0x1d7d0,
+	BNXT_ULP_CLASS_HID_1f890 = 0x1f890,
+	BNXT_ULP_CLASS_HID_1da50 = 0x1da50,
+	BNXT_ULP_CLASS_HID_1ff10 = 0x1ff10,
+	BNXT_ULP_CLASS_HID_c244 = 0xc244,
+	BNXT_ULP_CLASS_HID_e704 = 0xe704,
+	BNXT_ULP_CLASS_HID_c8c4 = 0xc8c4,
+	BNXT_ULP_CLASS_HID_ed84 = 0xed84,
+	BNXT_ULP_CLASS_HID_de88 = 0xde88,
+	BNXT_ULP_CLASS_HID_e048 = 0xe048,
+	BNXT_ULP_CLASS_HID_c508 = 0xc508,
+	BNXT_ULP_CLASS_HID_e6c8 = 0xe6c8,
+	BNXT_ULP_CLASS_HID_199dc = 0x199dc,
+	BNXT_ULP_CLASS_HID_1ba9c = 0x1ba9c,
+	BNXT_ULP_CLASS_HID_1dc5c = 0x1dc5c,
+	BNXT_ULP_CLASS_HID_1e11c = 0x1e11c,
+	BNXT_ULP_CLASS_HID_19c88 = 0x19c88,
+	BNXT_ULP_CLASS_HID_1be48 = 0x1be48,
+	BNXT_ULP_CLASS_HID_1c308 = 0x1c308,
+	BNXT_ULP_CLASS_HID_1e4c8 = 0x1e4c8,
+	BNXT_ULP_CLASS_HID_8b7c = 0x8b7c,
+	BNXT_ULP_CLASS_HID_ac3c = 0xac3c,
+	BNXT_ULP_CLASS_HID_f1fc = 0xf1fc,
+	BNXT_ULP_CLASS_HID_f2bc = 0xf2bc,
+	BNXT_ULP_CLASS_HID_8440 = 0x8440,
+	BNXT_ULP_CLASS_HID_a900 = 0xa900,
+	BNXT_ULP_CLASS_HID_cac0 = 0xcac0,
+	BNXT_ULP_CLASS_HID_ef80 = 0xef80,
+	BNXT_ULP_CLASS_HID_1ba40 = 0x1ba40,
+	BNXT_ULP_CLASS_HID_1bf00 = 0x1bf00,
+	BNXT_ULP_CLASS_HID_1e0c0 = 0x1e0c0,
+	BNXT_ULP_CLASS_HID_1e580 = 0x1e580,
+	BNXT_ULP_CLASS_HID_1a17c = 0x1a17c,
+	BNXT_ULP_CLASS_HID_1a23c = 0x1a23c,
+	BNXT_ULP_CLASS_HID_1e7fc = 0x1e7fc,
+	BNXT_ULP_CLASS_HID_1e8bc = 0x1e8bc,
+	BNXT_ULP_CLASS_HID_afe0 = 0xafe0,
+	BNXT_ULP_CLASS_HID_f0a0 = 0xf0a0,
+	BNXT_ULP_CLASS_HID_d260 = 0xd260,
+	BNXT_ULP_CLASS_HID_f720 = 0xf720,
+	BNXT_ULP_CLASS_HID_a834 = 0xa834,
+	BNXT_ULP_CLASS_HID_adf4 = 0xadf4,
+	BNXT_ULP_CLASS_HID_eeb4 = 0xeeb4,
+	BNXT_ULP_CLASS_HID_f074 = 0xf074,
+	BNXT_ULP_CLASS_HID_1de34 = 0x1de34,
+	BNXT_ULP_CLASS_HID_1e3f4 = 0x1e3f4,
+	BNXT_ULP_CLASS_HID_1c4b4 = 0x1c4b4,
+	BNXT_ULP_CLASS_HID_1e674 = 0x1e674,
+	BNXT_ULP_CLASS_HID_1c5e0 = 0x1c5e0,
+	BNXT_ULP_CLASS_HID_1e6a0 = 0x1e6a0,
+	BNXT_ULP_CLASS_HID_1c860 = 0x1c860,
+	BNXT_ULP_CLASS_HID_1ed20 = 0x1ed20,
+	BNXT_ULP_CLASS_HID_8c0c = 0x8c0c,
+	BNXT_ULP_CLASS_HID_b1cc = 0xb1cc,
+	BNXT_ULP_CLASS_HID_f28c = 0xf28c,
+	BNXT_ULP_CLASS_HID_f44c = 0xf44c,
+	BNXT_ULP_CLASS_HID_8950 = 0x8950,
+	BNXT_ULP_CLASS_HID_aa10 = 0xaa10,
+	BNXT_ULP_CLASS_HID_cfd0 = 0xcfd0,
+	BNXT_ULP_CLASS_HID_f090 = 0xf090,
+	BNXT_ULP_CLASS_HID_1bf50 = 0x1bf50,
+	BNXT_ULP_CLASS_HID_1a010 = 0x1a010,
+	BNXT_ULP_CLASS_HID_1e5d0 = 0x1e5d0,
+	BNXT_ULP_CLASS_HID_1e690 = 0x1e690,
+	BNXT_ULP_CLASS_HID_1a20c = 0x1a20c,
+	BNXT_ULP_CLASS_HID_1a7cc = 0x1a7cc,
+	BNXT_ULP_CLASS_HID_1e88c = 0x1e88c,
+	BNXT_ULP_CLASS_HID_1ea4c = 0x1ea4c,
+	BNXT_ULP_CLASS_HID_d0f0 = 0xd0f0,
+	BNXT_ULP_CLASS_HID_f5b0 = 0xf5b0,
+	BNXT_ULP_CLASS_HID_d770 = 0xd770,
+	BNXT_ULP_CLASS_HID_f830 = 0xf830,
+	BNXT_ULP_CLASS_HID_adc4 = 0xadc4,
+	BNXT_ULP_CLASS_HID_ae84 = 0xae84,
+	BNXT_ULP_CLASS_HID_d044 = 0xd044,
+	BNXT_ULP_CLASS_HID_f504 = 0xf504,
+	BNXT_ULP_CLASS_HID_1c3c4 = 0x1c3c4,
+	BNXT_ULP_CLASS_HID_1e484 = 0x1e484,
+	BNXT_ULP_CLASS_HID_1c644 = 0x1c644,
+	BNXT_ULP_CLASS_HID_1eb04 = 0x1eb04,
+	BNXT_ULP_CLASS_HID_1c6f0 = 0x1c6f0,
+	BNXT_ULP_CLASS_HID_1ebb0 = 0x1ebb0,
+	BNXT_ULP_CLASS_HID_1cd70 = 0x1cd70,
+	BNXT_ULP_CLASS_HID_1f304 = 0x1f304,
+	BNXT_ULP_CLASS_HID_99a8 = 0x99a8,
+	BNXT_ULP_CLASS_HID_bb68 = 0xbb68,
+	BNXT_ULP_CLASS_HID_dc28 = 0xdc28,
+	BNXT_ULP_CLASS_HID_e1e8 = 0xe1e8,
+	BNXT_ULP_CLASS_HID_92fc = 0x92fc,
+	BNXT_ULP_CLASS_HID_b7bc = 0xb7bc,
+	BNXT_ULP_CLASS_HID_d97c = 0xd97c,
+	BNXT_ULP_CLASS_HID_fa3c = 0xfa3c,
+	BNXT_ULP_CLASS_HID_188fc = 0x188fc,
+	BNXT_ULP_CLASS_HID_1adbc = 0x1adbc,
+	BNXT_ULP_CLASS_HID_1cf7c = 0x1cf7c,
+	BNXT_ULP_CLASS_HID_1f03c = 0x1f03c,
+	BNXT_ULP_CLASS_HID_18fa8 = 0x18fa8,
+	BNXT_ULP_CLASS_HID_1b168 = 0x1b168,
+	BNXT_ULP_CLASS_HID_1f228 = 0x1f228,
+	BNXT_ULP_CLASS_HID_1f7e8 = 0x1f7e8,
+	BNXT_ULP_CLASS_HID_ba1c = 0xba1c,
+	BNXT_ULP_CLASS_HID_bfdc = 0xbfdc,
+	BNXT_ULP_CLASS_HID_e09c = 0xe09c,
+	BNXT_ULP_CLASS_HID_e25c = 0xe25c,
+	BNXT_ULP_CLASS_HID_b760 = 0xb760,
+	BNXT_ULP_CLASS_HID_b820 = 0xb820,
+	BNXT_ULP_CLASS_HID_fde0 = 0xfde0,
+	BNXT_ULP_CLASS_HID_fea0 = 0xfea0,
+	BNXT_ULP_CLASS_HID_1ad60 = 0x1ad60,
+	BNXT_ULP_CLASS_HID_1ae20 = 0x1ae20,
+	BNXT_ULP_CLASS_HID_1d3e0 = 0x1d3e0,
+	BNXT_ULP_CLASS_HID_1f4a0 = 0x1f4a0,
+	BNXT_ULP_CLASS_HID_1d01c = 0x1d01c,
+	BNXT_ULP_CLASS_HID_1f5dc = 0x1f5dc,
+	BNXT_ULP_CLASS_HID_1d69c = 0x1d69c,
+	BNXT_ULP_CLASS_HID_1f85c = 0x1f85c,
+	BNXT_ULP_CLASS_HID_86c0 = 0x86c0,
+	BNXT_ULP_CLASS_HID_ab80 = 0xab80,
+	BNXT_ULP_CLASS_HID_cd40 = 0xcd40,
+	BNXT_ULP_CLASS_HID_ee00 = 0xee00,
+	BNXT_ULP_CLASS_HID_8314 = 0x8314,
+	BNXT_ULP_CLASS_HID_a4d4 = 0xa4d4,
+	BNXT_ULP_CLASS_HID_c994 = 0xc994,
+	BNXT_ULP_CLASS_HID_eb54 = 0xeb54,
+	BNXT_ULP_CLASS_HID_1b914 = 0x1b914,
+	BNXT_ULP_CLASS_HID_1bad4 = 0x1bad4,
+	BNXT_ULP_CLASS_HID_1ff94 = 0x1ff94,
+	BNXT_ULP_CLASS_HID_1e154 = 0x1e154,
+	BNXT_ULP_CLASS_HID_1bcc0 = 0x1bcc0,
+	BNXT_ULP_CLASS_HID_1a180 = 0x1a180,
+	BNXT_ULP_CLASS_HID_1e340 = 0x1e340,
+	BNXT_ULP_CLASS_HID_1e400 = 0x1e400,
+	BNXT_ULP_CLASS_HID_aab4 = 0xaab4,
+	BNXT_ULP_CLASS_HID_ac74 = 0xac74,
+	BNXT_ULP_CLASS_HID_d134 = 0xd134,
+	BNXT_ULP_CLASS_HID_f2f4 = 0xf2f4,
+	BNXT_ULP_CLASS_HID_a7f8 = 0xa7f8,
+	BNXT_ULP_CLASS_HID_a8b8 = 0xa8b8,
+	BNXT_ULP_CLASS_HID_ea78 = 0xea78,
+	BNXT_ULP_CLASS_HID_ef38 = 0xef38,
+	BNXT_ULP_CLASS_HID_1ddf8 = 0x1ddf8,
+	BNXT_ULP_CLASS_HID_1feb8 = 0x1feb8,
+	BNXT_ULP_CLASS_HID_1c078 = 0x1c078,
+	BNXT_ULP_CLASS_HID_1e538 = 0x1e538,
+	BNXT_ULP_CLASS_HID_1c0b4 = 0x1c0b4,
+	BNXT_ULP_CLASS_HID_1e274 = 0x1e274,
+	BNXT_ULP_CLASS_HID_1c734 = 0x1c734,
+	BNXT_ULP_CLASS_HID_1e8f4 = 0x1e8f4,
+	BNXT_ULP_CLASS_HID_906c = 0x906c,
+	BNXT_ULP_CLASS_HID_b52c = 0xb52c,
+	BNXT_ULP_CLASS_HID_d6ec = 0xd6ec,
+	BNXT_ULP_CLASS_HID_fbac = 0xfbac,
+	BNXT_ULP_CLASS_HID_c86c = 0xc86c,
+	BNXT_ULP_CLASS_HID_ed2c = 0xed2c,
+	BNXT_ULP_CLASS_HID_d330 = 0xd330,
+	BNXT_ULP_CLASS_HID_f4f0 = 0xf4f0,
+	BNXT_ULP_CLASS_HID_182b0 = 0x182b0,
+	BNXT_ULP_CLASS_HID_1a470 = 0x1a470,
+	BNXT_ULP_CLASS_HID_1c930 = 0x1c930,
+	BNXT_ULP_CLASS_HID_1eaf0 = 0x1eaf0,
+	BNXT_ULP_CLASS_HID_1866c = 0x1866c,
+	BNXT_ULP_CLASS_HID_1ab2c = 0x1ab2c,
+	BNXT_ULP_CLASS_HID_1ccec = 0x1ccec,
+	BNXT_ULP_CLASS_HID_1f1ac = 0x1f1ac,
+	BNXT_ULP_CLASS_HID_b4d0 = 0xb4d0,
+	BNXT_ULP_CLASS_HID_b990 = 0xb990,
+	BNXT_ULP_CLASS_HID_fb50 = 0xfb50,
+	BNXT_ULP_CLASS_HID_fc10 = 0xfc10,
+	BNXT_ULP_CLASS_HID_b124 = 0xb124,
+	BNXT_ULP_CLASS_HID_b2e4 = 0xb2e4,
+	BNXT_ULP_CLASS_HID_f7a4 = 0xf7a4,
+	BNXT_ULP_CLASS_HID_f964 = 0xf964,
+	BNXT_ULP_CLASS_HID_1a724 = 0x1a724,
+	BNXT_ULP_CLASS_HID_1a8e4 = 0x1a8e4,
+	BNXT_ULP_CLASS_HID_1eda4 = 0x1eda4,
+	BNXT_ULP_CLASS_HID_1ef64 = 0x1ef64,
+	BNXT_ULP_CLASS_HID_1aad0 = 0x1aad0,
+	BNXT_ULP_CLASS_HID_1af90 = 0x1af90,
+	BNXT_ULP_CLASS_HID_1d150 = 0x1d150,
+	BNXT_ULP_CLASS_HID_1f210 = 0x1f210,
+	BNXT_ULP_CLASS_HID_8084 = 0x8084,
+	BNXT_ULP_CLASS_HID_a244 = 0xa244,
+	BNXT_ULP_CLASS_HID_c704 = 0xc704,
+	BNXT_ULP_CLASS_HID_e8c4 = 0xe8c4,
+	BNXT_ULP_CLASS_HID_9dc8 = 0x9dc8,
+	BNXT_ULP_CLASS_HID_be88 = 0xbe88,
+	BNXT_ULP_CLASS_HID_c048 = 0xc048,
+	BNXT_ULP_CLASS_HID_e508 = 0xe508,
+	BNXT_ULP_CLASS_HID_1b3c8 = 0x1b3c8,
+	BNXT_ULP_CLASS_HID_1b488 = 0x1b488,
+	BNXT_ULP_CLASS_HID_1f648 = 0x1f648,
+	BNXT_ULP_CLASS_HID_1fb08 = 0x1fb08,
+	BNXT_ULP_CLASS_HID_1b684 = 0x1b684,
+	BNXT_ULP_CLASS_HID_1b844 = 0x1b844,
+	BNXT_ULP_CLASS_HID_1fd04 = 0x1fd04,
+	BNXT_ULP_CLASS_HID_1fec4 = 0x1fec4,
+	BNXT_ULP_CLASS_HID_a568 = 0xa568,
+	BNXT_ULP_CLASS_HID_a628 = 0xa628,
+	BNXT_ULP_CLASS_HID_ebe8 = 0xebe8,
+	BNXT_ULP_CLASS_HID_eca8 = 0xeca8,
+	BNXT_ULP_CLASS_HID_a1bc = 0xa1bc,
+	BNXT_ULP_CLASS_HID_a37c = 0xa37c,
+	BNXT_ULP_CLASS_HID_e43c = 0xe43c,
+	BNXT_ULP_CLASS_HID_e9fc = 0xe9fc,
+	BNXT_ULP_CLASS_HID_1d7bc = 0x1d7bc,
+	BNXT_ULP_CLASS_HID_1f97c = 0x1f97c,
+	BNXT_ULP_CLASS_HID_1da3c = 0x1da3c,
+	BNXT_ULP_CLASS_HID_1fffc = 0x1fffc,
+	BNXT_ULP_CLASS_HID_1db68 = 0x1db68,
+	BNXT_ULP_CLASS_HID_1fc28 = 0x1fc28,
+	BNXT_ULP_CLASS_HID_1c1e8 = 0x1c1e8,
+	BNXT_ULP_CLASS_HID_1e2a8 = 0x1e2a8,
+	BNXT_ULP_CLASS_HID_9ab8 = 0x9ab8,
+	BNXT_ULP_CLASS_HID_bc78 = 0xbc78,
+	BNXT_ULP_CLASS_HID_c138 = 0xc138,
+	BNXT_ULP_CLASS_HID_e2f8 = 0xe2f8,
+	BNXT_ULP_CLASS_HID_978c = 0x978c,
+	BNXT_ULP_CLASS_HID_b94c = 0xb94c,
+	BNXT_ULP_CLASS_HID_da0c = 0xda0c,
+	BNXT_ULP_CLASS_HID_ffcc = 0xffcc,
+	BNXT_ULP_CLASS_HID_18d8c = 0x18d8c,
+	BNXT_ULP_CLASS_HID_1af4c = 0x1af4c,
+	BNXT_ULP_CLASS_HID_1f00c = 0x1f00c,
+	BNXT_ULP_CLASS_HID_1f5cc = 0x1f5cc,
+	BNXT_ULP_CLASS_HID_1b0b8 = 0x1b0b8,
+	BNXT_ULP_CLASS_HID_1b278 = 0x1b278,
+	BNXT_ULP_CLASS_HID_1f738 = 0x1f738,
+	BNXT_ULP_CLASS_HID_1f8f8 = 0x1f8f8,
+	BNXT_ULP_CLASS_HID_bf2c = 0xbf2c,
+	BNXT_ULP_CLASS_HID_a0ec = 0xa0ec,
+	BNXT_ULP_CLASS_HID_e5ac = 0xe5ac,
+	BNXT_ULP_CLASS_HID_e76c = 0xe76c,
+	BNXT_ULP_CLASS_HID_b870 = 0xb870,
+	BNXT_ULP_CLASS_HID_bd30 = 0xbd30,
+	BNXT_ULP_CLASS_HID_fef0 = 0xfef0,
+	BNXT_ULP_CLASS_HID_e3b0 = 0xe3b0,
+	BNXT_ULP_CLASS_HID_1ae70 = 0x1ae70,
+	BNXT_ULP_CLASS_HID_1f330 = 0x1f330,
+	BNXT_ULP_CLASS_HID_1d4f0 = 0x1d4f0,
+	BNXT_ULP_CLASS_HID_1f9b0 = 0x1f9b0,
+	BNXT_ULP_CLASS_HID_1d52c = 0x1d52c,
+	BNXT_ULP_CLASS_HID_1f6ec = 0x1f6ec,
+	BNXT_ULP_CLASS_HID_1dbac = 0x1dbac,
+	BNXT_ULP_CLASS_HID_1fd6c = 0x1fd6c,
+	BNXT_ULP_CLASS_HID_34d0 = 0x34d0,
+	BNXT_ULP_CLASS_HID_3a1c = 0x3a1c,
+	BNXT_ULP_CLASS_HID_5e80 = 0x5e80,
+	BNXT_ULP_CLASS_HID_07b8 = 0x07b8,
+	BNXT_ULP_CLASS_HID_282c = 0x282c,
+	BNXT_ULP_CLASS_HID_5944 = 0x5944,
+	BNXT_ULP_CLASS_HID_1e7c = 0x1e7c,
+	BNXT_ULP_CLASS_HID_22e0 = 0x22e0,
+	BNXT_ULP_CLASS_HID_a77c = 0xa77c,
+	BNXT_ULP_CLASS_HID_a8bc = 0xa8bc,
+	BNXT_ULP_CLASS_HID_edfc = 0xedfc,
+	BNXT_ULP_CLASS_HID_ef3c = 0xef3c,
+	BNXT_ULP_CLASS_HID_a000 = 0xa000,
+	BNXT_ULP_CLASS_HID_a540 = 0xa540,
+	BNXT_ULP_CLASS_HID_e680 = 0xe680,
+	BNXT_ULP_CLASS_HID_ebc0 = 0xebc0,
+	BNXT_ULP_CLASS_HID_1d600 = 0x1d600,
+	BNXT_ULP_CLASS_HID_1fb40 = 0x1fb40,
+	BNXT_ULP_CLASS_HID_1dc80 = 0x1dc80,
+	BNXT_ULP_CLASS_HID_1e1c0 = 0x1e1c0,
+	BNXT_ULP_CLASS_HID_1dd7c = 0x1dd7c,
+	BNXT_ULP_CLASS_HID_1febc = 0x1febc,
+	BNXT_ULP_CLASS_HID_1c3fc = 0x1c3fc,
+	BNXT_ULP_CLASS_HID_1e53c = 0x1e53c,
+	BNXT_ULP_CLASS_HID_cbe0 = 0xcbe0,
+	BNXT_ULP_CLASS_HID_b1f4 = 0xb1f4,
+	BNXT_ULP_CLASS_HID_d334 = 0xd334,
+	BNXT_ULP_CLASS_HID_f474 = 0xf474,
+	BNXT_ULP_CLASS_HID_c4b4 = 0xc4b4,
+	BNXT_ULP_CLASS_HID_e9f4 = 0xe9f4,
+	BNXT_ULP_CLASS_HID_cb34 = 0xcb34,
+	BNXT_ULP_CLASS_HID_f138 = 0xf138,
+	BNXT_ULP_CLASS_HID_19f78 = 0x19f78,
+	BNXT_ULP_CLASS_HID_1a0b8 = 0x1a0b8,
+	BNXT_ULP_CLASS_HID_1c5f8 = 0x1c5f8,
+	BNXT_ULP_CLASS_HID_1e738 = 0x1e738,
+	BNXT_ULP_CLASS_HID_182b4 = 0x182b4,
+	BNXT_ULP_CLASS_HID_1a7f4 = 0x1a7f4,
+	BNXT_ULP_CLASS_HID_1c934 = 0x1c934,
+	BNXT_ULP_CLASS_HID_1ea74 = 0x1ea74,
+	BNXT_ULP_CLASS_HID_b0d8 = 0xb0d8,
+	BNXT_ULP_CLASS_HID_b218 = 0xb218,
+	BNXT_ULP_CLASS_HID_f758 = 0xf758,
+	BNXT_ULP_CLASS_HID_f898 = 0xf898,
+	BNXT_ULP_CLASS_HID_8dec = 0x8dec,
+	BNXT_ULP_CLASS_HID_af2c = 0xaf2c,
+	BNXT_ULP_CLASS_HID_f06c = 0xf06c,
+	BNXT_ULP_CLASS_HID_f5ac = 0xf5ac,
+	BNXT_ULP_CLASS_HID_1a3ec = 0x1a3ec,
+	BNXT_ULP_CLASS_HID_1a52c = 0x1a52c,
+	BNXT_ULP_CLASS_HID_1e66c = 0x1e66c,
+	BNXT_ULP_CLASS_HID_1ebac = 0x1ebac,
+	BNXT_ULP_CLASS_HID_1a6d8 = 0x1a6d8,
+	BNXT_ULP_CLASS_HID_1a818 = 0x1a818,
+	BNXT_ULP_CLASS_HID_1ed58 = 0x1ed58,
+	BNXT_ULP_CLASS_HID_1ee98 = 0x1ee98,
+	BNXT_ULP_CLASS_HID_d54c = 0xd54c,
+	BNXT_ULP_CLASS_HID_f68c = 0xf68c,
+	BNXT_ULP_CLASS_HID_dbcc = 0xdbcc,
+	BNXT_ULP_CLASS_HID_fd0c = 0xfd0c,
+	BNXT_ULP_CLASS_HID_ae10 = 0xae10,
+	BNXT_ULP_CLASS_HID_f350 = 0xf350,
+	BNXT_ULP_CLASS_HID_d490 = 0xd490,
+	BNXT_ULP_CLASS_HID_f9d0 = 0xf9d0,
+	BNXT_ULP_CLASS_HID_1c410 = 0x1c410,
+	BNXT_ULP_CLASS_HID_1e950 = 0x1e950,
+	BNXT_ULP_CLASS_HID_1ca90 = 0x1ca90,
+	BNXT_ULP_CLASS_HID_1f0e4 = 0x1f0e4,
+	BNXT_ULP_CLASS_HID_1cb4c = 0x1cb4c,
+	BNXT_ULP_CLASS_HID_1b150 = 0x1b150,
+	BNXT_ULP_CLASS_HID_1d290 = 0x1d290,
+	BNXT_ULP_CLASS_HID_1f7d0 = 0x1f7d0,
+	BNXT_ULP_CLASS_HID_a1b0 = 0xa1b0,
+	BNXT_ULP_CLASS_HID_a2f0 = 0xa2f0,
+	BNXT_ULP_CLASS_HID_e430 = 0xe430,
+	BNXT_ULP_CLASS_HID_e970 = 0xe970,
+	BNXT_ULP_CLASS_HID_ba44 = 0xba44,
+	BNXT_ULP_CLASS_HID_bf84 = 0xbf84,
+	BNXT_ULP_CLASS_HID_e0c4 = 0xe0c4,
+	BNXT_ULP_CLASS_HID_e204 = 0xe204,
+	BNXT_ULP_CLASS_HID_1d044 = 0x1d044,
+	BNXT_ULP_CLASS_HID_1f584 = 0x1f584,
+	BNXT_ULP_CLASS_HID_1d6c4 = 0x1d6c4,
+	BNXT_ULP_CLASS_HID_1f804 = 0x1f804,
+	BNXT_ULP_CLASS_HID_1d7b0 = 0x1d7b0,
+	BNXT_ULP_CLASS_HID_1f8f0 = 0x1f8f0,
+	BNXT_ULP_CLASS_HID_1da30 = 0x1da30,
+	BNXT_ULP_CLASS_HID_1ff70 = 0x1ff70,
+	BNXT_ULP_CLASS_HID_c224 = 0xc224,
+	BNXT_ULP_CLASS_HID_e764 = 0xe764,
+	BNXT_ULP_CLASS_HID_c8a4 = 0xc8a4,
+	BNXT_ULP_CLASS_HID_ede4 = 0xede4,
+	BNXT_ULP_CLASS_HID_dee8 = 0xdee8,
+	BNXT_ULP_CLASS_HID_e028 = 0xe028,
+	BNXT_ULP_CLASS_HID_c568 = 0xc568,
+	BNXT_ULP_CLASS_HID_e6a8 = 0xe6a8,
+	BNXT_ULP_CLASS_HID_199bc = 0x199bc,
+	BNXT_ULP_CLASS_HID_1bafc = 0x1bafc,
+	BNXT_ULP_CLASS_HID_1dc3c = 0x1dc3c,
+	BNXT_ULP_CLASS_HID_1e17c = 0x1e17c,
+	BNXT_ULP_CLASS_HID_19ce8 = 0x19ce8,
+	BNXT_ULP_CLASS_HID_1be28 = 0x1be28,
+	BNXT_ULP_CLASS_HID_1c368 = 0x1c368,
+	BNXT_ULP_CLASS_HID_1e4a8 = 0x1e4a8,
+	BNXT_ULP_CLASS_HID_8b1c = 0x8b1c,
+	BNXT_ULP_CLASS_HID_ac5c = 0xac5c,
+	BNXT_ULP_CLASS_HID_f19c = 0xf19c,
+	BNXT_ULP_CLASS_HID_f2dc = 0xf2dc,
+	BNXT_ULP_CLASS_HID_8420 = 0x8420,
+	BNXT_ULP_CLASS_HID_a960 = 0xa960,
+	BNXT_ULP_CLASS_HID_caa0 = 0xcaa0,
+	BNXT_ULP_CLASS_HID_efe0 = 0xefe0,
+	BNXT_ULP_CLASS_HID_1ba20 = 0x1ba20,
+	BNXT_ULP_CLASS_HID_1bf60 = 0x1bf60,
+	BNXT_ULP_CLASS_HID_1e0a0 = 0x1e0a0,
+	BNXT_ULP_CLASS_HID_1e5e0 = 0x1e5e0,
+	BNXT_ULP_CLASS_HID_1a11c = 0x1a11c,
+	BNXT_ULP_CLASS_HID_1a25c = 0x1a25c,
+	BNXT_ULP_CLASS_HID_1e79c = 0x1e79c,
+	BNXT_ULP_CLASS_HID_1e8dc = 0x1e8dc,
+	BNXT_ULP_CLASS_HID_af80 = 0xaf80,
+	BNXT_ULP_CLASS_HID_f0c0 = 0xf0c0,
+	BNXT_ULP_CLASS_HID_d200 = 0xd200,
+	BNXT_ULP_CLASS_HID_f740 = 0xf740,
+	BNXT_ULP_CLASS_HID_a854 = 0xa854,
+	BNXT_ULP_CLASS_HID_ad94 = 0xad94,
+	BNXT_ULP_CLASS_HID_eed4 = 0xeed4,
+	BNXT_ULP_CLASS_HID_f014 = 0xf014,
+	BNXT_ULP_CLASS_HID_1de54 = 0x1de54,
+	BNXT_ULP_CLASS_HID_1e394 = 0x1e394,
+	BNXT_ULP_CLASS_HID_1c4d4 = 0x1c4d4,
+	BNXT_ULP_CLASS_HID_1e614 = 0x1e614,
+	BNXT_ULP_CLASS_HID_1c580 = 0x1c580,
+	BNXT_ULP_CLASS_HID_1e6c0 = 0x1e6c0,
+	BNXT_ULP_CLASS_HID_1c800 = 0x1c800,
+	BNXT_ULP_CLASS_HID_1ed40 = 0x1ed40,
+	BNXT_ULP_CLASS_HID_8c6c = 0x8c6c,
+	BNXT_ULP_CLASS_HID_b1ac = 0xb1ac,
+	BNXT_ULP_CLASS_HID_f2ec = 0xf2ec,
+	BNXT_ULP_CLASS_HID_f42c = 0xf42c,
+	BNXT_ULP_CLASS_HID_8930 = 0x8930,
+	BNXT_ULP_CLASS_HID_aa70 = 0xaa70,
+	BNXT_ULP_CLASS_HID_cfb0 = 0xcfb0,
+	BNXT_ULP_CLASS_HID_f0f0 = 0xf0f0,
+	BNXT_ULP_CLASS_HID_1bf30 = 0x1bf30,
+	BNXT_ULP_CLASS_HID_1a070 = 0x1a070,
+	BNXT_ULP_CLASS_HID_1e5b0 = 0x1e5b0,
+	BNXT_ULP_CLASS_HID_1e6f0 = 0x1e6f0,
+	BNXT_ULP_CLASS_HID_1a26c = 0x1a26c,
+	BNXT_ULP_CLASS_HID_1a7ac = 0x1a7ac,
+	BNXT_ULP_CLASS_HID_1e8ec = 0x1e8ec,
+	BNXT_ULP_CLASS_HID_1ea2c = 0x1ea2c,
+	BNXT_ULP_CLASS_HID_d090 = 0xd090,
+	BNXT_ULP_CLASS_HID_f5d0 = 0xf5d0,
+	BNXT_ULP_CLASS_HID_d710 = 0xd710,
+	BNXT_ULP_CLASS_HID_f850 = 0xf850,
+	BNXT_ULP_CLASS_HID_ada4 = 0xada4,
+	BNXT_ULP_CLASS_HID_aee4 = 0xaee4,
+	BNXT_ULP_CLASS_HID_d024 = 0xd024,
+	BNXT_ULP_CLASS_HID_f564 = 0xf564,
+	BNXT_ULP_CLASS_HID_1c3a4 = 0x1c3a4,
+	BNXT_ULP_CLASS_HID_1e4e4 = 0x1e4e4,
+	BNXT_ULP_CLASS_HID_1c624 = 0x1c624,
+	BNXT_ULP_CLASS_HID_1eb64 = 0x1eb64,
+	BNXT_ULP_CLASS_HID_1c690 = 0x1c690,
+	BNXT_ULP_CLASS_HID_1ebd0 = 0x1ebd0,
+	BNXT_ULP_CLASS_HID_1cd10 = 0x1cd10,
+	BNXT_ULP_CLASS_HID_1f364 = 0x1f364,
+	BNXT_ULP_CLASS_HID_99c8 = 0x99c8,
+	BNXT_ULP_CLASS_HID_bb08 = 0xbb08,
+	BNXT_ULP_CLASS_HID_dc48 = 0xdc48,
+	BNXT_ULP_CLASS_HID_e188 = 0xe188,
+	BNXT_ULP_CLASS_HID_929c = 0x929c,
+	BNXT_ULP_CLASS_HID_b7dc = 0xb7dc,
+	BNXT_ULP_CLASS_HID_d91c = 0xd91c,
+	BNXT_ULP_CLASS_HID_fa5c = 0xfa5c,
+	BNXT_ULP_CLASS_HID_1889c = 0x1889c,
+	BNXT_ULP_CLASS_HID_1addc = 0x1addc,
+	BNXT_ULP_CLASS_HID_1cf1c = 0x1cf1c,
+	BNXT_ULP_CLASS_HID_1f05c = 0x1f05c,
+	BNXT_ULP_CLASS_HID_18fc8 = 0x18fc8,
+	BNXT_ULP_CLASS_HID_1b108 = 0x1b108,
+	BNXT_ULP_CLASS_HID_1f248 = 0x1f248,
+	BNXT_ULP_CLASS_HID_1f788 = 0x1f788,
+	BNXT_ULP_CLASS_HID_ba7c = 0xba7c,
+	BNXT_ULP_CLASS_HID_bfbc = 0xbfbc,
+	BNXT_ULP_CLASS_HID_e0fc = 0xe0fc,
+	BNXT_ULP_CLASS_HID_e23c = 0xe23c,
+	BNXT_ULP_CLASS_HID_b700 = 0xb700,
+	BNXT_ULP_CLASS_HID_b840 = 0xb840,
+	BNXT_ULP_CLASS_HID_fd80 = 0xfd80,
+	BNXT_ULP_CLASS_HID_fec0 = 0xfec0,
+	BNXT_ULP_CLASS_HID_1ad00 = 0x1ad00,
+	BNXT_ULP_CLASS_HID_1ae40 = 0x1ae40,
+	BNXT_ULP_CLASS_HID_1d380 = 0x1d380,
+	BNXT_ULP_CLASS_HID_1f4c0 = 0x1f4c0,
+	BNXT_ULP_CLASS_HID_1d07c = 0x1d07c,
+	BNXT_ULP_CLASS_HID_1f5bc = 0x1f5bc,
+	BNXT_ULP_CLASS_HID_1d6fc = 0x1d6fc,
+	BNXT_ULP_CLASS_HID_1f83c = 0x1f83c,
+	BNXT_ULP_CLASS_HID_86a0 = 0x86a0,
+	BNXT_ULP_CLASS_HID_abe0 = 0xabe0,
+	BNXT_ULP_CLASS_HID_cd20 = 0xcd20,
+	BNXT_ULP_CLASS_HID_ee60 = 0xee60,
+	BNXT_ULP_CLASS_HID_8374 = 0x8374,
+	BNXT_ULP_CLASS_HID_a4b4 = 0xa4b4,
+	BNXT_ULP_CLASS_HID_c9f4 = 0xc9f4,
+	BNXT_ULP_CLASS_HID_eb34 = 0xeb34,
+	BNXT_ULP_CLASS_HID_1b974 = 0x1b974,
+	BNXT_ULP_CLASS_HID_1bab4 = 0x1bab4,
+	BNXT_ULP_CLASS_HID_1fff4 = 0x1fff4,
+	BNXT_ULP_CLASS_HID_1e134 = 0x1e134,
+	BNXT_ULP_CLASS_HID_1bca0 = 0x1bca0,
+	BNXT_ULP_CLASS_HID_1a1e0 = 0x1a1e0,
+	BNXT_ULP_CLASS_HID_1e320 = 0x1e320,
+	BNXT_ULP_CLASS_HID_1e460 = 0x1e460,
+	BNXT_ULP_CLASS_HID_aad4 = 0xaad4,
+	BNXT_ULP_CLASS_HID_ac14 = 0xac14,
+	BNXT_ULP_CLASS_HID_d154 = 0xd154,
+	BNXT_ULP_CLASS_HID_f294 = 0xf294,
+	BNXT_ULP_CLASS_HID_a798 = 0xa798,
+	BNXT_ULP_CLASS_HID_a8d8 = 0xa8d8,
+	BNXT_ULP_CLASS_HID_ea18 = 0xea18,
+	BNXT_ULP_CLASS_HID_ef58 = 0xef58,
+	BNXT_ULP_CLASS_HID_1dd98 = 0x1dd98,
+	BNXT_ULP_CLASS_HID_1fed8 = 0x1fed8,
+	BNXT_ULP_CLASS_HID_1c018 = 0x1c018,
+	BNXT_ULP_CLASS_HID_1e558 = 0x1e558,
+	BNXT_ULP_CLASS_HID_1c0d4 = 0x1c0d4,
+	BNXT_ULP_CLASS_HID_1e214 = 0x1e214,
+	BNXT_ULP_CLASS_HID_1c754 = 0x1c754,
+	BNXT_ULP_CLASS_HID_1e894 = 0x1e894,
+	BNXT_ULP_CLASS_HID_900c = 0x900c,
+	BNXT_ULP_CLASS_HID_b54c = 0xb54c,
+	BNXT_ULP_CLASS_HID_d68c = 0xd68c,
+	BNXT_ULP_CLASS_HID_fbcc = 0xfbcc,
+	BNXT_ULP_CLASS_HID_c80c = 0xc80c,
+	BNXT_ULP_CLASS_HID_ed4c = 0xed4c,
+	BNXT_ULP_CLASS_HID_d350 = 0xd350,
+	BNXT_ULP_CLASS_HID_f490 = 0xf490,
+	BNXT_ULP_CLASS_HID_182d0 = 0x182d0,
+	BNXT_ULP_CLASS_HID_1a410 = 0x1a410,
+	BNXT_ULP_CLASS_HID_1c950 = 0x1c950,
+	BNXT_ULP_CLASS_HID_1ea90 = 0x1ea90,
+	BNXT_ULP_CLASS_HID_1860c = 0x1860c,
+	BNXT_ULP_CLASS_HID_1ab4c = 0x1ab4c,
+	BNXT_ULP_CLASS_HID_1cc8c = 0x1cc8c,
+	BNXT_ULP_CLASS_HID_1f1cc = 0x1f1cc,
+	BNXT_ULP_CLASS_HID_b4b0 = 0xb4b0,
+	BNXT_ULP_CLASS_HID_b9f0 = 0xb9f0,
+	BNXT_ULP_CLASS_HID_fb30 = 0xfb30,
+	BNXT_ULP_CLASS_HID_fc70 = 0xfc70,
+	BNXT_ULP_CLASS_HID_b144 = 0xb144,
+	BNXT_ULP_CLASS_HID_b284 = 0xb284,
+	BNXT_ULP_CLASS_HID_f7c4 = 0xf7c4,
+	BNXT_ULP_CLASS_HID_f904 = 0xf904,
+	BNXT_ULP_CLASS_HID_1a744 = 0x1a744,
+	BNXT_ULP_CLASS_HID_1a884 = 0x1a884,
+	BNXT_ULP_CLASS_HID_1edc4 = 0x1edc4,
+	BNXT_ULP_CLASS_HID_1ef04 = 0x1ef04,
+	BNXT_ULP_CLASS_HID_1aab0 = 0x1aab0,
+	BNXT_ULP_CLASS_HID_1aff0 = 0x1aff0,
+	BNXT_ULP_CLASS_HID_1d130 = 0x1d130,
+	BNXT_ULP_CLASS_HID_1f270 = 0x1f270,
+	BNXT_ULP_CLASS_HID_80e4 = 0x80e4,
+	BNXT_ULP_CLASS_HID_a224 = 0xa224,
+	BNXT_ULP_CLASS_HID_c764 = 0xc764,
+	BNXT_ULP_CLASS_HID_e8a4 = 0xe8a4,
+	BNXT_ULP_CLASS_HID_9da8 = 0x9da8,
+	BNXT_ULP_CLASS_HID_bee8 = 0xbee8,
+	BNXT_ULP_CLASS_HID_c028 = 0xc028,
+	BNXT_ULP_CLASS_HID_e568 = 0xe568,
+	BNXT_ULP_CLASS_HID_1b3a8 = 0x1b3a8,
+	BNXT_ULP_CLASS_HID_1b4e8 = 0x1b4e8,
+	BNXT_ULP_CLASS_HID_1f628 = 0x1f628,
+	BNXT_ULP_CLASS_HID_1fb68 = 0x1fb68,
+	BNXT_ULP_CLASS_HID_1b6e4 = 0x1b6e4,
+	BNXT_ULP_CLASS_HID_1b824 = 0x1b824,
+	BNXT_ULP_CLASS_HID_1fd64 = 0x1fd64,
+	BNXT_ULP_CLASS_HID_1fea4 = 0x1fea4,
+	BNXT_ULP_CLASS_HID_a508 = 0xa508,
+	BNXT_ULP_CLASS_HID_a648 = 0xa648,
+	BNXT_ULP_CLASS_HID_eb88 = 0xeb88,
+	BNXT_ULP_CLASS_HID_ecc8 = 0xecc8,
+	BNXT_ULP_CLASS_HID_a1dc = 0xa1dc,
+	BNXT_ULP_CLASS_HID_a31c = 0xa31c,
+	BNXT_ULP_CLASS_HID_e45c = 0xe45c,
+	BNXT_ULP_CLASS_HID_e99c = 0xe99c,
+	BNXT_ULP_CLASS_HID_1d7dc = 0x1d7dc,
+	BNXT_ULP_CLASS_HID_1f91c = 0x1f91c,
+	BNXT_ULP_CLASS_HID_1da5c = 0x1da5c,
+	BNXT_ULP_CLASS_HID_1ff9c = 0x1ff9c,
+	BNXT_ULP_CLASS_HID_1db08 = 0x1db08,
+	BNXT_ULP_CLASS_HID_1fc48 = 0x1fc48,
+	BNXT_ULP_CLASS_HID_1c188 = 0x1c188,
+	BNXT_ULP_CLASS_HID_1e2c8 = 0x1e2c8,
+	BNXT_ULP_CLASS_HID_9ad8 = 0x9ad8,
+	BNXT_ULP_CLASS_HID_bc18 = 0xbc18,
+	BNXT_ULP_CLASS_HID_c158 = 0xc158,
+	BNXT_ULP_CLASS_HID_e298 = 0xe298,
+	BNXT_ULP_CLASS_HID_97ec = 0x97ec,
+	BNXT_ULP_CLASS_HID_b92c = 0xb92c,
+	BNXT_ULP_CLASS_HID_da6c = 0xda6c,
+	BNXT_ULP_CLASS_HID_ffac = 0xffac,
+	BNXT_ULP_CLASS_HID_18dec = 0x18dec,
+	BNXT_ULP_CLASS_HID_1af2c = 0x1af2c,
+	BNXT_ULP_CLASS_HID_1f06c = 0x1f06c,
+	BNXT_ULP_CLASS_HID_1f5ac = 0x1f5ac,
+	BNXT_ULP_CLASS_HID_1b0d8 = 0x1b0d8,
+	BNXT_ULP_CLASS_HID_1b218 = 0x1b218,
+	BNXT_ULP_CLASS_HID_1f758 = 0x1f758,
+	BNXT_ULP_CLASS_HID_1f898 = 0x1f898,
+	BNXT_ULP_CLASS_HID_bf4c = 0xbf4c,
+	BNXT_ULP_CLASS_HID_a08c = 0xa08c,
+	BNXT_ULP_CLASS_HID_e5cc = 0xe5cc,
+	BNXT_ULP_CLASS_HID_e70c = 0xe70c,
+	BNXT_ULP_CLASS_HID_b810 = 0xb810,
+	BNXT_ULP_CLASS_HID_bd50 = 0xbd50,
+	BNXT_ULP_CLASS_HID_fe90 = 0xfe90,
+	BNXT_ULP_CLASS_HID_e3d0 = 0xe3d0,
+	BNXT_ULP_CLASS_HID_1ae10 = 0x1ae10,
+	BNXT_ULP_CLASS_HID_1f350 = 0x1f350,
+	BNXT_ULP_CLASS_HID_1d490 = 0x1d490,
+	BNXT_ULP_CLASS_HID_1f9d0 = 0x1f9d0,
+	BNXT_ULP_CLASS_HID_1d54c = 0x1d54c,
+	BNXT_ULP_CLASS_HID_1f68c = 0x1f68c,
+	BNXT_ULP_CLASS_HID_1dbcc = 0x1dbcc,
+	BNXT_ULP_CLASS_HID_1fd0c = 0x1fd0c,
+	BNXT_ULP_CLASS_HID_34b0 = 0x34b0,
+	BNXT_ULP_CLASS_HID_3a7c = 0x3a7c,
+	BNXT_ULP_CLASS_HID_5ee0 = 0x5ee0,
+	BNXT_ULP_CLASS_HID_07d8 = 0x07d8,
+	BNXT_ULP_CLASS_HID_284c = 0x284c,
+	BNXT_ULP_CLASS_HID_5924 = 0x5924,
+	BNXT_ULP_CLASS_HID_1e1c = 0x1e1c,
+	BNXT_ULP_CLASS_HID_2280 = 0x2280,
+	BNXT_ULP_CLASS_HID_24604 = 0x24604,
+	BNXT_ULP_CLASS_HID_255d4 = 0x255d4,
+	BNXT_ULP_CLASS_HID_22e08 = 0x22e08,
+	BNXT_ULP_CLASS_HID_24378 = 0x24378,
+	BNXT_ULP_CLASS_HID_20fcc = 0x20fcc,
+	BNXT_ULP_CLASS_HID_21a9c = 0x21a9c,
+	BNXT_ULP_CLASS_HID_217d0 = 0x217d0,
+	BNXT_ULP_CLASS_HID_20800 = 0x20800,
+	BNXT_ULP_CLASS_HID_253a0 = 0x253a0,
+	BNXT_ULP_CLASS_HID_23f70 = 0x23f70,
+	BNXT_ULP_CLASS_HID_23ba4 = 0x23ba4,
+	BNXT_ULP_CLASS_HID_22c94 = 0x22c94,
+	BNXT_ULP_CLASS_HID_21968 = 0x21968,
+	BNXT_ULP_CLASS_HID_243c4 = 0x243c4,
+	BNXT_ULP_CLASS_HID_25c38 = 0x25c38,
+	BNXT_ULP_CLASS_HID_2125c = 0x2125c,
+	BNXT_ULP_CLASS_HID_240c8 = 0x240c8,
+	BNXT_ULP_CLASS_HID_22f98 = 0x22f98,
+	BNXT_ULP_CLASS_HID_228cc = 0x228cc,
+	BNXT_ULP_CLASS_HID_25d3c = 0x25d3c,
+	BNXT_ULP_CLASS_HID_20990 = 0x20990,
+	BNXT_ULP_CLASS_HID_214a0 = 0x214a0,
+	BNXT_ULP_CLASS_HID_21194 = 0x21194,
+	BNXT_ULP_CLASS_HID_202c4 = 0x202c4,
+	BNXT_ULP_CLASS_HID_22a64 = 0x22a64,
+	BNXT_ULP_CLASS_HID_23934 = 0x23934,
+	BNXT_ULP_CLASS_HID_23268 = 0x23268,
+	BNXT_ULP_CLASS_HID_22758 = 0x22758,
+	BNXT_ULP_CLASS_HID_2132c = 0x2132c,
+	BNXT_ULP_CLASS_HID_25d88 = 0x25d88,
+	BNXT_ULP_CLASS_HID_256fc = 0x256fc,
+	BNXT_ULP_CLASS_HID_24b2c = 0x24b2c,
+	BNXT_ULP_CLASS_HID_22f14 = 0x22f14,
+	BNXT_ULP_CLASS_HID_23a24 = 0x23a24,
+	BNXT_ULP_CLASS_HID_23718 = 0x23718,
+	BNXT_ULP_CLASS_HID_22848 = 0x22848,
+	BNXT_ULP_CLASS_HID_214dc = 0x214dc,
+	BNXT_ULP_CLASS_HID_25eb8 = 0x25eb8,
+	BNXT_ULP_CLASS_HID_25bec = 0x25bec,
+	BNXT_ULP_CLASS_HID_21110 = 0x21110,
+	BNXT_ULP_CLASS_HID_238b0 = 0x238b0,
+	BNXT_ULP_CLASS_HID_20440 = 0x20440,
+	BNXT_ULP_CLASS_HID_200b4 = 0x200b4,
+	BNXT_ULP_CLASS_HID_235e4 = 0x235e4,
+	BNXT_ULP_CLASS_HID_25d04 = 0x25d04,
+	BNXT_ULP_CLASS_HID_228d4 = 0x228d4,
+	BNXT_ULP_CLASS_HID_22508 = 0x22508,
+	BNXT_ULP_CLASS_HID_25678 = 0x25678,
+	BNXT_ULP_CLASS_HID_229d8 = 0x229d8,
+	BNXT_ULP_CLASS_HID_234e8 = 0x234e8,
+	BNXT_ULP_CLASS_HID_231dc = 0x231dc,
+	BNXT_ULP_CLASS_HID_2220c = 0x2220c,
+	BNXT_ULP_CLASS_HID_24dac = 0x24dac,
+	BNXT_ULP_CLASS_HID_2597c = 0x2597c,
+	BNXT_ULP_CLASS_HID_255b0 = 0x255b0,
+	BNXT_ULP_CLASS_HID_246e0 = 0x246e0,
+	BNXT_ULP_CLASS_HID_23374 = 0x23374,
+	BNXT_ULP_CLASS_HID_21e04 = 0x21e04,
+	BNXT_ULP_CLASS_HID_21b78 = 0x21b78,
+	BNXT_ULP_CLASS_HID_20fa8 = 0x20fa8,
+	BNXT_ULP_CLASS_HID_257c8 = 0x257c8,
+	BNXT_ULP_CLASS_HID_22298 = 0x22298,
+	BNXT_ULP_CLASS_HID_23fcc = 0x23fcc,
+	BNXT_ULP_CLASS_HID_2503c = 0x2503c,
+	BNXT_ULP_CLASS_HID_2239c = 0x2239c,
+	BNXT_ULP_CLASS_HID_20eac = 0x20eac,
+	BNXT_ULP_CLASS_HID_20be0 = 0x20be0,
+	BNXT_ULP_CLASS_HID_23cd0 = 0x23cd0,
+	BNXT_ULP_CLASS_HID_24470 = 0x24470,
+	BNXT_ULP_CLASS_HID_25300 = 0x25300,
+	BNXT_ULP_CLASS_HID_22c74 = 0x22c74,
+	BNXT_ULP_CLASS_HID_240a4 = 0x240a4,
+	BNXT_ULP_CLASS_HID_23da0 = 0x23da0,
+	BNXT_ULP_CLASS_HID_20970 = 0x20970,
+	BNXT_ULP_CLASS_HID_205a4 = 0x205a4,
+	BNXT_ULP_CLASS_HID_23694 = 0x23694,
+	BNXT_ULP_CLASS_HID_25e34 = 0x25e34,
+	BNXT_ULP_CLASS_HID_22dc4 = 0x22dc4,
+	BNXT_ULP_CLASS_HID_22638 = 0x22638,
+	BNXT_ULP_CLASS_HID_25b68 = 0x25b68,
+	BNXT_ULP_CLASS_HID_34c8 = 0x34c8,
+	BNXT_ULP_CLASS_HID_3a04 = 0x3a04,
+	BNXT_ULP_CLASS_HID_5e98 = 0x5e98,
+	BNXT_ULP_CLASS_HID_07a0 = 0x07a0,
+	BNXT_ULP_CLASS_HID_2834 = 0x2834,
+	BNXT_ULP_CLASS_HID_595c = 0x595c,
+	BNXT_ULP_CLASS_HID_1e64 = 0x1e64,
+	BNXT_ULP_CLASS_HID_22f8 = 0x22f8,
+	BNXT_ULP_CLASS_HID_24664 = 0x24664,
+	BNXT_ULP_CLASS_HID_29418 = 0x29418,
+	BNXT_ULP_CLASS_HID_30118 = 0x30118,
+	BNXT_ULP_CLASS_HID_38a18 = 0x38a18,
+	BNXT_ULP_CLASS_HID_255b4 = 0x255b4,
+	BNXT_ULP_CLASS_HID_2deb4 = 0x2deb4,
+	BNXT_ULP_CLASS_HID_34bb4 = 0x34bb4,
+	BNXT_ULP_CLASS_HID_39968 = 0x39968,
+	BNXT_ULP_CLASS_HID_22e68 = 0x22e68,
+	BNXT_ULP_CLASS_HID_2db68 = 0x2db68,
+	BNXT_ULP_CLASS_HID_34468 = 0x34468,
+	BNXT_ULP_CLASS_HID_3921c = 0x3921c,
+	BNXT_ULP_CLASS_HID_24318 = 0x24318,
+	BNXT_ULP_CLASS_HID_290cc = 0x290cc,
+	BNXT_ULP_CLASS_HID_31dcc = 0x31dcc,
+	BNXT_ULP_CLASS_HID_386cc = 0x386cc,
+	BNXT_ULP_CLASS_HID_20fac = 0x20fac,
+	BNXT_ULP_CLASS_HID_2b8ac = 0x2b8ac,
+	BNXT_ULP_CLASS_HID_325ac = 0x325ac,
+	BNXT_ULP_CLASS_HID_3aeac = 0x3aeac,
+	BNXT_ULP_CLASS_HID_21afc = 0x21afc,
+	BNXT_ULP_CLASS_HID_287fc = 0x287fc,
+	BNXT_ULP_CLASS_HID_330fc = 0x330fc,
+	BNXT_ULP_CLASS_HID_3bdfc = 0x3bdfc,
+	BNXT_ULP_CLASS_HID_217b0 = 0x217b0,
+	BNXT_ULP_CLASS_HID_280b0 = 0x280b0,
+	BNXT_ULP_CLASS_HID_30db0 = 0x30db0,
+	BNXT_ULP_CLASS_HID_3b6b0 = 0x3b6b0,
+	BNXT_ULP_CLASS_HID_20860 = 0x20860,
+	BNXT_ULP_CLASS_HID_2b560 = 0x2b560,
+	BNXT_ULP_CLASS_HID_33e60 = 0x33e60,
+	BNXT_ULP_CLASS_HID_3ab60 = 0x3ab60,
+	BNXT_ULP_CLASS_HID_253c0 = 0x253c0,
+	BNXT_ULP_CLASS_HID_2dcc0 = 0x2dcc0,
+	BNXT_ULP_CLASS_HID_349c0 = 0x349c0,
+	BNXT_ULP_CLASS_HID_397f4 = 0x397f4,
+	BNXT_ULP_CLASS_HID_23f10 = 0x23f10,
+	BNXT_ULP_CLASS_HID_2a810 = 0x2a810,
+	BNXT_ULP_CLASS_HID_35510 = 0x35510,
+	BNXT_ULP_CLASS_HID_3de10 = 0x3de10,
+	BNXT_ULP_CLASS_HID_23bc4 = 0x23bc4,
+	BNXT_ULP_CLASS_HID_2a4c4 = 0x2a4c4,
+	BNXT_ULP_CLASS_HID_351c4 = 0x351c4,
+	BNXT_ULP_CLASS_HID_3dac4 = 0x3dac4,
+	BNXT_ULP_CLASS_HID_22cf4 = 0x22cf4,
+	BNXT_ULP_CLASS_HID_2d9f4 = 0x2d9f4,
+	BNXT_ULP_CLASS_HID_342f4 = 0x342f4,
+	BNXT_ULP_CLASS_HID_390a8 = 0x390a8,
+	BNXT_ULP_CLASS_HID_21908 = 0x21908,
+	BNXT_ULP_CLASS_HID_28208 = 0x28208,
+	BNXT_ULP_CLASS_HID_30f08 = 0x30f08,
+	BNXT_ULP_CLASS_HID_3b808 = 0x3b808,
+	BNXT_ULP_CLASS_HID_243a4 = 0x243a4,
+	BNXT_ULP_CLASS_HID_29158 = 0x29158,
+	BNXT_ULP_CLASS_HID_31a58 = 0x31a58,
+	BNXT_ULP_CLASS_HID_38758 = 0x38758,
+	BNXT_ULP_CLASS_HID_25c58 = 0x25c58,
+	BNXT_ULP_CLASS_HID_2c958 = 0x2c958,
+	BNXT_ULP_CLASS_HID_3170c = 0x3170c,
+	BNXT_ULP_CLASS_HID_3800c = 0x3800c,
+	BNXT_ULP_CLASS_HID_2123c = 0x2123c,
+	BNXT_ULP_CLASS_HID_29f3c = 0x29f3c,
+	BNXT_ULP_CLASS_HID_3083c = 0x3083c,
+	BNXT_ULP_CLASS_HID_3b53c = 0x3b53c,
+	BNXT_ULP_CLASS_HID_240a8 = 0x240a8,
+	BNXT_ULP_CLASS_HID_2cda8 = 0x2cda8,
+	BNXT_ULP_CLASS_HID_31b5c = 0x31b5c,
+	BNXT_ULP_CLASS_HID_3845c = 0x3845c,
+	BNXT_ULP_CLASS_HID_22ff8 = 0x22ff8,
+	BNXT_ULP_CLASS_HID_2d8f8 = 0x2d8f8,
+	BNXT_ULP_CLASS_HID_345f8 = 0x345f8,
+	BNXT_ULP_CLASS_HID_393ac = 0x393ac,
+	BNXT_ULP_CLASS_HID_228ac = 0x228ac,
+	BNXT_ULP_CLASS_HID_2d5ac = 0x2d5ac,
+	BNXT_ULP_CLASS_HID_35eac = 0x35eac,
+	BNXT_ULP_CLASS_HID_3cbac = 0x3cbac,
+	BNXT_ULP_CLASS_HID_25d5c = 0x25d5c,
+	BNXT_ULP_CLASS_HID_2c65c = 0x2c65c,
+	BNXT_ULP_CLASS_HID_31410 = 0x31410,
+	BNXT_ULP_CLASS_HID_38110 = 0x38110,
+	BNXT_ULP_CLASS_HID_209f0 = 0x209f0,
+	BNXT_ULP_CLASS_HID_2b2f0 = 0x2b2f0,
+	BNXT_ULP_CLASS_HID_33ff0 = 0x33ff0,
+	BNXT_ULP_CLASS_HID_3a8f0 = 0x3a8f0,
+	BNXT_ULP_CLASS_HID_214c0 = 0x214c0,
+	BNXT_ULP_CLASS_HID_281c0 = 0x281c0,
+	BNXT_ULP_CLASS_HID_30ac0 = 0x30ac0,
+	BNXT_ULP_CLASS_HID_3b7c0 = 0x3b7c0,
+	BNXT_ULP_CLASS_HID_211f4 = 0x211f4,
+	BNXT_ULP_CLASS_HID_29af4 = 0x29af4,
+	BNXT_ULP_CLASS_HID_307f4 = 0x307f4,
+	BNXT_ULP_CLASS_HID_3b0f4 = 0x3b0f4,
+	BNXT_ULP_CLASS_HID_202a4 = 0x202a4,
+	BNXT_ULP_CLASS_HID_28fa4 = 0x28fa4,
+	BNXT_ULP_CLASS_HID_338a4 = 0x338a4,
+	BNXT_ULP_CLASS_HID_3a5a4 = 0x3a5a4,
+	BNXT_ULP_CLASS_HID_22a04 = 0x22a04,
+	BNXT_ULP_CLASS_HID_2d704 = 0x2d704,
+	BNXT_ULP_CLASS_HID_34004 = 0x34004,
+	BNXT_ULP_CLASS_HID_3cd04 = 0x3cd04,
+	BNXT_ULP_CLASS_HID_23954 = 0x23954,
+	BNXT_ULP_CLASS_HID_2a254 = 0x2a254,
+	BNXT_ULP_CLASS_HID_32f54 = 0x32f54,
+	BNXT_ULP_CLASS_HID_3d854 = 0x3d854,
+	BNXT_ULP_CLASS_HID_23208 = 0x23208,
+	BNXT_ULP_CLASS_HID_2bf08 = 0x2bf08,
+	BNXT_ULP_CLASS_HID_32808 = 0x32808,
+	BNXT_ULP_CLASS_HID_3d508 = 0x3d508,
+	BNXT_ULP_CLASS_HID_22738 = 0x22738,
+	BNXT_ULP_CLASS_HID_2d038 = 0x2d038,
+	BNXT_ULP_CLASS_HID_35d38 = 0x35d38,
+	BNXT_ULP_CLASS_HID_3c638 = 0x3c638,
+	BNXT_ULP_CLASS_HID_2134c = 0x2134c,
+	BNXT_ULP_CLASS_HID_29c4c = 0x29c4c,
+	BNXT_ULP_CLASS_HID_3094c = 0x3094c,
+	BNXT_ULP_CLASS_HID_3b24c = 0x3b24c,
+	BNXT_ULP_CLASS_HID_25de8 = 0x25de8,
+	BNXT_ULP_CLASS_HID_2c6e8 = 0x2c6e8,
+	BNXT_ULP_CLASS_HID_3149c = 0x3149c,
+	BNXT_ULP_CLASS_HID_3819c = 0x3819c,
+	BNXT_ULP_CLASS_HID_2569c = 0x2569c,
+	BNXT_ULP_CLASS_HID_2c39c = 0x2c39c,
+	BNXT_ULP_CLASS_HID_31150 = 0x31150,
+	BNXT_ULP_CLASS_HID_39a50 = 0x39a50,
+	BNXT_ULP_CLASS_HID_24b4c = 0x24b4c,
+	BNXT_ULP_CLASS_HID_29900 = 0x29900,
+	BNXT_ULP_CLASS_HID_30200 = 0x30200,
+	BNXT_ULP_CLASS_HID_38f00 = 0x38f00,
+	BNXT_ULP_CLASS_HID_22f74 = 0x22f74,
+	BNXT_ULP_CLASS_HID_2d874 = 0x2d874,
+	BNXT_ULP_CLASS_HID_34574 = 0x34574,
+	BNXT_ULP_CLASS_HID_39328 = 0x39328,
+	BNXT_ULP_CLASS_HID_23a44 = 0x23a44,
+	BNXT_ULP_CLASS_HID_2a744 = 0x2a744,
+	BNXT_ULP_CLASS_HID_35044 = 0x35044,
+	BNXT_ULP_CLASS_HID_3dd44 = 0x3dd44,
+	BNXT_ULP_CLASS_HID_23778 = 0x23778,
+	BNXT_ULP_CLASS_HID_2a078 = 0x2a078,
+	BNXT_ULP_CLASS_HID_32d78 = 0x32d78,
+	BNXT_ULP_CLASS_HID_3d678 = 0x3d678,
+	BNXT_ULP_CLASS_HID_22828 = 0x22828,
+	BNXT_ULP_CLASS_HID_2d528 = 0x2d528,
+	BNXT_ULP_CLASS_HID_35e28 = 0x35e28,
+	BNXT_ULP_CLASS_HID_3cb28 = 0x3cb28,
+	BNXT_ULP_CLASS_HID_214bc = 0x214bc,
+	BNXT_ULP_CLASS_HID_281bc = 0x281bc,
+	BNXT_ULP_CLASS_HID_30abc = 0x30abc,
+	BNXT_ULP_CLASS_HID_3b7bc = 0x3b7bc,
+	BNXT_ULP_CLASS_HID_25ed8 = 0x25ed8,
+	BNXT_ULP_CLASS_HID_2cbd8 = 0x2cbd8,
+	BNXT_ULP_CLASS_HID_3198c = 0x3198c,
+	BNXT_ULP_CLASS_HID_3828c = 0x3828c,
+	BNXT_ULP_CLASS_HID_25b8c = 0x25b8c,
+	BNXT_ULP_CLASS_HID_2c48c = 0x2c48c,
+	BNXT_ULP_CLASS_HID_31240 = 0x31240,
+	BNXT_ULP_CLASS_HID_39f40 = 0x39f40,
+	BNXT_ULP_CLASS_HID_21170 = 0x21170,
+	BNXT_ULP_CLASS_HID_29a70 = 0x29a70,
+	BNXT_ULP_CLASS_HID_30770 = 0x30770,
+	BNXT_ULP_CLASS_HID_3b070 = 0x3b070,
+	BNXT_ULP_CLASS_HID_238d0 = 0x238d0,
+	BNXT_ULP_CLASS_HID_2a5d0 = 0x2a5d0,
+	BNXT_ULP_CLASS_HID_32ed0 = 0x32ed0,
+	BNXT_ULP_CLASS_HID_3dbd0 = 0x3dbd0,
+	BNXT_ULP_CLASS_HID_20420 = 0x20420,
+	BNXT_ULP_CLASS_HID_2b120 = 0x2b120,
+	BNXT_ULP_CLASS_HID_33a20 = 0x33a20,
+	BNXT_ULP_CLASS_HID_3a720 = 0x3a720,
+	BNXT_ULP_CLASS_HID_200d4 = 0x200d4,
+	BNXT_ULP_CLASS_HID_28dd4 = 0x28dd4,
+	BNXT_ULP_CLASS_HID_336d4 = 0x336d4,
+	BNXT_ULP_CLASS_HID_3a3d4 = 0x3a3d4,
+	BNXT_ULP_CLASS_HID_23584 = 0x23584,
+	BNXT_ULP_CLASS_HID_2be84 = 0x2be84,
+	BNXT_ULP_CLASS_HID_32b84 = 0x32b84,
+	BNXT_ULP_CLASS_HID_3d484 = 0x3d484,
+	BNXT_ULP_CLASS_HID_25d64 = 0x25d64,
+	BNXT_ULP_CLASS_HID_2c664 = 0x2c664,
+	BNXT_ULP_CLASS_HID_31418 = 0x31418,
+	BNXT_ULP_CLASS_HID_38118 = 0x38118,
+	BNXT_ULP_CLASS_HID_228b4 = 0x228b4,
+	BNXT_ULP_CLASS_HID_2d5b4 = 0x2d5b4,
+	BNXT_ULP_CLASS_HID_35eb4 = 0x35eb4,
+	BNXT_ULP_CLASS_HID_3cbb4 = 0x3cbb4,
+	BNXT_ULP_CLASS_HID_22568 = 0x22568,
+	BNXT_ULP_CLASS_HID_2ae68 = 0x2ae68,
+	BNXT_ULP_CLASS_HID_35b68 = 0x35b68,
+	BNXT_ULP_CLASS_HID_3c468 = 0x3c468,
+	BNXT_ULP_CLASS_HID_25618 = 0x25618,
+	BNXT_ULP_CLASS_HID_2c318 = 0x2c318,
+	BNXT_ULP_CLASS_HID_310cc = 0x310cc,
+	BNXT_ULP_CLASS_HID_39dcc = 0x39dcc,
+	BNXT_ULP_CLASS_HID_229b8 = 0x229b8,
+	BNXT_ULP_CLASS_HID_2d2b8 = 0x2d2b8,
+	BNXT_ULP_CLASS_HID_35fb8 = 0x35fb8,
+	BNXT_ULP_CLASS_HID_3c8b8 = 0x3c8b8,
+	BNXT_ULP_CLASS_HID_23488 = 0x23488,
+	BNXT_ULP_CLASS_HID_2a188 = 0x2a188,
+	BNXT_ULP_CLASS_HID_32a88 = 0x32a88,
+	BNXT_ULP_CLASS_HID_3d788 = 0x3d788,
+	BNXT_ULP_CLASS_HID_231bc = 0x231bc,
+	BNXT_ULP_CLASS_HID_2babc = 0x2babc,
+	BNXT_ULP_CLASS_HID_327bc = 0x327bc,
+	BNXT_ULP_CLASS_HID_3d0bc = 0x3d0bc,
+	BNXT_ULP_CLASS_HID_2226c = 0x2226c,
+	BNXT_ULP_CLASS_HID_2af6c = 0x2af6c,
+	BNXT_ULP_CLASS_HID_3586c = 0x3586c,
+	BNXT_ULP_CLASS_HID_3c56c = 0x3c56c,
+	BNXT_ULP_CLASS_HID_24dcc = 0x24dcc,
+	BNXT_ULP_CLASS_HID_29b80 = 0x29b80,
+	BNXT_ULP_CLASS_HID_30480 = 0x30480,
+	BNXT_ULP_CLASS_HID_3b180 = 0x3b180,
+	BNXT_ULP_CLASS_HID_2591c = 0x2591c,
+	BNXT_ULP_CLASS_HID_2c21c = 0x2c21c,
+	BNXT_ULP_CLASS_HID_313d0 = 0x313d0,
+	BNXT_ULP_CLASS_HID_39cd0 = 0x39cd0,
+	BNXT_ULP_CLASS_HID_255d0 = 0x255d0,
+	BNXT_ULP_CLASS_HID_2ded0 = 0x2ded0,
+	BNXT_ULP_CLASS_HID_34bd0 = 0x34bd0,
+	BNXT_ULP_CLASS_HID_39984 = 0x39984,
+	BNXT_ULP_CLASS_HID_24680 = 0x24680,
+	BNXT_ULP_CLASS_HID_294b4 = 0x294b4,
+	BNXT_ULP_CLASS_HID_301b4 = 0x301b4,
+	BNXT_ULP_CLASS_HID_38ab4 = 0x38ab4,
+	BNXT_ULP_CLASS_HID_23314 = 0x23314,
+	BNXT_ULP_CLASS_HID_2bc14 = 0x2bc14,
+	BNXT_ULP_CLASS_HID_32914 = 0x32914,
+	BNXT_ULP_CLASS_HID_3d214 = 0x3d214,
+	BNXT_ULP_CLASS_HID_21e64 = 0x21e64,
+	BNXT_ULP_CLASS_HID_28b64 = 0x28b64,
+	BNXT_ULP_CLASS_HID_33464 = 0x33464,
+	BNXT_ULP_CLASS_HID_3a164 = 0x3a164,
+	BNXT_ULP_CLASS_HID_21b18 = 0x21b18,
+	BNXT_ULP_CLASS_HID_28418 = 0x28418,
+	BNXT_ULP_CLASS_HID_33118 = 0x33118,
+	BNXT_ULP_CLASS_HID_3ba18 = 0x3ba18,
+	BNXT_ULP_CLASS_HID_20fc8 = 0x20fc8,
+	BNXT_ULP_CLASS_HID_2b8c8 = 0x2b8c8,
+	BNXT_ULP_CLASS_HID_325c8 = 0x325c8,
+	BNXT_ULP_CLASS_HID_3aec8 = 0x3aec8,
+	BNXT_ULP_CLASS_HID_257a8 = 0x257a8,
+	BNXT_ULP_CLASS_HID_2c0a8 = 0x2c0a8,
+	BNXT_ULP_CLASS_HID_34da8 = 0x34da8,
+	BNXT_ULP_CLASS_HID_39b5c = 0x39b5c,
+	BNXT_ULP_CLASS_HID_222f8 = 0x222f8,
+	BNXT_ULP_CLASS_HID_2aff8 = 0x2aff8,
+	BNXT_ULP_CLASS_HID_358f8 = 0x358f8,
+	BNXT_ULP_CLASS_HID_3c5f8 = 0x3c5f8,
+	BNXT_ULP_CLASS_HID_23fac = 0x23fac,
+	BNXT_ULP_CLASS_HID_2a8ac = 0x2a8ac,
+	BNXT_ULP_CLASS_HID_355ac = 0x355ac,
+	BNXT_ULP_CLASS_HID_3deac = 0x3deac,
+	BNXT_ULP_CLASS_HID_2505c = 0x2505c,
+	BNXT_ULP_CLASS_HID_2dd5c = 0x2dd5c,
+	BNXT_ULP_CLASS_HID_3465c = 0x3465c,
+	BNXT_ULP_CLASS_HID_39410 = 0x39410,
+	BNXT_ULP_CLASS_HID_223fc = 0x223fc,
+	BNXT_ULP_CLASS_HID_2acfc = 0x2acfc,
+	BNXT_ULP_CLASS_HID_359fc = 0x359fc,
+	BNXT_ULP_CLASS_HID_3c2fc = 0x3c2fc,
+	BNXT_ULP_CLASS_HID_20ecc = 0x20ecc,
+	BNXT_ULP_CLASS_HID_2bbcc = 0x2bbcc,
+	BNXT_ULP_CLASS_HID_324cc = 0x324cc,
+	BNXT_ULP_CLASS_HID_3d1cc = 0x3d1cc,
+	BNXT_ULP_CLASS_HID_20b80 = 0x20b80,
+	BNXT_ULP_CLASS_HID_2b480 = 0x2b480,
+	BNXT_ULP_CLASS_HID_32180 = 0x32180,
+	BNXT_ULP_CLASS_HID_3aa80 = 0x3aa80,
+	BNXT_ULP_CLASS_HID_23cb0 = 0x23cb0,
+	BNXT_ULP_CLASS_HID_2a9b0 = 0x2a9b0,
+	BNXT_ULP_CLASS_HID_352b0 = 0x352b0,
+	BNXT_ULP_CLASS_HID_3dfb0 = 0x3dfb0,
+	BNXT_ULP_CLASS_HID_24410 = 0x24410,
+	BNXT_ULP_CLASS_HID_295c4 = 0x295c4,
+	BNXT_ULP_CLASS_HID_31ec4 = 0x31ec4,
+	BNXT_ULP_CLASS_HID_38bc4 = 0x38bc4,
+	BNXT_ULP_CLASS_HID_25360 = 0x25360,
+	BNXT_ULP_CLASS_HID_2dc60 = 0x2dc60,
+	BNXT_ULP_CLASS_HID_34960 = 0x34960,
+	BNXT_ULP_CLASS_HID_39714 = 0x39714,
+	BNXT_ULP_CLASS_HID_22c14 = 0x22c14,
+	BNXT_ULP_CLASS_HID_2d914 = 0x2d914,
+	BNXT_ULP_CLASS_HID_34214 = 0x34214,
+	BNXT_ULP_CLASS_HID_393c8 = 0x393c8,
+	BNXT_ULP_CLASS_HID_240c4 = 0x240c4,
+	BNXT_ULP_CLASS_HID_2cdc4 = 0x2cdc4,
+	BNXT_ULP_CLASS_HID_31bf8 = 0x31bf8,
+	BNXT_ULP_CLASS_HID_384f8 = 0x384f8,
+	BNXT_ULP_CLASS_HID_23dc0 = 0x23dc0,
+	BNXT_ULP_CLASS_HID_2a6c0 = 0x2a6c0,
+	BNXT_ULP_CLASS_HID_353c0 = 0x353c0,
+	BNXT_ULP_CLASS_HID_3dcc0 = 0x3dcc0,
+	BNXT_ULP_CLASS_HID_20910 = 0x20910,
+	BNXT_ULP_CLASS_HID_2b210 = 0x2b210,
+	BNXT_ULP_CLASS_HID_33f10 = 0x33f10,
+	BNXT_ULP_CLASS_HID_3a810 = 0x3a810,
+	BNXT_ULP_CLASS_HID_205c4 = 0x205c4,
+	BNXT_ULP_CLASS_HID_28ec4 = 0x28ec4,
+	BNXT_ULP_CLASS_HID_33bc4 = 0x33bc4,
+	BNXT_ULP_CLASS_HID_3a4c4 = 0x3a4c4,
+	BNXT_ULP_CLASS_HID_236f4 = 0x236f4,
+	BNXT_ULP_CLASS_HID_2a3f4 = 0x2a3f4,
+	BNXT_ULP_CLASS_HID_32cf4 = 0x32cf4,
+	BNXT_ULP_CLASS_HID_3d9f4 = 0x3d9f4,
+	BNXT_ULP_CLASS_HID_25e54 = 0x25e54,
+	BNXT_ULP_CLASS_HID_2cb54 = 0x2cb54,
+	BNXT_ULP_CLASS_HID_31908 = 0x31908,
+	BNXT_ULP_CLASS_HID_38208 = 0x38208,
+	BNXT_ULP_CLASS_HID_22da4 = 0x22da4,
+	BNXT_ULP_CLASS_HID_2d6a4 = 0x2d6a4,
+	BNXT_ULP_CLASS_HID_343a4 = 0x343a4,
+	BNXT_ULP_CLASS_HID_39158 = 0x39158,
+	BNXT_ULP_CLASS_HID_22658 = 0x22658,
+	BNXT_ULP_CLASS_HID_2d358 = 0x2d358,
+	BNXT_ULP_CLASS_HID_35c58 = 0x35c58,
+	BNXT_ULP_CLASS_HID_3c958 = 0x3c958,
+	BNXT_ULP_CLASS_HID_25b08 = 0x25b08,
+	BNXT_ULP_CLASS_HID_2c408 = 0x2c408,
+	BNXT_ULP_CLASS_HID_3123c = 0x3123c,
+	BNXT_ULP_CLASS_HID_39f3c = 0x39f3c,
+	BNXT_ULP_CLASS_HID_34a8 = 0x34a8,
+	BNXT_ULP_CLASS_HID_3a64 = 0x3a64,
+	BNXT_ULP_CLASS_HID_5ef8 = 0x5ef8,
+	BNXT_ULP_CLASS_HID_07c0 = 0x07c0,
+	BNXT_ULP_CLASS_HID_2854 = 0x2854,
+	BNXT_ULP_CLASS_HID_593c = 0x593c,
+	BNXT_ULP_CLASS_HID_1e04 = 0x1e04,
+	BNXT_ULP_CLASS_HID_2298 = 0x2298,
+	BNXT_ULP_CLASS_HID_24644 = 0x24644,
+	BNXT_ULP_CLASS_HID_29438 = 0x29438,
+	BNXT_ULP_CLASS_HID_30138 = 0x30138,
+	BNXT_ULP_CLASS_HID_38a38 = 0x38a38,
+	BNXT_ULP_CLASS_HID_25594 = 0x25594,
+	BNXT_ULP_CLASS_HID_2de94 = 0x2de94,
+	BNXT_ULP_CLASS_HID_34b94 = 0x34b94,
+	BNXT_ULP_CLASS_HID_39948 = 0x39948,
+	BNXT_ULP_CLASS_HID_22e48 = 0x22e48,
+	BNXT_ULP_CLASS_HID_2db48 = 0x2db48,
+	BNXT_ULP_CLASS_HID_34448 = 0x34448,
+	BNXT_ULP_CLASS_HID_3923c = 0x3923c,
+	BNXT_ULP_CLASS_HID_24338 = 0x24338,
+	BNXT_ULP_CLASS_HID_290ec = 0x290ec,
+	BNXT_ULP_CLASS_HID_31dec = 0x31dec,
+	BNXT_ULP_CLASS_HID_386ec = 0x386ec,
+	BNXT_ULP_CLASS_HID_20f8c = 0x20f8c,
+	BNXT_ULP_CLASS_HID_2b88c = 0x2b88c,
+	BNXT_ULP_CLASS_HID_3258c = 0x3258c,
+	BNXT_ULP_CLASS_HID_3ae8c = 0x3ae8c,
+	BNXT_ULP_CLASS_HID_21adc = 0x21adc,
+	BNXT_ULP_CLASS_HID_287dc = 0x287dc,
+	BNXT_ULP_CLASS_HID_330dc = 0x330dc,
+	BNXT_ULP_CLASS_HID_3bddc = 0x3bddc,
+	BNXT_ULP_CLASS_HID_21790 = 0x21790,
+	BNXT_ULP_CLASS_HID_28090 = 0x28090,
+	BNXT_ULP_CLASS_HID_30d90 = 0x30d90,
+	BNXT_ULP_CLASS_HID_3b690 = 0x3b690,
+	BNXT_ULP_CLASS_HID_20840 = 0x20840,
+	BNXT_ULP_CLASS_HID_2b540 = 0x2b540,
+	BNXT_ULP_CLASS_HID_33e40 = 0x33e40,
+	BNXT_ULP_CLASS_HID_3ab40 = 0x3ab40,
+	BNXT_ULP_CLASS_HID_253e0 = 0x253e0,
+	BNXT_ULP_CLASS_HID_2dce0 = 0x2dce0,
+	BNXT_ULP_CLASS_HID_349e0 = 0x349e0,
+	BNXT_ULP_CLASS_HID_397d4 = 0x397d4,
+	BNXT_ULP_CLASS_HID_23f30 = 0x23f30,
+	BNXT_ULP_CLASS_HID_2a830 = 0x2a830,
+	BNXT_ULP_CLASS_HID_35530 = 0x35530,
+	BNXT_ULP_CLASS_HID_3de30 = 0x3de30,
+	BNXT_ULP_CLASS_HID_23be4 = 0x23be4,
+	BNXT_ULP_CLASS_HID_2a4e4 = 0x2a4e4,
+	BNXT_ULP_CLASS_HID_351e4 = 0x351e4,
+	BNXT_ULP_CLASS_HID_3dae4 = 0x3dae4,
+	BNXT_ULP_CLASS_HID_22cd4 = 0x22cd4,
+	BNXT_ULP_CLASS_HID_2d9d4 = 0x2d9d4,
+	BNXT_ULP_CLASS_HID_342d4 = 0x342d4,
+	BNXT_ULP_CLASS_HID_39088 = 0x39088,
+	BNXT_ULP_CLASS_HID_21928 = 0x21928,
+	BNXT_ULP_CLASS_HID_28228 = 0x28228,
+	BNXT_ULP_CLASS_HID_30f28 = 0x30f28,
+	BNXT_ULP_CLASS_HID_3b828 = 0x3b828,
+	BNXT_ULP_CLASS_HID_24384 = 0x24384,
+	BNXT_ULP_CLASS_HID_29178 = 0x29178,
+	BNXT_ULP_CLASS_HID_31a78 = 0x31a78,
+	BNXT_ULP_CLASS_HID_38778 = 0x38778,
+	BNXT_ULP_CLASS_HID_25c78 = 0x25c78,
+	BNXT_ULP_CLASS_HID_2c978 = 0x2c978,
+	BNXT_ULP_CLASS_HID_3172c = 0x3172c,
+	BNXT_ULP_CLASS_HID_3802c = 0x3802c,
+	BNXT_ULP_CLASS_HID_2121c = 0x2121c,
+	BNXT_ULP_CLASS_HID_29f1c = 0x29f1c,
+	BNXT_ULP_CLASS_HID_3081c = 0x3081c,
+	BNXT_ULP_CLASS_HID_3b51c = 0x3b51c,
+	BNXT_ULP_CLASS_HID_24088 = 0x24088,
+	BNXT_ULP_CLASS_HID_2cd88 = 0x2cd88,
+	BNXT_ULP_CLASS_HID_31b7c = 0x31b7c,
+	BNXT_ULP_CLASS_HID_3847c = 0x3847c,
+	BNXT_ULP_CLASS_HID_22fd8 = 0x22fd8,
+	BNXT_ULP_CLASS_HID_2d8d8 = 0x2d8d8,
+	BNXT_ULP_CLASS_HID_345d8 = 0x345d8,
+	BNXT_ULP_CLASS_HID_3938c = 0x3938c,
+	BNXT_ULP_CLASS_HID_2288c = 0x2288c,
+	BNXT_ULP_CLASS_HID_2d58c = 0x2d58c,
+	BNXT_ULP_CLASS_HID_35e8c = 0x35e8c,
+	BNXT_ULP_CLASS_HID_3cb8c = 0x3cb8c,
+	BNXT_ULP_CLASS_HID_25d7c = 0x25d7c,
+	BNXT_ULP_CLASS_HID_2c67c = 0x2c67c,
+	BNXT_ULP_CLASS_HID_31430 = 0x31430,
+	BNXT_ULP_CLASS_HID_38130 = 0x38130,
+	BNXT_ULP_CLASS_HID_209d0 = 0x209d0,
+	BNXT_ULP_CLASS_HID_2b2d0 = 0x2b2d0,
+	BNXT_ULP_CLASS_HID_33fd0 = 0x33fd0,
+	BNXT_ULP_CLASS_HID_3a8d0 = 0x3a8d0,
+	BNXT_ULP_CLASS_HID_214e0 = 0x214e0,
+	BNXT_ULP_CLASS_HID_281e0 = 0x281e0,
+	BNXT_ULP_CLASS_HID_30ae0 = 0x30ae0,
+	BNXT_ULP_CLASS_HID_3b7e0 = 0x3b7e0,
+	BNXT_ULP_CLASS_HID_211d4 = 0x211d4,
+	BNXT_ULP_CLASS_HID_29ad4 = 0x29ad4,
+	BNXT_ULP_CLASS_HID_307d4 = 0x307d4,
+	BNXT_ULP_CLASS_HID_3b0d4 = 0x3b0d4,
+	BNXT_ULP_CLASS_HID_20284 = 0x20284,
+	BNXT_ULP_CLASS_HID_28f84 = 0x28f84,
+	BNXT_ULP_CLASS_HID_33884 = 0x33884,
+	BNXT_ULP_CLASS_HID_3a584 = 0x3a584,
+	BNXT_ULP_CLASS_HID_22a24 = 0x22a24,
+	BNXT_ULP_CLASS_HID_2d724 = 0x2d724,
+	BNXT_ULP_CLASS_HID_34024 = 0x34024,
+	BNXT_ULP_CLASS_HID_3cd24 = 0x3cd24,
+	BNXT_ULP_CLASS_HID_23974 = 0x23974,
+	BNXT_ULP_CLASS_HID_2a274 = 0x2a274,
+	BNXT_ULP_CLASS_HID_32f74 = 0x32f74,
+	BNXT_ULP_CLASS_HID_3d874 = 0x3d874,
+	BNXT_ULP_CLASS_HID_23228 = 0x23228,
+	BNXT_ULP_CLASS_HID_2bf28 = 0x2bf28,
+	BNXT_ULP_CLASS_HID_32828 = 0x32828,
+	BNXT_ULP_CLASS_HID_3d528 = 0x3d528,
+	BNXT_ULP_CLASS_HID_22718 = 0x22718,
+	BNXT_ULP_CLASS_HID_2d018 = 0x2d018,
+	BNXT_ULP_CLASS_HID_35d18 = 0x35d18,
+	BNXT_ULP_CLASS_HID_3c618 = 0x3c618,
+	BNXT_ULP_CLASS_HID_2136c = 0x2136c,
+	BNXT_ULP_CLASS_HID_29c6c = 0x29c6c,
+	BNXT_ULP_CLASS_HID_3096c = 0x3096c,
+	BNXT_ULP_CLASS_HID_3b26c = 0x3b26c,
+	BNXT_ULP_CLASS_HID_25dc8 = 0x25dc8,
+	BNXT_ULP_CLASS_HID_2c6c8 = 0x2c6c8,
+	BNXT_ULP_CLASS_HID_314bc = 0x314bc,
+	BNXT_ULP_CLASS_HID_381bc = 0x381bc,
+	BNXT_ULP_CLASS_HID_256bc = 0x256bc,
+	BNXT_ULP_CLASS_HID_2c3bc = 0x2c3bc,
+	BNXT_ULP_CLASS_HID_31170 = 0x31170,
+	BNXT_ULP_CLASS_HID_39a70 = 0x39a70,
+	BNXT_ULP_CLASS_HID_24b6c = 0x24b6c,
+	BNXT_ULP_CLASS_HID_29920 = 0x29920,
+	BNXT_ULP_CLASS_HID_30220 = 0x30220,
+	BNXT_ULP_CLASS_HID_38f20 = 0x38f20,
+	BNXT_ULP_CLASS_HID_22f54 = 0x22f54,
+	BNXT_ULP_CLASS_HID_2d854 = 0x2d854,
+	BNXT_ULP_CLASS_HID_34554 = 0x34554,
+	BNXT_ULP_CLASS_HID_39308 = 0x39308,
+	BNXT_ULP_CLASS_HID_23a64 = 0x23a64,
+	BNXT_ULP_CLASS_HID_2a764 = 0x2a764,
+	BNXT_ULP_CLASS_HID_35064 = 0x35064,
+	BNXT_ULP_CLASS_HID_3dd64 = 0x3dd64,
+	BNXT_ULP_CLASS_HID_23758 = 0x23758,
+	BNXT_ULP_CLASS_HID_2a058 = 0x2a058,
+	BNXT_ULP_CLASS_HID_32d58 = 0x32d58,
+	BNXT_ULP_CLASS_HID_3d658 = 0x3d658,
+	BNXT_ULP_CLASS_HID_22808 = 0x22808,
+	BNXT_ULP_CLASS_HID_2d508 = 0x2d508,
+	BNXT_ULP_CLASS_HID_35e08 = 0x35e08,
+	BNXT_ULP_CLASS_HID_3cb08 = 0x3cb08,
+	BNXT_ULP_CLASS_HID_2149c = 0x2149c,
+	BNXT_ULP_CLASS_HID_2819c = 0x2819c,
+	BNXT_ULP_CLASS_HID_30a9c = 0x30a9c,
+	BNXT_ULP_CLASS_HID_3b79c = 0x3b79c,
+	BNXT_ULP_CLASS_HID_25ef8 = 0x25ef8,
+	BNXT_ULP_CLASS_HID_2cbf8 = 0x2cbf8,
+	BNXT_ULP_CLASS_HID_319ac = 0x319ac,
+	BNXT_ULP_CLASS_HID_382ac = 0x382ac,
+	BNXT_ULP_CLASS_HID_25bac = 0x25bac,
+	BNXT_ULP_CLASS_HID_2c4ac = 0x2c4ac,
+	BNXT_ULP_CLASS_HID_31260 = 0x31260,
+	BNXT_ULP_CLASS_HID_39f60 = 0x39f60,
+	BNXT_ULP_CLASS_HID_21150 = 0x21150,
+	BNXT_ULP_CLASS_HID_29a50 = 0x29a50,
+	BNXT_ULP_CLASS_HID_30750 = 0x30750,
+	BNXT_ULP_CLASS_HID_3b050 = 0x3b050,
+	BNXT_ULP_CLASS_HID_238f0 = 0x238f0,
+	BNXT_ULP_CLASS_HID_2a5f0 = 0x2a5f0,
+	BNXT_ULP_CLASS_HID_32ef0 = 0x32ef0,
+	BNXT_ULP_CLASS_HID_3dbf0 = 0x3dbf0,
+	BNXT_ULP_CLASS_HID_20400 = 0x20400,
+	BNXT_ULP_CLASS_HID_2b100 = 0x2b100,
+	BNXT_ULP_CLASS_HID_33a00 = 0x33a00,
+	BNXT_ULP_CLASS_HID_3a700 = 0x3a700,
+	BNXT_ULP_CLASS_HID_200f4 = 0x200f4,
+	BNXT_ULP_CLASS_HID_28df4 = 0x28df4,
+	BNXT_ULP_CLASS_HID_336f4 = 0x336f4,
+	BNXT_ULP_CLASS_HID_3a3f4 = 0x3a3f4,
+	BNXT_ULP_CLASS_HID_235a4 = 0x235a4,
+	BNXT_ULP_CLASS_HID_2bea4 = 0x2bea4,
+	BNXT_ULP_CLASS_HID_32ba4 = 0x32ba4,
+	BNXT_ULP_CLASS_HID_3d4a4 = 0x3d4a4,
+	BNXT_ULP_CLASS_HID_25d44 = 0x25d44,
+	BNXT_ULP_CLASS_HID_2c644 = 0x2c644,
+	BNXT_ULP_CLASS_HID_31438 = 0x31438,
+	BNXT_ULP_CLASS_HID_38138 = 0x38138,
+	BNXT_ULP_CLASS_HID_22894 = 0x22894,
+	BNXT_ULP_CLASS_HID_2d594 = 0x2d594,
+	BNXT_ULP_CLASS_HID_35e94 = 0x35e94,
+	BNXT_ULP_CLASS_HID_3cb94 = 0x3cb94,
+	BNXT_ULP_CLASS_HID_22548 = 0x22548,
+	BNXT_ULP_CLASS_HID_2ae48 = 0x2ae48,
+	BNXT_ULP_CLASS_HID_35b48 = 0x35b48,
+	BNXT_ULP_CLASS_HID_3c448 = 0x3c448,
+	BNXT_ULP_CLASS_HID_25638 = 0x25638,
+	BNXT_ULP_CLASS_HID_2c338 = 0x2c338,
+	BNXT_ULP_CLASS_HID_310ec = 0x310ec,
+	BNXT_ULP_CLASS_HID_39dec = 0x39dec,
+	BNXT_ULP_CLASS_HID_22998 = 0x22998,
+	BNXT_ULP_CLASS_HID_2d298 = 0x2d298,
+	BNXT_ULP_CLASS_HID_35f98 = 0x35f98,
+	BNXT_ULP_CLASS_HID_3c898 = 0x3c898,
+	BNXT_ULP_CLASS_HID_234a8 = 0x234a8,
+	BNXT_ULP_CLASS_HID_2a1a8 = 0x2a1a8,
+	BNXT_ULP_CLASS_HID_32aa8 = 0x32aa8,
+	BNXT_ULP_CLASS_HID_3d7a8 = 0x3d7a8,
+	BNXT_ULP_CLASS_HID_2319c = 0x2319c,
+	BNXT_ULP_CLASS_HID_2ba9c = 0x2ba9c,
+	BNXT_ULP_CLASS_HID_3279c = 0x3279c,
+	BNXT_ULP_CLASS_HID_3d09c = 0x3d09c,
+	BNXT_ULP_CLASS_HID_2224c = 0x2224c,
+	BNXT_ULP_CLASS_HID_2af4c = 0x2af4c,
+	BNXT_ULP_CLASS_HID_3584c = 0x3584c,
+	BNXT_ULP_CLASS_HID_3c54c = 0x3c54c,
+	BNXT_ULP_CLASS_HID_24dec = 0x24dec,
+	BNXT_ULP_CLASS_HID_29ba0 = 0x29ba0,
+	BNXT_ULP_CLASS_HID_304a0 = 0x304a0,
+	BNXT_ULP_CLASS_HID_3b1a0 = 0x3b1a0,
+	BNXT_ULP_CLASS_HID_2593c = 0x2593c,
+	BNXT_ULP_CLASS_HID_2c23c = 0x2c23c,
+	BNXT_ULP_CLASS_HID_313f0 = 0x313f0,
+	BNXT_ULP_CLASS_HID_39cf0 = 0x39cf0,
+	BNXT_ULP_CLASS_HID_255f0 = 0x255f0,
+	BNXT_ULP_CLASS_HID_2def0 = 0x2def0,
+	BNXT_ULP_CLASS_HID_34bf0 = 0x34bf0,
+	BNXT_ULP_CLASS_HID_399a4 = 0x399a4,
+	BNXT_ULP_CLASS_HID_246a0 = 0x246a0,
+	BNXT_ULP_CLASS_HID_29494 = 0x29494,
+	BNXT_ULP_CLASS_HID_30194 = 0x30194,
+	BNXT_ULP_CLASS_HID_38a94 = 0x38a94,
+	BNXT_ULP_CLASS_HID_23334 = 0x23334,
+	BNXT_ULP_CLASS_HID_2bc34 = 0x2bc34,
+	BNXT_ULP_CLASS_HID_32934 = 0x32934,
+	BNXT_ULP_CLASS_HID_3d234 = 0x3d234,
+	BNXT_ULP_CLASS_HID_21e44 = 0x21e44,
+	BNXT_ULP_CLASS_HID_28b44 = 0x28b44,
+	BNXT_ULP_CLASS_HID_33444 = 0x33444,
+	BNXT_ULP_CLASS_HID_3a144 = 0x3a144,
+	BNXT_ULP_CLASS_HID_21b38 = 0x21b38,
+	BNXT_ULP_CLASS_HID_28438 = 0x28438,
+	BNXT_ULP_CLASS_HID_33138 = 0x33138,
+	BNXT_ULP_CLASS_HID_3ba38 = 0x3ba38,
+	BNXT_ULP_CLASS_HID_20fe8 = 0x20fe8,
+	BNXT_ULP_CLASS_HID_2b8e8 = 0x2b8e8,
+	BNXT_ULP_CLASS_HID_325e8 = 0x325e8,
+	BNXT_ULP_CLASS_HID_3aee8 = 0x3aee8,
+	BNXT_ULP_CLASS_HID_25788 = 0x25788,
+	BNXT_ULP_CLASS_HID_2c088 = 0x2c088,
+	BNXT_ULP_CLASS_HID_34d88 = 0x34d88,
+	BNXT_ULP_CLASS_HID_39b7c = 0x39b7c,
+	BNXT_ULP_CLASS_HID_222d8 = 0x222d8,
+	BNXT_ULP_CLASS_HID_2afd8 = 0x2afd8,
+	BNXT_ULP_CLASS_HID_358d8 = 0x358d8,
+	BNXT_ULP_CLASS_HID_3c5d8 = 0x3c5d8,
+	BNXT_ULP_CLASS_HID_23f8c = 0x23f8c,
+	BNXT_ULP_CLASS_HID_2a88c = 0x2a88c,
+	BNXT_ULP_CLASS_HID_3558c = 0x3558c,
+	BNXT_ULP_CLASS_HID_3de8c = 0x3de8c,
+	BNXT_ULP_CLASS_HID_2507c = 0x2507c,
+	BNXT_ULP_CLASS_HID_2dd7c = 0x2dd7c,
+	BNXT_ULP_CLASS_HID_3467c = 0x3467c,
+	BNXT_ULP_CLASS_HID_39430 = 0x39430,
+	BNXT_ULP_CLASS_HID_223dc = 0x223dc,
+	BNXT_ULP_CLASS_HID_2acdc = 0x2acdc,
+	BNXT_ULP_CLASS_HID_359dc = 0x359dc,
+	BNXT_ULP_CLASS_HID_3c2dc = 0x3c2dc,
+	BNXT_ULP_CLASS_HID_20eec = 0x20eec,
+	BNXT_ULP_CLASS_HID_2bbec = 0x2bbec,
+	BNXT_ULP_CLASS_HID_324ec = 0x324ec,
+	BNXT_ULP_CLASS_HID_3d1ec = 0x3d1ec,
+	BNXT_ULP_CLASS_HID_20ba0 = 0x20ba0,
+	BNXT_ULP_CLASS_HID_2b4a0 = 0x2b4a0,
+	BNXT_ULP_CLASS_HID_321a0 = 0x321a0,
+	BNXT_ULP_CLASS_HID_3aaa0 = 0x3aaa0,
+	BNXT_ULP_CLASS_HID_23c90 = 0x23c90,
+	BNXT_ULP_CLASS_HID_2a990 = 0x2a990,
+	BNXT_ULP_CLASS_HID_35290 = 0x35290,
+	BNXT_ULP_CLASS_HID_3df90 = 0x3df90,
+	BNXT_ULP_CLASS_HID_24430 = 0x24430,
+	BNXT_ULP_CLASS_HID_295e4 = 0x295e4,
+	BNXT_ULP_CLASS_HID_31ee4 = 0x31ee4,
+	BNXT_ULP_CLASS_HID_38be4 = 0x38be4,
+	BNXT_ULP_CLASS_HID_25340 = 0x25340,
+	BNXT_ULP_CLASS_HID_2dc40 = 0x2dc40,
+	BNXT_ULP_CLASS_HID_34940 = 0x34940,
+	BNXT_ULP_CLASS_HID_39734 = 0x39734,
+	BNXT_ULP_CLASS_HID_22c34 = 0x22c34,
+	BNXT_ULP_CLASS_HID_2d934 = 0x2d934,
+	BNXT_ULP_CLASS_HID_34234 = 0x34234,
+	BNXT_ULP_CLASS_HID_393e8 = 0x393e8,
+	BNXT_ULP_CLASS_HID_240e4 = 0x240e4,
+	BNXT_ULP_CLASS_HID_2cde4 = 0x2cde4,
+	BNXT_ULP_CLASS_HID_31bd8 = 0x31bd8,
+	BNXT_ULP_CLASS_HID_384d8 = 0x384d8,
+	BNXT_ULP_CLASS_HID_23de0 = 0x23de0,
+	BNXT_ULP_CLASS_HID_2a6e0 = 0x2a6e0,
+	BNXT_ULP_CLASS_HID_353e0 = 0x353e0,
+	BNXT_ULP_CLASS_HID_3dce0 = 0x3dce0,
+	BNXT_ULP_CLASS_HID_20930 = 0x20930,
+	BNXT_ULP_CLASS_HID_2b230 = 0x2b230,
+	BNXT_ULP_CLASS_HID_33f30 = 0x33f30,
+	BNXT_ULP_CLASS_HID_3a830 = 0x3a830,
+	BNXT_ULP_CLASS_HID_205e4 = 0x205e4,
+	BNXT_ULP_CLASS_HID_28ee4 = 0x28ee4,
+	BNXT_ULP_CLASS_HID_33be4 = 0x33be4,
+	BNXT_ULP_CLASS_HID_3a4e4 = 0x3a4e4,
+	BNXT_ULP_CLASS_HID_236d4 = 0x236d4,
+	BNXT_ULP_CLASS_HID_2a3d4 = 0x2a3d4,
+	BNXT_ULP_CLASS_HID_32cd4 = 0x32cd4,
+	BNXT_ULP_CLASS_HID_3d9d4 = 0x3d9d4,
+	BNXT_ULP_CLASS_HID_25e74 = 0x25e74,
+	BNXT_ULP_CLASS_HID_2cb74 = 0x2cb74,
+	BNXT_ULP_CLASS_HID_31928 = 0x31928,
+	BNXT_ULP_CLASS_HID_38228 = 0x38228,
+	BNXT_ULP_CLASS_HID_22d84 = 0x22d84,
+	BNXT_ULP_CLASS_HID_2d684 = 0x2d684,
+	BNXT_ULP_CLASS_HID_34384 = 0x34384,
+	BNXT_ULP_CLASS_HID_39178 = 0x39178,
+	BNXT_ULP_CLASS_HID_22678 = 0x22678,
+	BNXT_ULP_CLASS_HID_2d378 = 0x2d378,
+	BNXT_ULP_CLASS_HID_35c78 = 0x35c78,
+	BNXT_ULP_CLASS_HID_3c978 = 0x3c978,
+	BNXT_ULP_CLASS_HID_25b28 = 0x25b28,
+	BNXT_ULP_CLASS_HID_2c428 = 0x2c428,
+	BNXT_ULP_CLASS_HID_3121c = 0x3121c,
+	BNXT_ULP_CLASS_HID_39f1c = 0x39f1c,
+	BNXT_ULP_CLASS_HID_3488 = 0x3488,
+	BNXT_ULP_CLASS_HID_3a44 = 0x3a44,
+	BNXT_ULP_CLASS_HID_5ed8 = 0x5ed8,
+	BNXT_ULP_CLASS_HID_07e0 = 0x07e0,
+	BNXT_ULP_CLASS_HID_2874 = 0x2874,
+	BNXT_ULP_CLASS_HID_591c = 0x591c,
+	BNXT_ULP_CLASS_HID_1e24 = 0x1e24,
+	BNXT_ULP_CLASS_HID_22b8 = 0x22b8
 };
 
 enum bnxt_ulp_act_hid {
 	BNXT_ULP_ACT_HID_0000 = 0x0000,
 	BNXT_ULP_ACT_HID_0001 = 0x0001,
 	BNXT_ULP_ACT_HID_0400 = 0x0400,
-	BNXT_ULP_ACT_HID_0325 = 0x0325,
+	BNXT_ULP_ACT_HID_01ab = 0x01ab,
 	BNXT_ULP_ACT_HID_0010 = 0x0010,
-	BNXT_ULP_ACT_HID_0725 = 0x0725,
-	BNXT_ULP_ACT_HID_0335 = 0x0335,
+	BNXT_ULP_ACT_HID_05ab = 0x05ab,
+	BNXT_ULP_ACT_HID_01bb = 0x01bb,
 	BNXT_ULP_ACT_HID_0002 = 0x0002,
 	BNXT_ULP_ACT_HID_0003 = 0x0003,
 	BNXT_ULP_ACT_HID_0402 = 0x0402,
-	BNXT_ULP_ACT_HID_0327 = 0x0327,
+	BNXT_ULP_ACT_HID_01ad = 0x01ad,
 	BNXT_ULP_ACT_HID_0012 = 0x0012,
-	BNXT_ULP_ACT_HID_0727 = 0x0727,
-	BNXT_ULP_ACT_HID_0337 = 0x0337,
-	BNXT_ULP_ACT_HID_01de = 0x01de,
-	BNXT_ULP_ACT_HID_00c6 = 0x00c6,
-	BNXT_ULP_ACT_HID_0506 = 0x0506,
-	BNXT_ULP_ACT_HID_01ed = 0x01ed,
-	BNXT_ULP_ACT_HID_03ef = 0x03ef,
-	BNXT_ULP_ACT_HID_0516 = 0x0516,
-	BNXT_ULP_ACT_HID_01df = 0x01df,
-	BNXT_ULP_ACT_HID_01e4 = 0x01e4,
-	BNXT_ULP_ACT_HID_00cc = 0x00cc,
-	BNXT_ULP_ACT_HID_0504 = 0x0504,
-	BNXT_ULP_ACT_HID_01ef = 0x01ef,
-	BNXT_ULP_ACT_HID_03ed = 0x03ed,
-	BNXT_ULP_ACT_HID_0514 = 0x0514,
-	BNXT_ULP_ACT_HID_00db = 0x00db,
-	BNXT_ULP_ACT_HID_00df = 0x00df
+	BNXT_ULP_ACT_HID_05ad = 0x05ad,
+	BNXT_ULP_ACT_HID_01bd = 0x01bd,
+	BNXT_ULP_ACT_HID_0613 = 0x0613,
+	BNXT_ULP_ACT_HID_02a9 = 0x02a9,
+	BNXT_ULP_ACT_HID_0054 = 0x0054,
+	BNXT_ULP_ACT_HID_0622 = 0x0622,
+	BNXT_ULP_ACT_HID_0454 = 0x0454,
+	BNXT_ULP_ACT_HID_0064 = 0x0064,
+	BNXT_ULP_ACT_HID_0614 = 0x0614,
+	BNXT_ULP_ACT_HID_0615 = 0x0615,
+	BNXT_ULP_ACT_HID_02ab = 0x02ab,
+	BNXT_ULP_ACT_HID_0056 = 0x0056,
+	BNXT_ULP_ACT_HID_0624 = 0x0624,
+	BNXT_ULP_ACT_HID_0456 = 0x0456,
+	BNXT_ULP_ACT_HID_0066 = 0x0066,
+	BNXT_ULP_ACT_HID_048d = 0x048d,
+	BNXT_ULP_ACT_HID_048f = 0x048f,
+	BNXT_ULP_ACT_HID_04bc = 0x04bc,
+	BNXT_ULP_ACT_HID_00a9 = 0x00a9,
+	BNXT_ULP_ACT_HID_020f = 0x020f,
+	BNXT_ULP_ACT_HID_04a9 = 0x04a9,
+	BNXT_ULP_ACT_HID_01fc = 0x01fc,
+	BNXT_ULP_ACT_HID_04be = 0x04be,
+	BNXT_ULP_ACT_HID_00ab = 0x00ab,
+	BNXT_ULP_ACT_HID_0211 = 0x0211,
+	BNXT_ULP_ACT_HID_04ab = 0x04ab,
+	BNXT_ULP_ACT_HID_01fe = 0x01fe,
+	BNXT_ULP_ACT_HID_0667 = 0x0667,
+	BNXT_ULP_ACT_HID_0254 = 0x0254,
+	BNXT_ULP_ACT_HID_03ba = 0x03ba,
+	BNXT_ULP_ACT_HID_0654 = 0x0654,
+	BNXT_ULP_ACT_HID_03a7 = 0x03a7,
+	BNXT_ULP_ACT_HID_0669 = 0x0669,
+	BNXT_ULP_ACT_HID_0256 = 0x0256,
+	BNXT_ULP_ACT_HID_03bc = 0x03bc,
+	BNXT_ULP_ACT_HID_0656 = 0x0656,
+	BNXT_ULP_ACT_HID_03a9 = 0x03a9,
+	BNXT_ULP_ACT_HID_021b = 0x021b,
+	BNXT_ULP_ACT_HID_021c = 0x021c,
+	BNXT_ULP_ACT_HID_021e = 0x021e,
+	BNXT_ULP_ACT_HID_063f = 0x063f,
+	BNXT_ULP_ACT_HID_0510 = 0x0510,
+	BNXT_ULP_ACT_HID_03c6 = 0x03c6,
+	BNXT_ULP_ACT_HID_0082 = 0x0082,
+	BNXT_ULP_ACT_HID_06bb = 0x06bb,
+	BNXT_ULP_ACT_HID_021d = 0x021d,
+	BNXT_ULP_ACT_HID_0641 = 0x0641,
+	BNXT_ULP_ACT_HID_0512 = 0x0512,
+	BNXT_ULP_ACT_HID_03c8 = 0x03c8,
+	BNXT_ULP_ACT_HID_0084 = 0x0084,
+	BNXT_ULP_ACT_HID_06bd = 0x06bd,
+	BNXT_ULP_ACT_HID_06d7 = 0x06d7,
+	BNXT_ULP_ACT_HID_02c4 = 0x02c4,
+	BNXT_ULP_ACT_HID_042a = 0x042a,
+	BNXT_ULP_ACT_HID_06c4 = 0x06c4,
+	BNXT_ULP_ACT_HID_0417 = 0x0417,
+	BNXT_ULP_ACT_HID_06d9 = 0x06d9,
+	BNXT_ULP_ACT_HID_02c6 = 0x02c6,
+	BNXT_ULP_ACT_HID_042c = 0x042c,
+	BNXT_ULP_ACT_HID_06c6 = 0x06c6,
+	BNXT_ULP_ACT_HID_0419 = 0x0419,
+	BNXT_ULP_ACT_HID_0119 = 0x0119,
+	BNXT_ULP_ACT_HID_046f = 0x046f,
+	BNXT_ULP_ACT_HID_05d5 = 0x05d5,
+	BNXT_ULP_ACT_HID_0106 = 0x0106,
+	BNXT_ULP_ACT_HID_05c2 = 0x05c2,
+	BNXT_ULP_ACT_HID_011b = 0x011b,
+	BNXT_ULP_ACT_HID_0471 = 0x0471,
+	BNXT_ULP_ACT_HID_05d7 = 0x05d7,
+	BNXT_ULP_ACT_HID_0108 = 0x0108,
+	BNXT_ULP_ACT_HID_05c4 = 0x05c4,
+	BNXT_ULP_ACT_HID_00a2 = 0x00a2,
+	BNXT_ULP_ACT_HID_00a4 = 0x00a4
 };
 
 enum bnxt_ulp_df_tpl {
-	BNXT_ULP_DF_TPL_PORT_TO_VS = 2,
-	BNXT_ULP_DF_TPL_VS_TO_PORT = 3,
-	BNXT_ULP_DF_TPL_VFREP_TO_VF = 4,
-	BNXT_ULP_DF_TPL_VF_TO_VFREP = 5,
-	BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 6
+	BNXT_ULP_DF_TPL_PORT_TO_VS = 3,
+	BNXT_ULP_DF_TPL_VS_TO_PORT = 4,
+	BNXT_ULP_DF_TPL_VFREP_TO_VF = 5,
+	BNXT_ULP_DF_TPL_VF_TO_VFREP = 6,
+	BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7
 };
-
 #endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
index c1294d081c..a6a4b472f4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Dec  7 09:51:03 2020 */
+/* date: Wed Dec 16 16:03:45 2020 */
 
 #ifndef ULP_HDR_FIELD_ENUMS_H_
 #define ULP_HDR_FIELD_ENUMS_H_
@@ -122,16 +122,7 @@ enum bnxt_ulp_hf1_0_bitmask {
 	BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
 	BNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
 	BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM         = 0x0000020000000000,
-	BNXT_ULP_HF1_0_BITMASK_O_TCP_URP          = 0x0000010000000000
+	BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000
 };
 
 enum bnxt_ulp_hf1_1_bitmask {
@@ -150,10 +141,15 @@ enum bnxt_ulp_hf1_1_bitmask {
 	BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
 	BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
 	BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
-	BNXT_ULP_HF1_1_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,
-	BNXT_ULP_HF1_1_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,
-	BNXT_ULP_HF1_1_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,
-	BNXT_ULP_HF1_1_BITMASK_O_UDP_CSUM         = 0x0000200000000000
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM         = 0x0000020000000000,
+	BNXT_ULP_HF1_1_BITMASK_O_TCP_URP          = 0x0000010000000000
 };
 
 enum bnxt_ulp_hf1_2_bitmask {
@@ -162,23 +158,20 @@ enum bnxt_ulp_hf1_2_bitmask {
 	BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
 	BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
 	BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_IPV6_VER         = 0x0400000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_IPV6_TC          = 0x0200000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM         = 0x0000080000000000,
-	BNXT_ULP_HF1_2_BITMASK_O_TCP_URP          = 0x0000040000000000
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_VER         = 0x0400000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS         = 0x0200000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN         = 0x0100000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,
+	BNXT_ULP_HF1_2_BITMASK_O_UDP_CSUM         = 0x0000200000000000
 };
 
 enum bnxt_ulp_hf1_3_bitmask {
@@ -194,11 +187,7 @@ enum bnxt_ulp_hf1_3_bitmask {
 	BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
 	BNXT_ULP_HF1_3_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
 	BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
-	BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,
-	BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT     = 0x0004000000000000,
-	BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT     = 0x0002000000000000,
-	BNXT_ULP_HF1_3_BITMASK_O_UDP_LENGTH       = 0x0001000000000000,
-	BNXT_ULP_HF1_3_BITMASK_O_UDP_CSUM         = 0x0000800000000000
+	BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000
 };
 
 enum bnxt_ulp_hf1_4_bitmask {
@@ -207,28 +196,23 @@ enum bnxt_ulp_hf1_4_bitmask {
 	BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
 	BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
 	BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
-	BNXT_ULP_HF1_4_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
-	BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
-	BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_VER         = 0x0080000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
-	BNXT_ULP_HF1_4_BITMASK_O_TCP_URP          = 0x0000002000000000
+	BNXT_ULP_HF1_4_BITMASK_O_IPV6_VER         = 0x0400000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_IPV6_TC          = 0x0200000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM         = 0x0000080000000000,
+	BNXT_ULP_HF1_4_BITMASK_O_TCP_URP          = 0x0000040000000000
 };
 
 enum bnxt_ulp_hf1_5_bitmask {
@@ -237,23 +221,18 @@ enum bnxt_ulp_hf1_5_bitmask {
 	BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
 	BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
 	BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
-	BNXT_ULP_HF1_5_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
-	BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
-	BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_VER         = 0x0080000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
-	BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM         = 0x0000040000000000
+	BNXT_ULP_HF1_5_BITMASK_O_IPV6_VER         = 0x0400000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_IPV6_TC          = 0x0200000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT     = 0x0004000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT     = 0x0002000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH       = 0x0001000000000000,
+	BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM         = 0x0000800000000000
 };
 
 enum bnxt_ulp_hf1_6_bitmask {
@@ -265,23 +244,16 @@ enum bnxt_ulp_hf1_6_bitmask {
 	BNXT_ULP_HF1_6_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
 	BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
 	BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_IPV6_VER         = 0x0080000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_IPV6_TC          = 0x0040000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_IPV6_TTL         = 0x0004000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_SRC_PORT     = 0x0000800000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_DST_PORT     = 0x0000400000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_SENT_SEQ     = 0x0000200000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_RECV_ACK     = 0x0000100000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_DATA_OFF     = 0x0000080000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_TCP_FLAGS    = 0x0000040000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_RX_WIN       = 0x0000020000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_CSUM         = 0x0000010000000000,
-	BNXT_ULP_HF1_6_BITMASK_O_TCP_URP          = 0x0000008000000000
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_VER         = 0x0080000000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000
 };
 
 enum bnxt_ulp_hf1_7_bitmask {
@@ -293,17 +265,393 @@ enum bnxt_ulp_hf1_7_bitmask {
 	BNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
 	BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
 	BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_IPV6_VER         = 0x0080000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_IPV6_TC          = 0x0040000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_IPV6_TTL         = 0x0004000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT     = 0x0000800000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT     = 0x0000400000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH       = 0x0000200000000000,
-	BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM         = 0x0000100000000000
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER         = 0x0080000000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
+	BNXT_ULP_HF1_7_BITMASK_O_TCP_URP          = 0x0000002000000000
+};
+
+enum bnxt_ulp_hf1_8_bitmask {
+	BNXT_ULP_HF1_8_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF1_8_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF1_8_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+	BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+	BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_VER         = 0x0080000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+	BNXT_ULP_HF1_8_BITMASK_O_UDP_CSUM         = 0x0000040000000000
+};
+
+enum bnxt_ulp_hf1_9_bitmask {
+	BNXT_ULP_HF1_9_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF1_9_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF1_9_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+	BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+	BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_IPV6_VER         = 0x0080000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_IPV6_TC          = 0x0040000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_IPV6_TTL         = 0x0004000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,
+	BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000
+};
+
+enum bnxt_ulp_hf1_10_bitmask {
+	BNXT_ULP_HF1_10_BITMASK_WM                = 0x8000000000000000,
+	BNXT_ULP_HF1_10_BITMASK_SVIF_INDEX        = 0x4000000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_ETH_DMAC        = 0x2000000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_ETH_SMAC        = 0x1000000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_ETH_TYPE        = 0x0800000000000000,
+	BNXT_ULP_HF1_10_BITMASK_OO_VLAN_CFI_PRI   = 0x0400000000000000,
+	BNXT_ULP_HF1_10_BITMASK_OO_VLAN_VID       = 0x0200000000000000,
+	BNXT_ULP_HF1_10_BITMASK_OO_VLAN_TYPE      = 0x0100000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_IPV6_VER        = 0x0080000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_IPV6_TC         = 0x0040000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_IPV6_PROTO_ID   = 0x0008000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_IPV6_TTL        = 0x0004000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR   = 0x0002000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR   = 0x0001000000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT    = 0x0000800000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT    = 0x0000400000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_SENT_SEQ    = 0x0000200000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_RECV_ACK    = 0x0000100000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_DATA_OFF    = 0x0000080000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_TCP_FLAGS   = 0x0000040000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_RX_WIN      = 0x0000020000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_CSUM        = 0x0000010000000000,
+	BNXT_ULP_HF1_10_BITMASK_O_TCP_URP         = 0x0000008000000000
+};
+
+enum bnxt_ulp_hf1_11_bitmask {
+	BNXT_ULP_HF1_11_BITMASK_WM                = 0x8000000000000000,
+	BNXT_ULP_HF1_11_BITMASK_SVIF_INDEX        = 0x4000000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_ETH_DMAC        = 0x2000000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_ETH_SMAC        = 0x1000000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_ETH_TYPE        = 0x0800000000000000,
+	BNXT_ULP_HF1_11_BITMASK_OO_VLAN_CFI_PRI   = 0x0400000000000000,
+	BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID       = 0x0200000000000000,
+	BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE      = 0x0100000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_IPV6_VER        = 0x0080000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_IPV6_TC         = 0x0040000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID   = 0x0008000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_IPV6_TTL        = 0x0004000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR   = 0x0002000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR   = 0x0001000000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT    = 0x0000800000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT    = 0x0000400000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_UDP_LENGTH      = 0x0000200000000000,
+	BNXT_ULP_HF1_11_BITMASK_O_UDP_CSUM        = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf2_0_bitmask {
+	BNXT_ULP_HF2_0_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_0_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_VER         = 0x0400000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS         = 0x0200000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN         = 0x0100000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
+	BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000
+};
+
+enum bnxt_ulp_hf2_1_bitmask {
+	BNXT_ULP_HF2_1_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_1_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_VER         = 0x0400000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_TOS         = 0x0200000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_LEN         = 0x0100000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM         = 0x0000020000000000,
+	BNXT_ULP_HF2_1_BITMASK_O_TCP_URP          = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf2_2_bitmask {
+	BNXT_ULP_HF2_2_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_2_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_VER         = 0x0400000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_TOS         = 0x0200000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_LEN         = 0x0100000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,
+	BNXT_ULP_HF2_2_BITMASK_O_UDP_CSUM         = 0x0000200000000000
+};
+
+enum bnxt_ulp_hf2_3_bitmask {
+	BNXT_ULP_HF2_3_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_3_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_IPV6_VER         = 0x0400000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_IPV6_TC          = 0x0200000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
+	BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000
+};
+
+enum bnxt_ulp_hf2_4_bitmask {
+	BNXT_ULP_HF2_4_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_4_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_IPV6_VER         = 0x0400000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_IPV6_TC          = 0x0200000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_CSUM         = 0x0000080000000000,
+	BNXT_ULP_HF2_4_BITMASK_O_TCP_URP          = 0x0000040000000000
+};
+
+enum bnxt_ulp_hf2_5_bitmask {
+	BNXT_ULP_HF2_5_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_5_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_IPV6_VER         = 0x0400000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_IPV6_TC          = 0x0200000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT     = 0x0004000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT     = 0x0002000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_UDP_LENGTH       = 0x0001000000000000,
+	BNXT_ULP_HF2_5_BITMASK_O_UDP_CSUM         = 0x0000800000000000
+};
+
+enum bnxt_ulp_hf2_6_bitmask {
+	BNXT_ULP_HF2_6_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_6_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_6_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+	BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+	BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_VER         = 0x0080000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000
+};
+
+enum bnxt_ulp_hf2_7_bitmask {
+	BNXT_ULP_HF2_7_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_7_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_7_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+	BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+	BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_VER         = 0x0080000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
+	BNXT_ULP_HF2_7_BITMASK_O_TCP_URP          = 0x0000002000000000
+};
+
+enum bnxt_ulp_hf2_8_bitmask {
+	BNXT_ULP_HF2_8_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_8_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_8_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+	BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+	BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_VER         = 0x0080000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+	BNXT_ULP_HF2_8_BITMASK_O_UDP_CSUM         = 0x0000040000000000
+};
+
+enum bnxt_ulp_hf2_9_bitmask {
+	BNXT_ULP_HF2_9_BITMASK_WM                 = 0x8000000000000000,
+	BNXT_ULP_HF2_9_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+	BNXT_ULP_HF2_9_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+	BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+	BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_IPV6_VER         = 0x0080000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_IPV6_TC          = 0x0040000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_IPV6_TTL         = 0x0004000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,
+	BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000
+};
+
+enum bnxt_ulp_hf2_10_bitmask {
+	BNXT_ULP_HF2_10_BITMASK_WM                = 0x8000000000000000,
+	BNXT_ULP_HF2_10_BITMASK_SVIF_INDEX        = 0x4000000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_ETH_DMAC        = 0x2000000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_ETH_SMAC        = 0x1000000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_ETH_TYPE        = 0x0800000000000000,
+	BNXT_ULP_HF2_10_BITMASK_OO_VLAN_CFI_PRI   = 0x0400000000000000,
+	BNXT_ULP_HF2_10_BITMASK_OO_VLAN_VID       = 0x0200000000000000,
+	BNXT_ULP_HF2_10_BITMASK_OO_VLAN_TYPE      = 0x0100000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_IPV6_VER        = 0x0080000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_IPV6_TC         = 0x0040000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_IPV6_PROTO_ID   = 0x0008000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_IPV6_TTL        = 0x0004000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR   = 0x0002000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR   = 0x0001000000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT    = 0x0000800000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT    = 0x0000400000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_SENT_SEQ    = 0x0000200000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_RECV_ACK    = 0x0000100000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_DATA_OFF    = 0x0000080000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_TCP_FLAGS   = 0x0000040000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_RX_WIN      = 0x0000020000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_CSUM        = 0x0000010000000000,
+	BNXT_ULP_HF2_10_BITMASK_O_TCP_URP         = 0x0000008000000000
+};
+
+enum bnxt_ulp_hf2_11_bitmask {
+	BNXT_ULP_HF2_11_BITMASK_WM                = 0x8000000000000000,
+	BNXT_ULP_HF2_11_BITMASK_SVIF_INDEX        = 0x4000000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_ETH_DMAC        = 0x2000000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_ETH_SMAC        = 0x1000000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_ETH_TYPE        = 0x0800000000000000,
+	BNXT_ULP_HF2_11_BITMASK_OO_VLAN_CFI_PRI   = 0x0400000000000000,
+	BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID       = 0x0200000000000000,
+	BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE      = 0x0100000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_IPV6_VER        = 0x0080000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_IPV6_TC         = 0x0040000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID   = 0x0008000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_IPV6_TTL        = 0x0004000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR   = 0x0002000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR   = 0x0001000000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT    = 0x0000800000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT    = 0x0000400000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_UDP_LENGTH      = 0x0000200000000000,
+	BNXT_ULP_HF2_11_BITMASK_O_UDP_CSUM        = 0x0000100000000000
 };
 #endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
index c1b3c7bcd2..d29b7a200f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
@@ -32,14 +32,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 0,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 0,
 	.result_bit_size = 64,
@@ -54,14 +54,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 1,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 1,
 	.result_bit_size = 0,
@@ -76,14 +76,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 2,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 13,
 	.result_bit_size = 128,
@@ -98,14 +98,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 2,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 39,
 	.result_bit_size = 128,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
index a0cab178ec..df09de929e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
@@ -82,13 +82,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 2,
+		.cond_true_goto = 2,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 0,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.key_start_idx = 0,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
@@ -101,14 +101,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 1,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
 	.key_start_idx = 1,
@@ -129,13 +129,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 1,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.key_start_idx = 14,
 	.blob_key_bit_size = 14,
 	.key_bit_size = 14,
@@ -144,29 +144,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.ident_nums = 3
 	},
 	{ /* class_tid: 1, stingray, table: branch.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 3,
+		.cond_true_goto = 3,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 1,
 		.cond_nums = 1 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID
 	},
 	{ /* class_tid: 1, stingray, table: profile_tcam.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 2,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
 	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
@@ -188,13 +188,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 2,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.key_start_idx = 60,
 	.blob_key_bit_size = 14,
 	.key_bit_size = 14,
@@ -210,12 +210,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 2,
 		.cond_nums = 1 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
 	.key_start_idx = 63,
@@ -233,12 +233,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 3,
 		.cond_nums = 1 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
 	.key_start_idx = 73,
@@ -251,15 +251,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.encap_num_fields = 0
 	},
 	{ /* class_tid: 1, stingray, table: last */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
 		.cond_nums = 0 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID
 	},
 	{ /* class_tid: 2, stingray, table: int_full_act_record.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -268,14 +268,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 44,
 	.result_bit_size = 128,
@@ -287,14 +287,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
 	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
@@ -318,13 +318,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.key_start_idx = 96,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
@@ -339,14 +339,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 87,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -357,14 +357,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 88,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -375,14 +375,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 89,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -395,14 +395,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 90,
 	.result_bit_size = 128,
@@ -414,14 +414,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 4,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
@@ -444,13 +444,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 5,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.key_start_idx = 110,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
@@ -463,14 +463,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
 		.cond_start_idx = 6,
 		.cond_nums = 2 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
 	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
@@ -492,13 +492,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
 		.cond_start_idx = 8,
 		.cond_nums = 2 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.key_start_idx = 124,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
@@ -513,14 +513,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 146,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -531,14 +531,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 147,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -549,14 +549,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 148,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -569,14 +569,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 149,
 	.result_bit_size = 0,
@@ -590,14 +590,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 161,
 	.result_bit_size = 128,
@@ -609,14 +609,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
 	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
@@ -638,13 +638,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.key_start_idx = 138,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
@@ -663,14 +663,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 204,
 	.result_bit_size = 128,
@@ -682,14 +682,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
@@ -710,14 +710,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
@@ -738,14 +738,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
 	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
@@ -767,13 +767,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.key_start_idx = 178,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
@@ -788,14 +788,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 273,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -806,14 +806,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 274,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -824,14 +824,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
 	.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.result_start_idx = 275,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
@@ -844,14 +844,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
 	.result_start_idx = 276,
 	.result_bit_size = 128,
@@ -863,14 +863,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
@@ -893,7 +893,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 10,
 		.cond_nums = 0 },
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
index 6b49a9d93f..64cf6534b9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Fri Dec  4 19:01:47 2020 */
+/* date: Wed Dec 16 16:03:45 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -99,6 +99,10 @@ const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = {
 	.tmpl_list_size          = ULP_WH_PLUS_ACT_TMPL_LIST_SIZE,
 	.tbl_list                = ulp_wh_plus_act_tbl_list,
 	.tbl_list_size           = ULP_WH_PLUS_ACT_TBL_LIST_SIZE,
+	.key_info_list           = ulp_wh_plus_act_key_info_list,
+	.key_info_list_size      = ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE,
+	.ident_list              = ulp_wh_plus_act_ident_list,
+	.ident_list_size         = ULP_WH_PLUS_ACT_IDENT_LIST_SIZE,
 	.cond_list               = ulp_wh_plus_act_cond_list,
 	.cond_list_size          = ULP_WH_PLUS_ACT_COND_LIST_SIZE,
 	.result_field_list       = ulp_wh_plus_act_result_field_list,
@@ -322,15 +326,6 @@ uint8_t ulp_glb_field_tbl[] = {
 	[2070] = 12,
 	[2072] = 13,
 	[2074] = 14,
-	[2102] = 15,
-	[2104] = 16,
-	[2106] = 17,
-	[2108] = 18,
-	[2110] = 19,
-	[2112] = 20,
-	[2114] = 21,
-	[2116] = 22,
-	[2118] = 23,
 	[2176] = 0,
 	[2177] = 1,
 	[2178] = 2,
@@ -346,32 +341,34 @@ uint8_t ulp_glb_field_tbl[] = {
 	[2198] = 12,
 	[2200] = 13,
 	[2202] = 14,
-	[2248] = 15,
-	[2250] = 16,
-	[2252] = 17,
-	[2254] = 18,
+	[2230] = 15,
+	[2232] = 16,
+	[2234] = 17,
+	[2236] = 18,
+	[2238] = 19,
+	[2240] = 20,
+	[2242] = 21,
+	[2244] = 22,
+	[2246] = 23,
 	[2304] = 0,
 	[2305] = 1,
 	[2306] = 2,
 	[2308] = 3,
 	[2310] = 4,
-	[2332] = 5,
-	[2334] = 6,
-	[2336] = 7,
-	[2338] = 8,
-	[2340] = 9,
-	[2342] = 10,
-	[2344] = 11,
-	[2346] = 12,
-	[2358] = 13,
-	[2360] = 14,
-	[2362] = 15,
-	[2364] = 16,
-	[2366] = 17,
-	[2368] = 18,
-	[2370] = 19,
-	[2372] = 20,
-	[2374] = 21,
+	[2312] = 5,
+	[2314] = 6,
+	[2316] = 7,
+	[2318] = 8,
+	[2320] = 9,
+	[2322] = 10,
+	[2324] = 11,
+	[2326] = 12,
+	[2328] = 13,
+	[2330] = 14,
+	[2376] = 15,
+	[2378] = 16,
+	[2380] = 17,
+	[2382] = 18,
 	[2432] = 0,
 	[2433] = 1,
 	[2434] = 2,
@@ -385,81 +382,60 @@ uint8_t ulp_glb_field_tbl[] = {
 	[2470] = 10,
 	[2472] = 11,
 	[2474] = 12,
-	[2504] = 13,
-	[2506] = 14,
-	[2508] = 15,
-	[2510] = 16,
 	[2560] = 0,
 	[2561] = 1,
 	[2562] = 2,
 	[2564] = 3,
 	[2566] = 4,
-	[2568] = 8,
-	[2570] = 9,
-	[2572] = 10,
-	[2574] = 11,
-	[2576] = 12,
-	[2578] = 13,
-	[2580] = 14,
-	[2582] = 15,
-	[2584] = 16,
-	[2586] = 17,
-	[2614] = 18,
-	[2616] = 19,
-	[2618] = 20,
-	[2620] = 21,
-	[2622] = 22,
-	[2624] = 23,
-	[2626] = 24,
-	[2628] = 25,
-	[2630] = 26,
-	[2640] = 5,
-	[2644] = 6,
-	[2648] = 7,
+	[2588] = 5,
+	[2590] = 6,
+	[2592] = 7,
+	[2594] = 8,
+	[2596] = 9,
+	[2598] = 10,
+	[2600] = 11,
+	[2602] = 12,
+	[2614] = 13,
+	[2616] = 14,
+	[2618] = 15,
+	[2620] = 16,
+	[2622] = 17,
+	[2624] = 18,
+	[2626] = 19,
+	[2628] = 20,
+	[2630] = 21,
 	[2688] = 0,
 	[2689] = 1,
 	[2690] = 2,
 	[2692] = 3,
 	[2694] = 4,
-	[2696] = 8,
-	[2698] = 9,
-	[2700] = 10,
-	[2702] = 11,
-	[2704] = 12,
-	[2706] = 13,
-	[2708] = 14,
-	[2710] = 15,
-	[2712] = 16,
-	[2714] = 17,
-	[2760] = 18,
-	[2762] = 19,
-	[2764] = 20,
-	[2766] = 21,
-	[2768] = 5,
-	[2772] = 6,
-	[2776] = 7,
+	[2716] = 5,
+	[2718] = 6,
+	[2720] = 7,
+	[2722] = 8,
+	[2724] = 9,
+	[2726] = 10,
+	[2728] = 11,
+	[2730] = 12,
+	[2760] = 13,
+	[2762] = 14,
+	[2764] = 15,
+	[2766] = 16,
 	[2816] = 0,
 	[2817] = 1,
 	[2818] = 2,
 	[2820] = 3,
 	[2822] = 4,
-	[2844] = 8,
-	[2846] = 9,
-	[2848] = 10,
-	[2850] = 11,
-	[2852] = 12,
-	[2854] = 13,
-	[2856] = 14,
-	[2858] = 15,
-	[2870] = 16,
-	[2872] = 17,
-	[2874] = 18,
-	[2876] = 19,
-	[2878] = 20,
-	[2880] = 21,
-	[2882] = 22,
-	[2884] = 23,
-	[2886] = 24,
+	[2824] = 8,
+	[2826] = 9,
+	[2828] = 10,
+	[2830] = 11,
+	[2832] = 12,
+	[2834] = 13,
+	[2836] = 14,
+	[2838] = 15,
+	[2840] = 16,
+	[2842] = 17,
 	[2896] = 5,
 	[2900] = 6,
 	[2904] = 7,
@@ -468,20 +444,348 @@ uint8_t ulp_glb_field_tbl[] = {
 	[2946] = 2,
 	[2948] = 3,
 	[2950] = 4,
-	[2972] = 8,
-	[2974] = 9,
-	[2976] = 10,
-	[2978] = 11,
-	[2980] = 12,
-	[2982] = 13,
-	[2984] = 14,
-	[2986] = 15,
-	[3016] = 16,
-	[3018] = 17,
-	[3020] = 18,
-	[3022] = 19,
+	[2952] = 8,
+	[2954] = 9,
+	[2956] = 10,
+	[2958] = 11,
+	[2960] = 12,
+	[2962] = 13,
+	[2964] = 14,
+	[2966] = 15,
+	[2968] = 16,
+	[2970] = 17,
+	[2998] = 18,
+	[3000] = 19,
+	[3002] = 20,
+	[3004] = 21,
+	[3006] = 22,
+	[3008] = 23,
+	[3010] = 24,
+	[3012] = 25,
+	[3014] = 26,
 	[3024] = 5,
 	[3028] = 6,
-	[3032] = 7
+	[3032] = 7,
+	[3072] = 0,
+	[3073] = 1,
+	[3074] = 2,
+	[3076] = 3,
+	[3078] = 4,
+	[3080] = 8,
+	[3082] = 9,
+	[3084] = 10,
+	[3086] = 11,
+	[3088] = 12,
+	[3090] = 13,
+	[3092] = 14,
+	[3094] = 15,
+	[3096] = 16,
+	[3098] = 17,
+	[3144] = 18,
+	[3146] = 19,
+	[3148] = 20,
+	[3150] = 21,
+	[3152] = 5,
+	[3156] = 6,
+	[3160] = 7,
+	[3200] = 0,
+	[3201] = 1,
+	[3202] = 2,
+	[3204] = 3,
+	[3206] = 4,
+	[3228] = 8,
+	[3230] = 9,
+	[3232] = 10,
+	[3234] = 11,
+	[3236] = 12,
+	[3238] = 13,
+	[3240] = 14,
+	[3242] = 15,
+	[3280] = 5,
+	[3284] = 6,
+	[3288] = 7,
+	[3328] = 0,
+	[3329] = 1,
+	[3330] = 2,
+	[3332] = 3,
+	[3334] = 4,
+	[3356] = 8,
+	[3358] = 9,
+	[3360] = 10,
+	[3362] = 11,
+	[3364] = 12,
+	[3366] = 13,
+	[3368] = 14,
+	[3370] = 15,
+	[3382] = 16,
+	[3384] = 17,
+	[3386] = 18,
+	[3388] = 19,
+	[3390] = 20,
+	[3392] = 21,
+	[3394] = 22,
+	[3396] = 23,
+	[3398] = 24,
+	[3408] = 5,
+	[3412] = 6,
+	[3416] = 7,
+	[3456] = 0,
+	[3457] = 1,
+	[3458] = 2,
+	[3460] = 3,
+	[3462] = 4,
+	[3484] = 8,
+	[3486] = 9,
+	[3488] = 10,
+	[3490] = 11,
+	[3492] = 12,
+	[3494] = 13,
+	[3496] = 14,
+	[3498] = 15,
+	[3528] = 16,
+	[3530] = 17,
+	[3532] = 18,
+	[3534] = 19,
+	[3536] = 5,
+	[3540] = 6,
+	[3544] = 7,
+	[4096] = 0,
+	[4097] = 1,
+	[4098] = 2,
+	[4100] = 3,
+	[4102] = 4,
+	[4104] = 5,
+	[4106] = 6,
+	[4108] = 7,
+	[4110] = 8,
+	[4112] = 9,
+	[4114] = 10,
+	[4116] = 11,
+	[4118] = 12,
+	[4120] = 13,
+	[4122] = 14,
+	[4224] = 0,
+	[4225] = 1,
+	[4226] = 2,
+	[4228] = 3,
+	[4230] = 4,
+	[4232] = 5,
+	[4234] = 6,
+	[4236] = 7,
+	[4238] = 8,
+	[4240] = 9,
+	[4242] = 10,
+	[4244] = 11,
+	[4246] = 12,
+	[4248] = 13,
+	[4250] = 14,
+	[4278] = 15,
+	[4280] = 16,
+	[4282] = 17,
+	[4284] = 18,
+	[4286] = 19,
+	[4288] = 20,
+	[4290] = 21,
+	[4292] = 22,
+	[4294] = 23,
+	[4352] = 0,
+	[4353] = 1,
+	[4354] = 2,
+	[4356] = 3,
+	[4358] = 4,
+	[4360] = 5,
+	[4362] = 6,
+	[4364] = 7,
+	[4366] = 8,
+	[4368] = 9,
+	[4370] = 10,
+	[4372] = 11,
+	[4374] = 12,
+	[4376] = 13,
+	[4378] = 14,
+	[4424] = 15,
+	[4426] = 16,
+	[4428] = 17,
+	[4430] = 18,
+	[4480] = 0,
+	[4481] = 1,
+	[4482] = 2,
+	[4484] = 3,
+	[4486] = 4,
+	[4508] = 5,
+	[4510] = 6,
+	[4512] = 7,
+	[4514] = 8,
+	[4516] = 9,
+	[4518] = 10,
+	[4520] = 11,
+	[4522] = 12,
+	[4608] = 0,
+	[4609] = 1,
+	[4610] = 2,
+	[4612] = 3,
+	[4614] = 4,
+	[4636] = 5,
+	[4638] = 6,
+	[4640] = 7,
+	[4642] = 8,
+	[4644] = 9,
+	[4646] = 10,
+	[4648] = 11,
+	[4650] = 12,
+	[4662] = 13,
+	[4664] = 14,
+	[4666] = 15,
+	[4668] = 16,
+	[4670] = 17,
+	[4672] = 18,
+	[4674] = 19,
+	[4676] = 20,
+	[4678] = 21,
+	[4736] = 0,
+	[4737] = 1,
+	[4738] = 2,
+	[4740] = 3,
+	[4742] = 4,
+	[4764] = 5,
+	[4766] = 6,
+	[4768] = 7,
+	[4770] = 8,
+	[4772] = 9,
+	[4774] = 10,
+	[4776] = 11,
+	[4778] = 12,
+	[4808] = 13,
+	[4810] = 14,
+	[4812] = 15,
+	[4814] = 16,
+	[4864] = 0,
+	[4865] = 1,
+	[4866] = 2,
+	[4868] = 3,
+	[4870] = 4,
+	[4872] = 8,
+	[4874] = 9,
+	[4876] = 10,
+	[4878] = 11,
+	[4880] = 12,
+	[4882] = 13,
+	[4884] = 14,
+	[4886] = 15,
+	[4888] = 16,
+	[4890] = 17,
+	[4944] = 5,
+	[4948] = 6,
+	[4952] = 7,
+	[4992] = 0,
+	[4993] = 1,
+	[4994] = 2,
+	[4996] = 3,
+	[4998] = 4,
+	[5000] = 8,
+	[5002] = 9,
+	[5004] = 10,
+	[5006] = 11,
+	[5008] = 12,
+	[5010] = 13,
+	[5012] = 14,
+	[5014] = 15,
+	[5016] = 16,
+	[5018] = 17,
+	[5046] = 18,
+	[5048] = 19,
+	[5050] = 20,
+	[5052] = 21,
+	[5054] = 22,
+	[5056] = 23,
+	[5058] = 24,
+	[5060] = 25,
+	[5062] = 26,
+	[5072] = 5,
+	[5076] = 6,
+	[5080] = 7,
+	[5120] = 0,
+	[5121] = 1,
+	[5122] = 2,
+	[5124] = 3,
+	[5126] = 4,
+	[5128] = 8,
+	[5130] = 9,
+	[5132] = 10,
+	[5134] = 11,
+	[5136] = 12,
+	[5138] = 13,
+	[5140] = 14,
+	[5142] = 15,
+	[5144] = 16,
+	[5146] = 17,
+	[5192] = 18,
+	[5194] = 19,
+	[5196] = 20,
+	[5198] = 21,
+	[5200] = 5,
+	[5204] = 6,
+	[5208] = 7,
+	[5248] = 0,
+	[5249] = 1,
+	[5250] = 2,
+	[5252] = 3,
+	[5254] = 4,
+	[5276] = 8,
+	[5278] = 9,
+	[5280] = 10,
+	[5282] = 11,
+	[5284] = 12,
+	[5286] = 13,
+	[5288] = 14,
+	[5290] = 15,
+	[5328] = 5,
+	[5332] = 6,
+	[5336] = 7,
+	[5376] = 0,
+	[5377] = 1,
+	[5378] = 2,
+	[5380] = 3,
+	[5382] = 4,
+	[5404] = 8,
+	[5406] = 9,
+	[5408] = 10,
+	[5410] = 11,
+	[5412] = 12,
+	[5414] = 13,
+	[5416] = 14,
+	[5418] = 15,
+	[5430] = 16,
+	[5432] = 17,
+	[5434] = 18,
+	[5436] = 19,
+	[5438] = 20,
+	[5440] = 21,
+	[5442] = 22,
+	[5444] = 23,
+	[5446] = 24,
+	[5456] = 5,
+	[5460] = 6,
+	[5464] = 7,
+	[5504] = 0,
+	[5505] = 1,
+	[5506] = 2,
+	[5508] = 3,
+	[5510] = 4,
+	[5532] = 8,
+	[5534] = 9,
+	[5536] = 10,
+	[5538] = 11,
+	[5540] = 12,
+	[5542] = 13,
+	[5544] = 14,
+	[5546] = 15,
+	[5576] = 16,
+	[5578] = 17,
+	[5580] = 18,
+	[5582] = 19,
+	[5584] = 5,
+	[5588] = 6,
+	[5592] = 7
 };
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h
index befde44a1b..cccdcf5b72 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h
@@ -36,6 +36,10 @@ bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[];
 extern struct
 bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[];
 
+extern struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[];
+
+extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[];
+
 /* STINGRAY template table declarations */
 extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[];
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
index 3de82a673f..8cc81b1451 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Tue Dec  8 14:57:13 2020 */
+/* date: Thu Dec 17 19:43:07 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -25,12 +25,52 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
 	/* act_tid: 2, wh_plus, ingress */
 	[2] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 6,
+	.num_tbls = 7,
 	.start_tbl_idx = 5,
 	.reject_info = {
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
 		.cond_start_idx = 12,
 		.cond_nums = 0 }
+	},
+	/* act_tid: 3, wh_plus, ingress */
+	[3] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 6,
+	.start_tbl_idx = 12,
+	.reject_info = {
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+		.cond_start_idx = 13,
+		.cond_nums = 0 }
+	},
+	/* act_tid: 4, wh_plus, egress */
+	[4] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 5,
+	.start_tbl_idx = 18,
+	.reject_info = {
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 }
+	},
+	/* act_tid: 5, wh_plus, egress */
+	[5] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 6,
+	.start_tbl_idx = 23,
+	.reject_info = {
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+		.cond_start_idx = 20,
+		.cond_nums = 0 }
+	},
+	/* act_tid: 6, wh_plus, egress */
+	[6] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 6,
+	.start_tbl_idx = 29,
+	.reject_info = {
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+		.cond_start_idx = 23,
+		.cond_nums = 0 }
 	}
 };
 
@@ -42,13 +82,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 9,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
 	.key_start_idx = 0,
 	.blob_key_bit_size = 1,
 	.key_bit_size = 1,
@@ -63,14 +104,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 10,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 0,
 	.result_bit_size = 64,
@@ -84,14 +126,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 11,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 1,
 	.result_bit_size = 0,
@@ -106,14 +149,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 12,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 13,
 	.result_bit_size = 128,
@@ -128,19 +172,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 12,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.result_start_idx = 39,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
-	.encap_num_fields = 0
+	.encap_num_fields = 12
+	},
+	{ /* act_tid: 2, wh_plus, table: control.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 12,
+		.cond_nums = 0 },
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID
 	},
 	{ /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -149,16 +207,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 12,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 65,
+	.result_start_idx = 77,
 	.result_bit_size = 32,
 	.result_num_fields = 6
 	},
@@ -169,16 +229,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 12,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 71,
+	.result_start_idx = 83,
 	.result_bit_size = 64,
 	.result_num_fields = 1
 	},
@@ -190,16 +252,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 13,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 72,
+	.result_start_idx = 84,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0
@@ -212,19 +276,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 13,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 98,
+	.result_start_idx = 110,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
-	.encap_num_fields = 0
+	.encap_num_fields = 12
 	},
 	{ /* act_tid: 2, wh_plus, table: mirror_tbl.wr */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -233,7 +299,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 13,
 		.cond_nums = 0 },
@@ -242,7 +309,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
 	.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 124,
+	.result_start_idx = 148,
 	.result_bit_size = 32,
 	.result_num_fields = 6
 	},
@@ -253,133 +320,3643 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 13,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
 	.key_start_idx = 1,
 	.blob_key_bit_size = 1,
 	.key_bit_size = 1,
 	.key_num_fields = 1,
-	.result_start_idx = 130,
+	.result_start_idx = 154,
 	.result_bit_size = 34,
 	.result_num_fields = 2
-	}
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC
-	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_SRC
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC
+	{ /* act_tid: 3, wh_plus, table: int_flow_counter_tbl.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_STATS_64,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 13,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 156,
+	.result_bit_size = 64,
+	.result_num_fields = 1
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
+	{ /* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 14,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 157,
+	.result_bit_size = 32,
+	.result_num_fields = 1
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_DST
+	{ /* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 15,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 158,
+	.result_bit_size = 32,
+	.result_num_fields = 1
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST
+	{ /* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+	.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+	.result_start_idx = 159,
+	.result_bit_size = 0,
+	.result_num_fields = 0,
+	.encap_num_fields = 12
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+	{ /* act_tid: 3, wh_plus, table: int_full_act_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_RX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 171,
+	.result_bit_size = 128,
+	.result_num_fields = 26
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID
+	{ /* act_tid: 3, wh_plus, table: ext_full_act_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_EXT,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_RX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 197,
+	.result_bit_size = 128,
+	.result_num_fields = 26,
+	.encap_num_fields = 12
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP
+	{ /* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_STATS_64,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 16,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 235,
+	.result_bit_size = 64,
+	.result_num_fields = 1
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+	{ /* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 17,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 236,
+	.result_bit_size = 0,
+	.result_num_fields = 0,
+	.encap_num_fields = 12
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_COUNT
+	{ /* act_tid: 4, wh_plus, table: int_full_act_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 18,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 248,
+	.result_bit_size = 128,
+	.result_num_fields = 26
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+	{ /* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_EXT,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 18,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 274,
+	.result_bit_size = 128,
+	.result_num_fields = 26,
+	.encap_num_fields = 12
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_ACT_BIT_COUNT
-	}
-};
-
-struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = {
-	/* act_tid: 1, wh_plus, table: shared_mirror_record.rd */
-	{
-	.field_info_mask = {
-		.description = "shared_index",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "shared_index",
-		.field_bit_size = 1,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
-		.field_opr1 = {
-			(BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
-			BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
-		}
+	{ /* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_EXT,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 19,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 312,
+	.result_bit_size = 128,
+	.result_num_fields = 26,
+	.encap_num_fields = 12
 	},
-	/* act_tid: 2, wh_plus, table: shared_mirror_record.wr */
-	{
-	.field_info_mask = {
-		.description = "shared_index",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "shared_index",
-		.field_bit_size = 1,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
-		}
+	{ /* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_STATS_64,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 20,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 350,
+	.result_bit_size = 64,
+	.result_num_fields = 1
+	},
+	{ /* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 21,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 351,
+	.result_bit_size = 32,
+	.result_num_fields = 1
+	},
+	{ /* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 22,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 352,
+	.result_bit_size = 32,
+	.result_num_fields = 1
+	},
+	{ /* act_tid: 5, wh_plus, table: int_encap_mac_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 23,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+	.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+	.result_start_idx = 353,
+	.result_bit_size = 0,
+	.result_num_fields = 0,
+	.encap_num_fields = 12
+	},
+	{ /* act_tid: 5, wh_plus, table: int_full_act_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 23,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 365,
+	.result_bit_size = 128,
+	.result_num_fields = 26
+	},
+	{ /* act_tid: 5, wh_plus, table: ext_full_act_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_EXT,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 23,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 391,
+	.result_bit_size = 128,
+	.result_num_fields = 26,
+	.encap_num_fields = 12
+	},
+	{ /* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_STATS_64,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 23,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 429,
+	.result_bit_size = 64,
+	.result_num_fields = 1
+	},
+	{ /* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 24,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 430,
+	.result_bit_size = 0,
+	.result_num_fields = 0,
+	.encap_num_fields = 3
+	},
+	{ /* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 25,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 433,
+	.result_bit_size = 0,
+	.result_num_fields = 0,
+	.encap_num_fields = 3
+	},
+	{ /* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 26,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 436,
+	.result_bit_size = 0,
+	.result_num_fields = 0,
+	.encap_num_fields = 12
+	},
+	{ /* act_tid: 6, wh_plus, table: int_full_act_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 26,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 448,
+	.result_bit_size = 128,
+	.result_num_fields = 26
+	},
+	{ /* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_EXT,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 26,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 474,
+	.result_bit_size = 128,
+	.result_num_fields = 26,
+	.encap_num_fields = 12
 	}
 };
 
-struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
-	/* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */
+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
+	/* cond_reject: wh_plus, act_tid: 1 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_SRC
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV6_DST
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP
+	},
+	/* cond_execute: act_tid: 1, shared_mirror_record.rd */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+	},
+	/* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_COUNT
+	},
+	/* cond_execute: act_tid: 1, int_vtag_encap_record.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+	},
+	/* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_COUNT
+	},
+	/* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_COUNT
+	},
+	/* cond_execute: act_tid: 3, act_modify_ipv4_src.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC
+	},
+	/* cond_execute: act_tid: 3, act_modify_ipv4_dst.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
+	},
+	/* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_COUNT
+	},
+	/* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+	},
+	/* cond_execute: act_tid: 4, ext_full_act_record.no_tag */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+	},
+	/* cond_execute: act_tid: 4, ext_full_act_record.one_tag */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+	},
+	/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_COUNT
+	},
+	/* cond_execute: act_tid: 5, act_modify_ipv4_src.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC
+	},
+	/* cond_execute: act_tid: 5, act_modify_ipv4_dst.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
+	},
+	/* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACT_BIT_COUNT
+	},
+	/* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+	.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+	},
+	/* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+	.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+	}
+};
+
+struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[] = {
+	/* act_tid: 1, wh_plus, table: shared_mirror_record.rd */
+	{
+	.field_info_mask = {
+		.description = "shared_index",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "shared_index",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+		.field_opr1 = {
+			(BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+			BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+		}
+	},
+	/* act_tid: 2, wh_plus, table: shared_mirror_record.wr */
+	{
+	.field_info_mask = {
+		.description = "shared_index",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "shared_index",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+		}
+	}
+};
+
+struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
+	/* act_tid: 1, wh_plus, table: int_flow_counter_tbl.0 */
+	{
+	.description = "count",
+	.field_bit_size = 64,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 80,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 1, wh_plus, table: int_full_act_record.0 */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_DECAP_FUNC_THRU_TUN},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr2 = {
+		ULP_WP_SYM_DECAP_FUNC_NONE}
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+	},
+	{
+	.description = "hit",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "type",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 1, wh_plus, table: ext_full_act_record.0 */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "flow_cntr_ext",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_DECAP_FUNC_THRU_TUN},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr2 = {
+		ULP_WP_SYM_DECAP_FUNC_NONE}
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+	},
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_L2_EN_YES}
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 0,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 2, wh_plus, table: mirror_tbl.alloc */
+	{
+	.description = "act_rec_ptr",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "copy",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ign_drop",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "reserved",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "sp_ptr",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */
+	{
+	.description = "count",
+	.field_bit_size = 64,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 2, wh_plus, table: int_full_act_record.0 */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr2 = {
+		1}
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "hit",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "type",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 2, wh_plus, table: ext_full_act_record.0 */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "flow_cntr_ext",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr2 = {
+		1}
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_L2_EN_YES}
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 0,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 2, wh_plus, table: mirror_tbl.wr */
+	{
+	.description = "act_rec_ptr",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+	},
+	{
+	.description = "enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "copy",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ign_drop",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "reserved",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "sp_ptr",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 2, wh_plus, table: shared_mirror_record.wr */
+	{
+	.description = "rid",
+	.field_bit_size = 32,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_RID & 0xff}
+	},
+	{
+	.description = "mirror_id",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr2 = {
+		(1 >> 8) & 0xff,
+		1 & 0xff}
+	},
+	/* act_tid: 3, wh_plus, table: int_flow_counter_tbl.0 */
+	{
+	.description = "count",
+	.field_bit_size = 64,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 3, wh_plus, table: act_modify_ipv4_src.0 */
+	{
+	.description = "ipv4_addr",
+	.field_bit_size = 32,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}
+	},
+	/* act_tid: 3, wh_plus, table: act_modify_ipv4_dst.0 */
+	{
+	.description = "ipv4_addr",
+	.field_bit_size = 32,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}
+	},
+	/* act_tid: 3, wh_plus, table: int_encap_mac_record.0 */
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_L2_EN_YES}
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 80,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 3, wh_plus, table: int_full_act_record.0 */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff,
+		BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff}
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_DECAP_FUNC_THRU_TL2},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr2 = {
+		ULP_WP_SYM_DECAP_FUNC_THRU_L2}
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "hit",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "type",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 3, wh_plus, table: ext_full_act_record.0 */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "flow_cntr_ext",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff,
+		BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff}
+	},
+	{
+	.description = "encap_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_DECAP_FUNC_THRU_TL2},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr2 = {
+		ULP_WP_SYM_DECAP_FUNC_THRU_L2}
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_L2_EN_YES}
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 0,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 4, wh_plus, table: int_flow_counter_tbl.0 */
+	{
+	.description = "count",
+	.field_bit_size = 64,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 4, wh_plus, table: int_vtag_encap_record.0 */
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 80,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 4, wh_plus, table: int_full_act_record.0 */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+	},
+	{
+	.description = "hit",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "type",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 4, wh_plus, table: ext_full_act_record.no_tag */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "flow_cntr_ext",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+	},
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_L2_EN_YES}
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 0,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 4, wh_plus, table: ext_full_act_record.one_tag */
+	{
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+	},
+	{
+	.description = "age_enable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+	},
+	{
+	.description = "flow_cntr_ext",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "encap_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter_id",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_opr1 = {
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+	},
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 0,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 5, wh_plus, table: int_flow_counter_tbl.0 */
+	{
+	.description = "count",
+	.field_bit_size = 64,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* act_tid: 5, wh_plus, table: act_modify_ipv4_src.0 */
+	{
+	.description = "ipv4_addr",
+	.field_bit_size = 32,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}
+	},
+	/* act_tid: 5, wh_plus, table: act_modify_ipv4_dst.0 */
 	{
-	.description = "count",
-	.field_bit_size = 64,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "ipv4_addr",
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}
 	},
-	/* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */
+	/* act_tid: 5, wh_plus, table: int_encap_mac_record.0 */
 	{
 	.description = "ecv_tun_type",
 	.field_bit_size = 3,
@@ -406,16 +3983,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_L2_EN_YES}
 	},
 	{
 	.description = "ecv_vtag_type",
 	.field_bit_size = 4,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "ecv_custom_en",
@@ -429,25 +4006,23 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
 	.description = "vtag_tpid",
 	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
-	.field_opr1 = {
-		(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
-		BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "vtag_vid",
 	.field_bit_size = 12,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
-	.field_opr1 = {
-		(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "vtag_de",
@@ -459,11 +4034,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	{
 	.description = "vtag_pcp",
 	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
-	.field_opr1 = {
-		(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
-		BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "spare",
@@ -472,7 +4045,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* act_tid: 1, wh_plus, table: int_full_act_record.0 */
+	/* act_tid: 5, wh_plus, table: int_full_act_record.0 */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -543,10 +4116,10 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.description = "encap_ptr",
 	.field_bit_size = 11,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
 	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+		(BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff,
+		BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff}
 	},
 	{
 	.description = "dst_ip_ptr",
@@ -574,7 +4147,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_opr1 = {
 		(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
 		BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "src_ip_ptr",
@@ -602,7 +4175,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_opr1 = {
 		(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
 		BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "meter_id",
@@ -646,22 +4219,22 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	{
 	.description = "decap_func",
 	.field_bit_size = 4,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
 	.field_cond_opr = {
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
 	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 	.field_opr1 = {
-		ULP_WP_SYM_DECAP_FUNC_THRU_TUN},
+		ULP_WP_SYM_DECAP_FUNC_THRU_TL2},
 	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
 	.field_opr2 = {
-		ULP_WP_SYM_DECAP_FUNC_NONE}
+		ULP_WP_SYM_DECAP_FUNC_THRU_L2}
 	},
 	{
 	.description = "vnic_or_vport",
@@ -669,23 +4242,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
-		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
 	},
 	{
 	.description = "pop_vlan",
 	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
-	.field_opr1 = {
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "meter",
@@ -697,36 +4262,16 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	{
 	.description = "mirror",
 	.field_bit_size = 2,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
-	.field_cond_opr = {
-		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "drop",
 	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
-	.field_opr1 = {
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "hit",
@@ -742,7 +4287,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* act_tid: 1, wh_plus, table: ext_full_act_record.0 */
+	/* act_tid: 5, wh_plus, table: ext_full_act_record.0 */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -819,16 +4364,20 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	{
 	.description = "encap_ptr",
 	.field_bit_size = 11,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR >> 8) & 0xff,
+		BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR & 0xff}
 	},
 	{
 	.description = "encap_rec_int",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
 	.description = "dst_ip_ptr",
@@ -856,7 +4405,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_opr1 = {
 		(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
 		BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "src_ip_ptr",
@@ -884,7 +4433,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_opr1 = {
 		(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
 		BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST
+	.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "meter_id",
@@ -894,122 +4443,270 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "l3_rdir",
-	.field_bit_size = 1,
+	.description = "l3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "l3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+	},
+	{
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+	},
+	{
+	.description = "decap_func",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+	.field_cond_opr = {
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 56) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 48) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 40) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 32) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 24) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 16) & 0xff,
+		((uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN >> 8) & 0xff,
+		(uint64_t)BNXT_ULP_HDR_BIT_T_VXLAN & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_DECAP_FUNC_THRU_TL2},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr2 = {
+		ULP_WP_SYM_DECAP_FUNC_THRU_L2}
+	},
+	{
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+	},
+	{
+	.description = "pop_vlan",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "meter",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_l2_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_L2_EN_YES}
+	},
+	{
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_custom_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "ecv_valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_tpid",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_vid",
+	.field_bit_size = 12,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_de",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "vtag_pcp",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "spare",
+	.field_bit_size = 0,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* act_tid: 6, wh_plus, table: int_flow_counter_tbl.0 */
 	{
-	.description = "tl3_rdir",
-	.field_bit_size = 1,
+	.description = "count",
+	.field_bit_size = 64,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* act_tid: 6, wh_plus, table: sp_smac_ipv4.0 */
 	{
-	.description = "l3_ttl_dec",
-	.field_bit_size = 1,
+	.description = "smac",
+	.field_bit_size = 48,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
 	},
 	{
-	.description = "tl3_ttl_dec",
-	.field_bit_size = 1,
+	.description = "ipv4_src_addr",
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
 	},
 	{
-	.description = "decap_func",
-	.field_bit_size = 4,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
-	.field_cond_opr = {
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		ULP_WP_SYM_DECAP_FUNC_THRU_TUN},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr2 = {
-		ULP_WP_SYM_DECAP_FUNC_NONE}
+	.description = "reserved",
+	.field_bit_size = 48,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* act_tid: 6, wh_plus, table: sp_smac_ipv6.0 */
 	{
-	.description = "vnic_or_vport",
-	.field_bit_size = 12,
+	.description = "smac",
+	.field_bit_size = 48,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
-		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff}
 	},
 	{
-	.description = "pop_vlan",
-	.field_bit_size = 1,
+	.description = "ipv6_src_addr",
+	.field_bit_size = 128,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff}
 	},
 	{
-	.description = "meter",
-	.field_bit_size = 1,
+	.description = "reserved",
+	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* act_tid: 6, wh_plus, table: int_tun_encap_record.0 */
 	{
-	.description = "mirror",
-	.field_bit_size = 2,
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
+		ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
 	},
 	{
-	.description = "drop",
-	.field_bit_size = 1,
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 	.field_opr1 = {
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+		ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
 	},
-	/* act_tid: 2, wh_plus, table: mirror_tbl.alloc */
 	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 16,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
 	},
 	{
-	.description = "enable",
+	.description = "ecv_l2_en",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -1018,42 +4715,85 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 		1}
 	},
 	{
-	.description = "copy",
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+	},
+	{
+	.description = "ecv_custom_en",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "ign_drop",
+	.description = "ecv_valid",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.description = "reserved",
-	.field_bit_size = 2,
+	.description = "encap_l2_dmac",
+	.field_bit_size = 48,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+	},
+	{
+	.description = "encap_vtag",
+	.field_bit_size = 0,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
 	},
 	{
-	.description = "sp_ptr",
-	.field_bit_size = 11,
+	.description = "encap_ip",
+	.field_bit_size = 0,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
 	},
-	/* act_tid: 2, wh_plus, table: int_flow_counter_tbl.0 */
 	{
-	.description = "count",
-	.field_bit_size = 64,
+	.description = "encap_udp",
+	.field_bit_size = 32,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
+	},
+	{
+	.description = "encap_tun",
+	.field_bit_size = 0,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff}
 	},
-	/* act_tid: 2, wh_plus, table: int_full_act_record.0 */
+	/* act_tid: 6, wh_plus, table: int_full_act_record.0 */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -1123,9 +4863,11 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	{
 	.description = "encap_ptr",
 	.field_bit_size = 11,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
 	},
 	{
 	.description = "dst_ip_ptr",
@@ -1203,8 +4945,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
-		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
 	},
 	{
 	.description = "pop_vlan",
@@ -1223,14 +4965,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	{
 	.description = "mirror",
 	.field_bit_size = 2,
-	.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr2 = {
-		1}
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "drop",
@@ -1253,7 +4990,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* act_tid: 2, wh_plus, table: ext_full_act_record.0 */
+	/* act_tid: 6, wh_plus, table: ext_full_act_record_vxlan.0 */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -1417,23 +5154,15 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
-		BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
 	},
 	{
 	.description = "pop_vlan",
 	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
-	.field_opr1 = {
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
-		((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
-		(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "meter",
@@ -1445,14 +5174,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	{
 	.description = "mirror",
 	.field_bit_size = 2,
-	.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr2 = {
-		1}
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "drop",
@@ -1461,18 +5185,35 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* act_tid: 2, wh_plus, table: mirror_tbl.wr */
 	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 16,
+	.description = "ecv_tun_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+		ULP_WP_SYM_ECV_TUN_TYPE_VXLAN}
 	},
 	{
-	.description = "enable",
+	.description = "ecv_l4_type",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM}
+	},
+	{
+	.description = "ecv_l3_type",
+	.field_bit_size = 3,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+	},
+	{
+	.description = "ecv_l2_en",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -1481,55 +5222,80 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
 		1}
 	},
 	{
-	.description = "copy",
+	.description = "ecv_vtag_type",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+	},
+	{
+	.description = "ecv_custom_en",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "ign_drop",
+	.description = "ecv_valid",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.description = "reserved",
-	.field_bit_size = 2,
+	.description = "encap_l2_dmac",
+	.field_bit_size = 48,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff}
+	},
+	{
+	.description = "encap_vtag",
+	.field_bit_size = 0,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff}
 	},
 	{
-	.description = "sp_ptr",
-	.field_bit_size = 11,
+	.description = "encap_ip",
+	.field_bit_size = 0,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP_SZ,
+	.field_opr1 = {
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff}
 	},
-	/* act_tid: 2, wh_plus, table: shared_mirror_record.wr */
 	{
-	.description = "rid",
+	.description = "encap_udp",
 	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_FID >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_FID & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff}
 	},
 	{
-	.description = "mirror_id",
-	.field_bit_size = 2,
-	.field_opc = BNXT_ULP_FIELD_OPC_SRC1_PLUS_CONST_POST,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.description = "encap_tun",
+	.field_bit_size = 80,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
 	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff},
-	.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr2 = {
-		(1 >> 8) & 0xff,
-		1 & 0xff}
+		(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
+		BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff}
 	}
 };
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
index 608150dce8..85e4301bb3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Tue Dec  8 14:57:13 2020 */
+/* date: Thu Dec 17 17:35:03 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -22,41 +22,41 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
 		.cond_start_idx = 0,
 		.cond_nums = 0 }
 	},
-	/* class_tid: 2, wh_plus, ingress */
+	/* class_tid: 2, wh_plus, egress */
 	[2] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 6,
+	.num_tbls = 11,
 	.start_tbl_idx = 11,
 	.reject_info = {
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-		.cond_start_idx = 6,
+		.cond_start_idx = 4,
 		.cond_nums = 0 }
 	},
-	/* class_tid: 3, wh_plus, egress */
+	/* class_tid: 3, wh_plus, ingress */
 	[3] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 8,
-	.start_tbl_idx = 17,
+	.start_tbl_idx = 22,
 	.reject_info = {
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-		.cond_start_idx = 6,
+		.cond_start_idx = 8,
 		.cond_nums = 0 }
 	},
 	/* class_tid: 4, wh_plus, egress */
 	[4] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 8,
-	.start_tbl_idx = 25,
+	.num_tbls = 14,
+	.start_tbl_idx = 30,
 	.reject_info = {
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-		.cond_start_idx = 12,
+		.cond_start_idx = 9,
 		.cond_nums = 0 }
 	},
 	/* class_tid: 5, wh_plus, egress */
 	[5] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 7,
-	.start_tbl_idx = 33,
+	.num_tbls = 9,
+	.start_tbl_idx = 44,
 	.reject_info = {
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
 		.cond_start_idx = 14,
@@ -65,39 +65,72 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
 	/* class_tid: 6, wh_plus, egress */
 	[6] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 9,
+	.start_tbl_idx = 53,
+	.reject_info = {
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 }
+	},
+	/* class_tid: 7, wh_plus, egress */
+	[7] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 1,
-	.start_tbl_idx = 40,
+	.start_tbl_idx = 62,
 	.reject_info = {
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 16,
 		.cond_nums = 0 }
 	}
 };
 
 struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
+	{ /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 2,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 0,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 0,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.ident_start_idx = 0,
+	.ident_nums = 1
+	},
 	{ /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 0,
+		.cond_start_idx = 1,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
-	.key_start_idx = 0,
+	.key_start_idx = 1,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
 	.result_start_idx = 0,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
-	.ident_start_idx = 0,
+	.ident_start_idx = 1,
 	.ident_nums = 1
 	},
 	{ /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */
@@ -107,81 +140,86 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 0,
+		.cond_start_idx = 1,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.key_start_idx = 13,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 14,
 	.blob_key_bit_size = 14,
 	.key_bit_size = 14,
 	.key_num_fields = 3,
-	.ident_start_idx = 1,
+	.ident_start_idx = 2,
 	.ident_nums = 3
 	},
-	{ /* class_tid: 1, wh_plus, table: branch.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,
+	{ /* class_tid: 1, wh_plus, table: control.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 4,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 4,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-		.cond_start_idx = 0,
+		.cond_start_idx = 1,
 		.cond_nums = 1 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH
+	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID
 	},
-	{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */
+	{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 2,
+		.cond_true_goto  = 2,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-		.cond_start_idx = 1,
+		.cond_start_idx = 2,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
 	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-	.key_start_idx = 16,
+	.key_start_idx = 17,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
 	.result_start_idx = 13,
 	.result_bit_size = 38,
-	.result_num_fields = 8,
-	.ident_start_idx = 4,
+	.result_num_fields = 17,
+	.ident_start_idx = 5,
 	.ident_nums = 1
 	},
-	{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */
+	{ /* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 2,
+		.cond_start_idx = 3,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
 	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-	.key_start_idx = 59,
+	.key_start_idx = 60,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 21,
+	.result_start_idx = 30,
 	.result_bit_size = 38,
-	.result_num_fields = 8,
-	.ident_start_idx = 5,
+	.result_num_fields = 17,
+	.ident_start_idx = 6,
 	.ident_nums = 1
 	},
 	{ /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */
@@ -191,858 +229,6669 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 2,
+		.cond_start_idx = 3,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.key_start_idx = 102,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 103,
 	.blob_key_bit_size = 14,
 	.key_bit_size = 14,
 	.key_num_fields = 3,
-	.result_start_idx = 29,
+	.result_start_idx = 47,
 	.result_bit_size = 66,
 	.result_num_fields = 5
 	},
-	{ /* class_tid: 1, wh_plus, table: em.ipv4_0 */
+	{ /* class_tid: 1, wh_plus, table: em.ipv4 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-		.cond_start_idx = 2,
+		.cond_start_idx = 3,
 		.cond_nums = 1 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-	.key_start_idx = 105,
+	.key_start_idx = 106,
 	.blob_key_bit_size = 176,
 	.key_bit_size = 176,
 	.key_num_fields = 10,
-	.result_start_idx = 34,
+	.result_start_idx = 52,
 	.result_bit_size = 64,
 	.result_num_fields = 9
 	},
-	{ /* class_tid: 1, wh_plus, table: eem.ipv4_0 */
+	{ /* class_tid: 1, wh_plus, table: eem.ipv4 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
 	.resource_type = TF_MEM_EXTERNAL,
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
 	.execute_info = {
-		.cond_goto = 3,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-		.cond_start_idx = 3,
-		.cond_nums = 1 },
+		.cond_true_goto  = 0,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 4,
+		.cond_nums = 0 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-	.key_start_idx = 115,
+	.key_start_idx = 116,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
-	.key_num_fields = 10,
-	.result_start_idx = 43,
+	.key_num_fields = 11,
+	.result_start_idx = 61,
 	.result_bit_size = 64,
 	.result_num_fields = 9
 	},
-	{ /* class_tid: 1, wh_plus, table: em.ipv6_0 */
+	{ /* class_tid: 1, wh_plus, table: em.ipv6 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 4,
-		.cond_nums = 1 },
+		.cond_nums = 0 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-	.key_start_idx = 125,
+	.key_start_idx = 127,
 	.blob_key_bit_size = 416,
 	.key_bit_size = 416,
 	.key_num_fields = 11,
-	.result_start_idx = 52,
+	.result_start_idx = 70,
 	.result_bit_size = 64,
 	.result_num_fields = 9
 	},
-	{ /* class_tid: 1, wh_plus, table: eem.ipv6_0 */
+	{ /* class_tid: 1, wh_plus, table: eem.ipv6 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
 	.resource_type = TF_MEM_EXTERNAL,
 	.direction = TF_DIR_RX,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
 	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-		.cond_start_idx = 5,
-		.cond_nums = 1 },
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 4,
+		.cond_nums = 0 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-	.key_start_idx = 136,
+	.key_start_idx = 138,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 61,
+	.result_start_idx = 79,
 	.result_bit_size = 64,
 	.result_num_fields = 9
 	},
-	{ /* class_tid: 1, wh_plus, table: branch.last */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,
-	.direction = TF_DIR_RX,
-	.execute_info = {
-		.cond_goto = 0,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 6,
-		.cond_nums = 0 },
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH
-	},
-	{ /* class_tid: 2, wh_plus, table: int_full_act_record.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
-	.direction = TF_DIR_RX,
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 6,
-		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+		.cond_true_goto  = 2,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 4,
+		.cond_nums = 1 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 70,
-	.result_bit_size = 128,
-	.result_num_fields = 26,
-	.encap_num_fields = 0
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 149,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.ident_start_idx = 7,
+	.ident_nums = 1
 	},
 	{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_RX,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 6,
+		.cond_start_idx = 5,
 		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
-	.fdb_operand = BNXT_ULP_RF_IDX_RID,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-	.key_start_idx = 147,
+	.key_start_idx = 150,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 96,
+	.result_start_idx = 88,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
-	.ident_start_idx = 6,
+	.ident_start_idx = 8,
 	.ident_nums = 1
 	},
-	{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */
+	{ /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_RX,
-	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 6,
-		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.key_start_idx = 160,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
-	.result_start_idx = 109,
-	.result_bit_size = 62,
-	.result_num_fields = 4
-	},
-	{ /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
-	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
-	.direction = TF_DIR_RX,
-	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 6,
-		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 113,
-	.result_bit_size = 32,
-	.result_num_fields = 1
-	},
-	{ /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
-	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
-	.direction = TF_DIR_RX,
-	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 6,
-		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 114,
-	.result_bit_size = 32,
-	.result_num_fields = 1
-	},
-	{ /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
-	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
-	.direction = TF_DIR_RX,
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 6,
+		.cond_start_idx = 5,
 		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 115,
-	.result_bit_size = 32,
-	.result_num_fields = 1
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 163,
+	.blob_key_bit_size = 14,
+	.key_bit_size = 14,
+	.key_num_fields = 3,
+	.ident_start_idx = 9,
+	.ident_nums = 3
 	},
-	{ /* class_tid: 3, wh_plus, table: int_full_act_record.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+	{ /* class_tid: 2, wh_plus, table: control.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 6,
-		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 4,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 5,
+		.cond_nums = 1 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 116,
-	.result_bit_size = 128,
-	.result_num_fields = 26,
-	.encap_num_fields = 0
+	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID
 	},
-	{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
+	{ /* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 2,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
 		.cond_start_idx = 6,
 		.cond_nums = 1 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
-	.pri_operand = 0,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-	.key_start_idx = 161,
-	.blob_key_bit_size = 167,
-	.key_bit_size = 167,
-	.key_num_fields = 13,
-	.result_start_idx = 142,
-	.result_bit_size = 64,
-	.result_num_fields = 13,
-	.ident_start_idx = 7,
-	.ident_nums = 0
-	},
-	{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
-	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-		.cond_start_idx = 7,
-		.cond_nums = 1 },
-	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.key_start_idx = 174,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
-	.ident_start_idx = 7,
+	.key_start_idx = 166,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 43,
+	.result_start_idx = 101,
+	.result_bit_size = 38,
+	.result_num_fields = 17,
+	.ident_start_idx = 12,
 	.ident_nums = 1
 	},
-	{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
+	{ /* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
-		.cond_start_idx = 8,
-		.cond_nums = 2 },
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 7,
+		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
 	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-	.key_start_idx = 175,
-	.blob_key_bit_size = 167,
-	.key_bit_size = 167,
-	.key_num_fields = 13,
-	.result_start_idx = 155,
-	.result_bit_size = 64,
-	.result_num_fields = 13,
-	.ident_start_idx = 8,
+	.key_start_idx = 209,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 43,
+	.result_start_idx = 118,
+	.result_bit_size = 38,
+	.result_num_fields = 17,
+	.ident_start_idx = 13,
 	.ident_nums = 1
 	},
-	{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
+	{ /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
-	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
-		.cond_start_idx = 10,
-		.cond_nums = 2 },
-	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.key_start_idx = 188,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
-	.result_start_idx = 168,
-	.result_bit_size = 62,
-	.result_num_fields = 4
-	},
-	{ /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
-	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 12,
+		.cond_start_idx = 7,
 		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 172,
-	.result_bit_size = 32,
-	.result_num_fields = 1
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 252,
+	.blob_key_bit_size = 14,
+	.key_bit_size = 14,
+	.key_num_fields = 3,
+	.result_start_idx = 135,
+	.result_bit_size = 66,
+	.result_num_fields = 5
 	},
-	{ /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
-	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+	{ /* class_tid: 2, wh_plus, table: em.ipv4 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
+	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 12,
-		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 7,
+		.cond_nums = 1 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 173,
-	.result_bit_size = 32,
-	.result_num_fields = 1
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+	.key_start_idx = 255,
+	.blob_key_bit_size = 176,
+	.key_bit_size = 176,
+	.key_num_fields = 10,
+	.result_start_idx = 140,
+	.result_bit_size = 64,
+	.result_num_fields = 9
 	},
-	{ /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
-	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+	{ /* class_tid: 2, wh_plus, table: eem.ipv4 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+	.resource_type = TF_MEM_EXTERNAL,
 	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 12,
+		.cond_start_idx = 8,
 		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 174,
-	.result_bit_size = 32,
-	.result_num_fields = 1
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+	.key_start_idx = 265,
+	.blob_key_bit_size = 448,
+	.key_bit_size = 448,
+	.key_num_fields = 11,
+	.result_start_idx = 149,
+	.result_bit_size = 64,
+	.result_num_fields = 9
 	},
-	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	{ /* class_tid: 2, wh_plus, table: em.ipv6 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
+	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 12,
+		.cond_start_idx = 8,
 		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.key_start_idx = 189,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
-	.ident_start_idx = 9,
-	.ident_nums = 1
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+	.key_start_idx = 276,
+	.blob_key_bit_size = 416,
+	.key_bit_size = 416,
+	.key_num_fields = 11,
+	.result_start_idx = 158,
+	.result_bit_size = 64,
+	.result_num_fields = 9
 	},
-	{ /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	{ /* class_tid: 2, wh_plus, table: eem.ipv6 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+	.resource_type = TF_MEM_EXTERNAL,
 	.direction = TF_DIR_TX,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 12,
+		.cond_start_idx = 8,
 		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 175,
-	.result_bit_size = 0,
-	.result_num_fields = 0,
-	.encap_num_fields = 12
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+	.key_start_idx = 287,
+	.blob_key_bit_size = 448,
+	.key_bit_size = 448,
+	.key_num_fields = 11,
+	.result_start_idx = 167,
+	.result_bit_size = 64,
+	.result_num_fields = 9
 	},
-	{ /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */
+	{ /* class_tid: 3, wh_plus, table: int_full_act_record.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
 	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
 	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
-	.direction = TF_DIR_TX,
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 12,
+		.cond_start_idx = 8,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 187,
+	.result_start_idx = 176,
 	.result_bit_size = 128,
-	.result_num_fields = 26,
-	.encap_num_fields = 0
+	.result_num_fields = 26
 	},
-	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_TX,
-	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-		.cond_start_idx = 12,
-		.cond_nums = 1 },
-	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
-	.fdb_operand = BNXT_ULP_RF_IDX_RID,
-	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
-	.pri_operand = 0,
-	.key_start_idx = 190,
-	.blob_key_bit_size = 167,
-	.key_bit_size = 167,
-	.key_num_fields = 13,
-	.result_start_idx = 213,
-	.result_bit_size = 64,
-	.result_num_fields = 13,
-	.ident_start_idx = 10,
-	.ident_nums = 0
-	},
-	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
+	{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
-	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-		.cond_start_idx = 13,
-		.cond_nums = 1 },
-	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.key_start_idx = 203,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
-	.result_start_idx = 226,
-	.result_bit_size = 62,
-	.result_num_fields = 4
-	},
-	{ /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
-	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 8,
 		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 230,
-	.result_bit_size = 128,
-	.result_num_fields = 26,
-	.encap_num_fields = 0
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 298,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.ident_start_idx = 14,
+	.ident_nums = 0
 	},
-	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	{ /* class_tid: 3, wh_plus, table: control.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
-		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 3,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 8,
+		.cond_nums = 1 },
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
-	.pri_operand = 0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-	.key_start_idx = 204,
-	.blob_key_bit_size = 167,
-	.key_bit_size = 167,
-	.key_num_fields = 13,
-	.result_start_idx = 256,
-	.result_bit_size = 64,
-	.result_num_fields = 13,
-	.ident_start_idx = 10,
-	.ident_nums = 0
+	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID
 	},
-	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+	{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 9,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-	.key_start_idx = 217,
-	.blob_key_bit_size = 167,
-	.key_bit_size = 167,
-	.key_num_fields = 13,
-	.result_start_idx = 269,
-	.result_bit_size = 64,
-	.result_num_fields = 13,
-	.ident_start_idx = 10,
-	.ident_nums = 0
-	},
-	{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_TX,
-	.execute_info = {
-		.cond_goto = 1,
-		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
-		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
-	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
-	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
-	.pri_operand = 0,
-	.key_start_idx = 230,
+	.key_start_idx = 299,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 282,
+	.result_start_idx = 202,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
-	.ident_start_idx = 10,
+	.ident_start_idx = 14,
 	.ident_nums = 1
 	},
-	{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
+	{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
+	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 9,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
-	.fdb_operand = BNXT_ULP_RF_IDX_RID,
-	.key_start_idx = 243,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 312,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 295,
+	.result_start_idx = 215,
 	.result_bit_size = 62,
 	.result_num_fields = 4
 	},
-	{ /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */
+	{ /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
 	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
-	.direction = TF_DIR_TX,
+	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 9,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
+	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 299,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 219,
 	.result_bit_size = 32,
 	.result_num_fields = 1
 	},
-	{ /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */
+	{ /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
-	.direction = TF_DIR_TX,
+	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 9,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
+	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 300,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 220,
 	.result_bit_size = 32,
 	.result_num_fields = 1
 	},
-	{ /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */
+	{ /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
-	.direction = TF_DIR_TX,
+	.direction = TF_DIR_RX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 9,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
-	.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
+	.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.result_start_idx = 301,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 221,
 	.result_bit_size = 32,
 	.result_num_fields = 1
 	},
-	{ /* class_tid: 5, wh_plus, table: int_full_act_record.ing */
+	{ /* class_tid: 4, wh_plus, table: control.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 6,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 9,
+		.cond_nums = 1 },
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+	},
+	{ /* class_tid: 4, wh_plus, table: int_full_act_record.vfr */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
 	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
 	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
-	.direction = TF_DIR_RX,
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 1,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 10,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
-	.result_start_idx = 302,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+	.result_start_idx = 222,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0
 	},
-	{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */
+	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 10,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 313,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.ident_start_idx = 15,
+	.ident_nums = 0
+	},
+	{ /* class_tid: 4, wh_plus, table: control.1 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 10,
+		.cond_nums = 1 },
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID
+	},
+	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
-	.direction = TF_DIR_RX,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-		.cond_start_idx = 14,
+		.cond_start_idx = 11,
 		.cond_nums = 0 },
 	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
 	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
 	.pri_operand = 0,
+	.key_start_idx = 314,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 248,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.ident_start_idx = 15,
+	.ident_nums = 0
+	},
+	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 11,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 327,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.result_start_idx = 261,
+	.result_bit_size = 62,
+	.result_num_fields = 4
+	},
+	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 11,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 328,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.ident_start_idx = 15,
+	.ident_nums = 0
+	},
+	{ /* class_tid: 4, wh_plus, table: control.2 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 3,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 11,
+		.cond_nums = 1 },
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID
+	},
+	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 12,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-	.key_start_idx = 244,
+	.key_start_idx = 329,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 328,
+	.result_start_idx = 265,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
-	.ident_start_idx = 11,
-	.ident_nums = 0
+	.ident_start_idx = 15,
+	.ident_nums = 1
+	},
+	{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+		.cond_start_idx = 12,
+		.cond_nums = 2 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 342,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.result_start_idx = 278,
+	.result_bit_size = 62,
+	.result_num_fields = 4
 	},
-	{ /* class_tid: 6, wh_plus, table: int_full_act_record.0 */
+	{ /* class_tid: 4, wh_plus, table: int_full_act_record.0 */
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
 	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
 	.execute_info = {
-		.cond_goto = 0,
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
 		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
 		.cond_start_idx = 14,
 		.cond_nums = 0 },
-	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
-	.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
 	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-	.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-	.result_start_idx = 341,
+	.result_start_idx = 282,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0
-	}
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
-	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
-	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
-	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+	{ /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 14,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 308,
+	.result_bit_size = 32,
+	.result_num_fields = 1
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+	{ /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 14,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 309,
+	.result_bit_size = 32,
+	.result_num_fields = 1
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
-	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+	{ /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 14,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+	.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 310,
+	.result_bit_size = 32,
+	.result_num_fields = 1
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
-	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+	{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 14,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 343,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.ident_start_idx = 16,
+	.ident_nums = 0
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
-	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+	{ /* class_tid: 5, wh_plus, table: control.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 3,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 14,
+		.cond_nums = 1 },
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
-	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+	{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
+	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
+	.pri_operand = 0,
+	.key_start_idx = 344,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 311,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.ident_start_idx = 16,
+	.ident_nums = 0
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
-	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 357,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.result_start_idx = 324,
+	.result_bit_size = 62,
+	.result_num_fields = 4
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
-	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+	{ /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+	.result_start_idx = 328,
+	.result_bit_size = 0,
+	.result_num_fields = 0,
+	.encap_num_fields = 12
 	},
-	{
-	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
-	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	{ /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+	.result_start_idx = 340,
+	.result_bit_size = 128,
+	.result_num_fields = 26
+	},
+	{ /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+	.result_start_idx = 366,
+	.result_bit_size = 128,
+	.result_num_fields = 26
+	},
+	{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
+	.pri_operand = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+	.key_start_idx = 358,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 392,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.ident_start_idx = 16,
+	.ident_nums = 0
+	},
+	{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
+	.pri_operand = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+	.key_start_idx = 371,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 405,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.ident_start_idx = 16,
+	.ident_nums = 0
+	},
+	{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 15,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 384,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.ident_start_idx = 16,
+	.ident_nums = 0
+	},
+	{ /* class_tid: 6, wh_plus, table: control.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 3,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+		.cond_start_idx = 15,
+		.cond_nums = 1 },
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID
+	},
+	{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+	.fdb_operand = BNXT_ULP_RF_IDX_RID,
+	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
+	.pri_operand = 0,
+	.key_start_idx = 385,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 418,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.ident_start_idx = 16,
+	.ident_nums = 1
+	},
+	{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.key_start_idx = 398,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.result_start_idx = 431,
+	.result_bit_size = 62,
+	.result_num_fields = 4
+	},
+	{ /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+	.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 435,
+	.result_bit_size = 32,
+	.result_num_fields = 1
+	},
+	{ /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+	.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 436,
+	.result_bit_size = 32,
+	.result_num_fields = 1
+	},
+	{ /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
+	.tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.result_start_idx = 437,
+	.result_bit_size = 32,
+	.result_num_fields = 1
+	},
+	{ /* class_tid: 6, wh_plus, table: int_full_act_record.ing */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 1,
+		.cond_false_goto = 1,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+	.result_start_idx = 438,
+	.result_bit_size = 128,
+	.result_num_fields = 26,
+	.encap_num_fields = 0
+	},
+	{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+	.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+	.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
+	.pri_operand = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+	.key_start_idx = 399,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 464,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.ident_start_idx = 17,
+	.ident_nums = 0
+	},
+	{ /* class_tid: 7, wh_plus, table: int_full_act_record.0 */
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+	.direction = TF_DIR_TX,
+	.execute_info = {
+		.cond_true_goto  = 0,
+		.cond_false_goto = 0,
+		.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+		.cond_start_idx = 16,
+		.cond_nums = 0 },
+	.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+	.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+	.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+	.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+	.result_start_idx = 477,
+	.result_bit_size = 128,
+	.result_num_fields = 26,
+	.encap_num_fields = 0
+	}
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
+	/* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+	.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
+	},
+	/* cond_execute: class_tid: 1, control.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	},
+	/* cond_execute: class_tid: 1, profile_tcam.ipv4 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+	},
+	/* cond_execute: class_tid: 1, em.ipv4 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+	},
+	/* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+	.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC
+	},
+	/* cond_execute: class_tid: 2, control.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	},
+	/* cond_execute: class_tid: 2, profile_tcam.ipv4 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+	},
+	/* cond_execute: class_tid: 2, em.ipv4 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+	},
+	/* cond_execute: class_tid: 3, control.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	},
+	/* cond_execute: class_tid: 4, control.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+	},
+	/* cond_execute: class_tid: 4, control.1 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	},
+	/* cond_execute: class_tid: 4, control.2 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	},
+	/* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.wr */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
+	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
+	},
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	},
+	/* cond_execute: class_tid: 5, control.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	},
+	/* cond_execute: class_tid: 6, control.0 */
+	{
+	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	}
+};
+
+struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
+	/* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */
+	{
+	.field_info_mask = {
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+		},
+	.field_info_spec = {
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
+	{
+	.field_info_mask = {
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "mac0_addr",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+		},
+	.field_info_spec = {
+		.description = "mac0_addr",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+		},
+	.field_info_spec = {
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "sparif",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "sparif",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "mac1_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "mac1_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "key_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "key_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */
+	{
+	.field_info_mask = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,
+		.field_cond_opr = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "hdr_sig_id",
+		.field_bit_size = 5,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "hdr_sig_id",
+		.field_bit_size = 5,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_type",
+		.field_bit_size = 4,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,
+		.field_cond_opr = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+		.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_type",
+		.field_bit_size = 4,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L4_HDR_TYPE_TCP},
+		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr2 = {
+			ULP_WP_SYM_L4_HDR_TYPE_UDP}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_error",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_valid",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_valid",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L3_HDR_VALID_YES}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_vtag_present",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L2_HDR_VALID_YES}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_flags",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_flags",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_err",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_err",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "hrec_next",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "hrec_next",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "reserved",
+		.field_bit_size = 9,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "reserved",
+		.field_bit_size = 9,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,
+		.field_cond_opr = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "agg_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "agg_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "pkt_type_0",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "pkt_type_0",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "pkt_type_1",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "pkt_type_1",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_type",
+		.field_bit_size = 4,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,
+		.field_cond_opr = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+		.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_type",
+		.field_bit_size = 4,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L4_HDR_TYPE_TCP},
+		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr2 = {
+			ULP_WP_SYM_L4_HDR_TYPE_UDP}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_error",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_valid",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_valid",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L3_HDR_TYPE_IPV6}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L3_HDR_VALID_YES}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_vtag_present",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L2_HDR_VALID_YES}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_flags",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_flags",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_err",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_err",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "hrec_next",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "hrec_next",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "reserved",
+		.field_bit_size = 9,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "reserved",
+		.field_bit_size = 9,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,
+		.field_cond_opr = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "agg_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "agg_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "pkt_type_0",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "pkt_type_0",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "pkt_type_1",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "pkt_type_1",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */
+	{
+	.field_info_mask = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,
+		.field_cond_opr = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "hdr_sig_id",
+		.field_bit_size = 5,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "hdr_sig_id",
+		.field_bit_size = 5,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: em.ipv4 */
+	{
+	.field_info_mask = {
+		.description = "spare",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "spare",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv4.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_ipv4.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv4.dst",
+		.field_bit_size = 32,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv4.dst",
+		.field_bit_size = 32,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv4.src",
+		.field_bit_size = 32,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv4.src",
+		.field_bit_size = 32,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: eem.ipv4 */
+	{
+	.field_info_mask = {
+		.description = "spare",
+		.field_bit_size = 35,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "spare",
+		.field_bit_size = 35,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: em.ipv6 */
+	{
+	.field_info_mask = {
+		.description = "spare",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "spare",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+		}
+	},
+	/* class_tid: 1, wh_plus, table: eem.ipv6 */
+	{
+	.field_info_mask = {
+		.description = "spare",
+		.field_bit_size = 35,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "spare",
+		.field_bit_size = 35,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */
+	{
+	.field_info_mask = {
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+		},
+	.field_info_spec = {
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
+	{
+	.field_info_mask = {
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "mac0_addr",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		},
+	.field_info_spec = {
+		.description = "mac0_addr",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+		},
+	.field_info_spec = {
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "sparif",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "sparif",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "mac1_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "mac1_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "key_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "key_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */
+	{
+	.field_info_mask = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,
+		.field_cond_opr = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "hdr_sig_id",
+		.field_bit_size = 5,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "hdr_sig_id",
+		.field_bit_size = 5,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_type",
+		.field_bit_size = 4,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,
+		.field_cond_opr = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+		.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_type",
+		.field_bit_size = 4,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L4_HDR_TYPE_TCP},
+		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr2 = {
+			ULP_WP_SYM_L4_HDR_TYPE_UDP}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_error",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_valid",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_valid",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L3_HDR_VALID_YES}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_vtag_present",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L2_HDR_VALID_YES}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_flags",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_flags",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_err",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_err",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "hrec_next",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "hrec_next",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "reserved",
+		.field_bit_size = 9,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "reserved",
+		.field_bit_size = 9,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,
+		.field_cond_opr = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "agg_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "agg_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "pkt_type_0",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "pkt_type_0",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "pkt_type_1",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "pkt_type_1",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_type",
+		.field_bit_size = 4,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,
+		.field_cond_opr = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+		.field_src2 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_type",
+		.field_bit_size = 4,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L4_HDR_TYPE_TCP},
+		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr2 = {
+			ULP_WP_SYM_L4_HDR_TYPE_UDP}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_error",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l4_hdr_valid",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		},
+	.field_info_spec = {
+		.description = "l4_hdr_valid",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_L4 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L3_HDR_TYPE_IPV6}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L3_HDR_VALID_YES}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_vtag_present",
+		.field_bit_size = 1,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_L2_HDR_VALID_YES}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_flags",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_flags",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_err",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_err",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tun_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tun_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_is_udp_tcp",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl4_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl4_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_ipv6_cmp_dst",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_ipv6_cmp_src",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_isIP",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl3_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_two_vtags",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_vtag_present",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_uc_mc_bc",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_hdr_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "tl2_hdr_valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "hrec_next",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "hrec_next",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "reserved",
+		.field_bit_size = 9,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "reserved",
+		.field_bit_size = 9,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,
+		.field_cond_opr = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "agg_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "agg_error",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "pkt_type_0",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "pkt_type_0",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "pkt_type_1",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "pkt_type_1",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */
+	{
+	.field_info_mask = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "recycle_cnt",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "prof_func_id",
+		.field_bit_size = 7,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_FIELD_BIT,
+		.field_cond_opr = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "hdr_sig_id",
+		.field_bit_size = 5,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "hdr_sig_id",
+		.field_bit_size = 5,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: em.ipv4 */
+	{
+	.field_info_mask = {
+		.description = "spare",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "spare",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv4.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_ipv4.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv4.dst",
+		.field_bit_size = 32,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv4.dst",
+		.field_bit_size = 32,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv4.src",
+		.field_bit_size = 32,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv4.src",
+		.field_bit_size = 32,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: eem.ipv4 */
+	{
+	.field_info_mask = {
+		.description = "spare",
+		.field_bit_size = 35,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "spare",
+		.field_bit_size = 35,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "em_profile_id",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+		}
+	},
+	/* class_tid: 2, wh_plus, table: em.ipv6 */
+	{
+	.field_info_mask = {
+		.description = "spare",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "spare",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "local_cos",
+		.field_bit_size = 3,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
+		},
+	.field_info_spec = {
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
 	},
 	{
-	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
-	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+	.field_info_mask = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		},
+	.field_info_spec = {
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+		}
 	},
 	{
-	.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
-	.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
-	}
-};
-
-struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
-	/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
-	{
 	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
 		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
 		},
 	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
 		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1050,7 +6899,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "mac0_addr",
+		.description = "o_eth.dmac",
 		.field_bit_size = 48,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
@@ -1059,7 +6908,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
 		},
 	.field_info_spec = {
-		.description = "mac0_addr",
+		.description = "o_eth.dmac",
 		.field_bit_size = 48,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
@@ -1070,51 +6919,57 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+			0xff,
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
+		.description = "em_profile_id",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "em_profile_id",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
 		}
 	},
+	/* class_tid: 2, wh_plus, table: eem.ipv6 */
 	{
 	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
+		.description = "spare",
+		.field_bit_size = 35,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
+		.description = "spare",
+		.field_bit_size = 35,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1122,15 +6977,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
+		.description = "local_cos",
+		.field_bit_size = 3,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
+		.description = "local_cos",
+		.field_bit_size = 3,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1138,51 +6993,83 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.description = "o_l4.dport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
+			0xff,
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.description = "o_l4.sport",
+		.field_bit_size = 16,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+		.field_cond_opr = {
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
 		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
+			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr2 = {
+			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
+		.description = "o_ipv6.ip_proto",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1190,33 +7077,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "o_ipv6.dst",
+		.field_bit_size = 128,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
 		.field_opr1 = {
-			0xff}
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
 		},
 	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
+		.description = "o_ipv6.src",
+		.field_bit_size = 128,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.field_opr1 = {
+			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "o_eth.smac",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1224,47 +7133,49 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
 		.field_opr1 = {
-			0xff}
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
 		},
 	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "o_eth.dmac",
+		.field_bit_size = 48,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
 		.field_opr1 = {
-			1}
+			(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+			BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
 		}
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */
 	{
 	.field_info_mask = {
-		.description = "recycle_cnt",
-		.field_bit_size = 2,
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
+			0xff,
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "recycle_cnt",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "l2_cntxt_id",
+		.field_bit_size = 10,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_opr1 = {
+			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "prof_func_id",
-		.field_bit_size = 7,
+		.description = "em_profile_id",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1272,19 +7183,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "prof_func_id",
-		.field_bit_size = 7,
+		.description = "em_profile_id",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 		.field_opr1 = {
-			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
 		}
 	},
+	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */
 	{
 	.field_info_mask = {
-		.description = "hdr_sig_id",
-		.field_bit_size = 5,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1292,27 +7204,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "hdr_sig_id",
-		.field_bit_size = 5,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+			(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
 		}
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */
+	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
 	{
 	.field_info_mask = {
-		.description = "l4_hdr_is_udp_tcp",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l4_hdr_is_udp_tcp",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1320,48 +7232,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l4_hdr_type",
-		.field_bit_size = 4,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l4_hdr_type",
-		.field_bit_size = 4,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_L4_HDR_TYPE_TCP},
-		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr2 = {
-			ULP_WP_SYM_L4_HDR_TYPE_UDP}
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "l4_hdr_error",
-		.field_bit_size = 1,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l4_hdr_error",
-		.field_bit_size = 1,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1369,8 +7264,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l4_hdr_valid",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1378,26 +7273,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l4_hdr_valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			ULP_WP_SYM_L4_HDR_VALID_YES}
+			(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_ipv6_cmp_dst",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_ipv6_cmp_dst",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1405,15 +7300,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_ipv6_cmp_src",
-		.field_bit_size = 1,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_ipv6_cmp_src",
-		.field_bit_size = 1,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1421,15 +7316,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_hdr_isIP",
-		.field_bit_size = 1,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_hdr_isIP",
-		.field_bit_size = 1,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1437,17 +7332,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_hdr_type",
-		.field_bit_size = 4,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_hdr_type",
-		.field_bit_size = 4,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1455,17 +7348,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_hdr_error",
-		.field_bit_size = 1,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_hdr_error",
-		.field_bit_size = 1,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1473,37 +7364,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_hdr_valid",
-		.field_bit_size = 1,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_hdr_valid",
-		.field_bit_size = 1,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_L3_HDR_VALID_YES}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_two_vtags",
-		.field_bit_size = 1,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l2_two_vtags",
-		.field_bit_size = 1,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1511,27 +7396,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_vtag_present",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "l2_vtag_present",
-		.field_bit_size = 1,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
-		}
-	},
-	{
-	.field_info_mask = {
-		.description = "l2_uc_mc_bc",
+		.description = "key_type",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -1540,7 +7405,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l2_uc_mc_bc",
+		.description = "key_type",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -1549,8 +7414,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_hdr_type",
-		.field_bit_size = 2,
+		.description = "valid",
+		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1558,17 +7423,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l2_hdr_type",
-		.field_bit_size = 2,
+		.description = "valid",
+		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
 		}
 	},
+	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
 	{
 	.field_info_mask = {
-		.description = "l2_hdr_error",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1576,17 +7444,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l2_hdr_error",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
 		}
 	},
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_vfr */
 	{
 	.field_info_mask = {
-		.description = "l2_hdr_valid",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1594,26 +7465,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l2_hdr_valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			ULP_WP_SYM_L2_HDR_VALID_YES}
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_flags",
-		.field_bit_size = 3,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_flags",
-		.field_bit_size = 3,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1621,15 +7493,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1637,15 +7509,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_err",
-		.field_bit_size = 1,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_err",
-		.field_bit_size = 1,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1653,8 +7525,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_valid",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1662,24 +7534,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "tl4_hdr_is_udp_tcp",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl4_hdr_is_udp_tcp",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1687,15 +7561,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl4_hdr_type",
-		.field_bit_size = 4,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl4_hdr_type",
-		.field_bit_size = 4,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1703,15 +7577,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl4_hdr_error",
-		.field_bit_size = 1,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl4_hdr_error",
-		.field_bit_size = 1,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1719,17 +7593,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl4_hdr_valid",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl4_hdr_valid",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1737,15 +7609,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_ipv6_cmp_dst",
-		.field_bit_size = 1,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl3_ipv6_cmp_dst",
-		.field_bit_size = 1,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1753,15 +7625,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_ipv6_cmp_src",
-		.field_bit_size = 1,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl3_ipv6_cmp_src",
-		.field_bit_size = 1,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1769,15 +7641,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_hdr_isIP",
-		.field_bit_size = 1,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl3_hdr_isIP",
-		.field_bit_size = 1,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1785,15 +7657,17 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_hdr_type",
-		.field_bit_size = 4,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl3_hdr_type",
-		.field_bit_size = 4,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1801,24 +7675,29 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_hdr_error",
+		.description = "valid",
 		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl3_hdr_error",
+		.description = "valid",
 		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
 		}
 	},
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */
 	{
 	.field_info_mask = {
-		.description = "tl3_hdr_valid",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1826,40 +7705,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl3_hdr_valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */
 	{
 	.field_info_mask = {
-		.description = "tl2_two_vtags",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl2_two_vtags",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */
 	{
 	.field_info_mask = {
-		.description = "tl2_vtag_present",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl2_vtag_present",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1867,15 +7754,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_uc_mc_bc",
-		.field_bit_size = 2,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl2_uc_mc_bc",
-		.field_bit_size = 2,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1883,15 +7770,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_hdr_type",
-		.field_bit_size = 2,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl2_hdr_type",
-		.field_bit_size = 2,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1899,8 +7786,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_hdr_valid",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -1908,24 +7795,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl2_hdr_valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "hrec_next",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "hrec_next",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1933,15 +7822,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "reserved",
-		.field_bit_size = 9,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "reserved",
-		.field_bit_size = 9,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1949,35 +7838,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "prof_func_id",
-		.field_bit_size = 7,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "prof_func_id",
-		.field_bit_size = 7,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "agg_error",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "agg_error",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -1985,16 +7870,30 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "recycle_cnt",
+		.description = "l2_num_vtags",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "recycle_cnt",
+		.description = "tl2_num_vtags",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2003,15 +7902,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "pkt_type_0",
-		.field_bit_size = 2,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "pkt_type_0",
-		.field_bit_size = 2,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2019,7 +7918,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "pkt_type_1",
+		.description = "key_type",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2028,7 +7927,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "pkt_type_1",
+		.description = "key_type",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2055,27 +7954,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			1}
 		}
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */
-	{
-	.field_info_mask = {
-		.description = "l4_hdr_is_udp_tcp",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l4_hdr_is_udp_tcp",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
-	},
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */
 	{
 	.field_info_mask = {
-		.description = "l4_hdr_type",
-		.field_bit_size = 4,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -2083,48 +7966,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l4_hdr_type",
-		.field_bit_size = 4,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_L4_HDR_TYPE_TCP},
-		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr2 = {
-			ULP_WP_SYM_L4_HDR_TYPE_UDP}
-		}
-	},
-	{
-	.field_info_mask = {
-		.description = "l4_hdr_error",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "l4_hdr_error",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */
 	{
 	.field_info_mask = {
-		.description = "l4_hdr_valid",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -2132,26 +7987,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l4_hdr_valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			ULP_WP_SYM_L4_HDR_VALID_YES}
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
 	{
 	.field_info_mask = {
-		.description = "l3_ipv6_cmp_dst",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_ipv6_cmp_dst",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2159,15 +8015,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_ipv6_cmp_src",
-		.field_bit_size = 1,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_ipv6_cmp_src",
-		.field_bit_size = 1,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2175,15 +8031,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_hdr_isIP",
-		.field_bit_size = 1,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_hdr_isIP",
-		.field_bit_size = 1,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2191,8 +8047,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_hdr_type",
-		.field_bit_size = 4,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -2200,28 +8056,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l3_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			ULP_WP_SYM_L3_HDR_TYPE_IPV6}
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_hdr_error",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_hdr_error",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2229,37 +8083,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l3_hdr_valid",
-		.field_bit_size = 1,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l3_hdr_valid",
-		.field_bit_size = 1,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_L3_HDR_VALID_YES}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_two_vtags",
-		.field_bit_size = 1,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l2_two_vtags",
-		.field_bit_size = 1,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2267,36 +8115,30 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_vtag_present",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l2_vtag_present",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_uc_mc_bc",
+		.description = "l2_num_vtags",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l2_uc_mc_bc",
+		.description = "l2_num_vtags",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2305,16 +8147,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_hdr_type",
+		.description = "tl2_num_vtags",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l2_hdr_type",
+		.description = "tl2_num_vtags",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2323,17 +8163,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_hdr_error",
-		.field_bit_size = 1,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l2_hdr_error",
-		.field_bit_size = 1,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2341,8 +8179,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_hdr_valid",
-		.field_bit_size = 1,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -2350,58 +8188,66 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l2_hdr_valid",
-		.field_bit_size = 1,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_L2_HDR_VALID_YES}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_flags",
-		.field_bit_size = 3,
+		.description = "valid",
+		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_flags",
-		.field_bit_size = 3,
+		.description = "valid",
+		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
 		}
 	},
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_err",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_err",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2409,33 +8255,36 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tun_hdr_valid",
-		.field_bit_size = 1,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
+			0xff,
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "tun_hdr_valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "tl4_hdr_is_udp_tcp",
-		.field_bit_size = 1,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl4_hdr_is_udp_tcp",
-		.field_bit_size = 1,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2443,31 +8292,35 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl4_hdr_type",
-		.field_bit_size = 4,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl4_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "tl4_hdr_error",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl4_hdr_error",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2475,17 +8328,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl4_hdr_valid",
-		.field_bit_size = 1,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl4_hdr_valid",
-		.field_bit_size = 1,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2493,15 +8344,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_ipv6_cmp_dst",
-		.field_bit_size = 1,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl3_ipv6_cmp_dst",
-		.field_bit_size = 1,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2509,15 +8360,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_ipv6_cmp_src",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl3_ipv6_cmp_src",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2525,31 +8376,35 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_hdr_isIP",
-		.field_bit_size = 1,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl3_hdr_isIP",
-		.field_bit_size = 1,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			2}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_hdr_type",
-		.field_bit_size = 4,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl3_hdr_type",
-		.field_bit_size = 4,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2557,24 +8412,28 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_hdr_error",
-		.field_bit_size = 1,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl3_hdr_error",
-		.field_bit_size = 1,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_TUN_HDR_TYPE_NONE}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "tl3_hdr_valid",
-		.field_bit_size = 1,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -2582,8 +8441,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl3_hdr_valid",
-		.field_bit_size = 1,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2591,47 +8450,57 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_two_vtags",
+		.description = "valid",
 		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl2_two_vtags",
+		.description = "valid",
 		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
 		}
 	},
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
 	{
 	.field_info_mask = {
-		.description = "tl2_vtag_present",
-		.field_bit_size = 1,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff,
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl2_vtag_present",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_uc_mc_bc",
-		.field_bit_size = 2,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl2_uc_mc_bc",
-		.field_bit_size = 2,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2639,15 +8508,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_hdr_type",
-		.field_bit_size = 2,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "tl2_hdr_type",
-		.field_bit_size = 2,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2655,8 +8524,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "tl2_hdr_valid",
-		.field_bit_size = 1,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -2664,24 +8533,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "tl2_hdr_valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "hrec_next",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "hrec_next",
-		.field_bit_size = 1,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2689,15 +8560,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "reserved",
-		.field_bit_size = 9,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "reserved",
-		.field_bit_size = 9,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2705,35 +8576,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "prof_func_id",
-		.field_bit_size = 7,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "prof_func_id",
-		.field_bit_size = 7,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-			BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "agg_error",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "agg_error",
-		.field_bit_size = 1,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2741,7 +8608,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "recycle_cnt",
+		.description = "l2_num_vtags",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2750,7 +8617,25 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "recycle_cnt",
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			1}
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "tl2_num_vtags",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2759,23 +8644,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "pkt_type_0",
-		.field_bit_size = 2,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			0xff}
 		},
 	.field_info_spec = {
-		.description = "pkt_type_0",
-		.field_bit_size = 2,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_opr1 = {
+			ULP_WP_SYM_TUN_HDR_TYPE_NONE}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "pkt_type_1",
+		.description = "key_type",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2784,7 +8673,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "pkt_type_1",
+		.description = "key_type",
 		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -2811,11 +8700,11 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			1}
 		}
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */
+	/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.rd_egr */
 	{
 	.field_info_mask = {
-		.description = "recycle_cnt",
-		.field_bit_size = 2,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -2823,8 +8712,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "recycle_cnt",
-		.field_bit_size = 2,
+		.description = "svif",
+		.field_bit_size = 8,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+		.field_opr1 = {
+			(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
+		}
+	},
+	/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */
+	{
+	.field_info_mask = {
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2832,28 +8740,40 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "prof_func_id",
-		.field_bit_size = 7,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "prof_func_id",
-		.field_bit_size = 7,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-			BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "hdr_sig_id",
-		.field_bit_size = 5,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		},
+	.field_info_spec = {
+		.description = "mac0_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		}
+	},
+	{
+	.field_info_mask = {
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -2861,27 +8781,26 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "hdr_sig_id",
-		.field_bit_size = 5,
+		.description = "svif",
+		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
+			(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
 		}
 	},
-	/* class_tid: 1, wh_plus, table: em.ipv4_0 */
 	{
 	.field_info_mask = {
-		.description = "spare",
-		.field_bit_size = 3,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "spare",
-		.field_bit_size = 3,
+		.description = "sparif",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2889,17 +8808,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "local_cos",
-		.field_bit_size = 3,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "local_cos",
-		.field_bit_size = 3,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -2907,161 +8824,97 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "o_l4.dport",
-		.field_bit_size = 16,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_l4.dport",
-		.field_bit_size = 16,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
-		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr2 = {
-			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_l4.sport",
-		.field_bit_size = 16,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_l4.sport",
-		.field_bit_size = 16,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
-		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr2 = {
-			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		.description = "mac1_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_ipv4.ip_proto",
-		.field_bit_size = 8,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_ipv4.ip_proto",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_IP_PROTO_TCP},
-		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr2 = {
-			ULP_WP_SYM_IP_PROTO_UDP}
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_ipv4.dst",
-		.field_bit_size = 32,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_ipv4.dst",
-		.field_bit_size = 32,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_ipv4.src",
-		.field_bit_size = 32,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_ipv4.src",
-		.field_bit_size = 32,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_eth.smac",
-		.field_bit_size = 48,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff,
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "o_eth.smac",
-		.field_bit_size = 48,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -3069,28 +8922,28 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_cntxt_id",
-		.field_bit_size = 10,
+		.description = "valid",
+		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
-			0xff,
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "l2_cntxt_id",
-		.field_bit_size = 10,
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+			1}
 		}
 	},
+	/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
 	{
 	.field_info_mask = {
-		.description = "em_profile_id",
+		.description = "svif",
 		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -3099,27 +8952,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "em_profile_id",
+		.description = "svif",
 		.field_bit_size = 8,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+			(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
 		}
 	},
-	/* class_tid: 1, wh_plus, table: eem.ipv4_0 */
+	/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */
 	{
 	.field_info_mask = {
-		.description = "spare",
-		.field_bit_size = 275,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "spare",
-		.field_bit_size = 275,
+		.description = "l2_ivlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -3127,17 +8980,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "local_cos",
-		.field_bit_size = 3,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "local_cos",
-		.field_bit_size = 3,
+		.description = "l2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -3145,75 +8996,23 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "o_l4.dport",
-		.field_bit_size = 16,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_l4.dport",
-		.field_bit_size = 16,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
-		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr2 = {
-			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
-		}
-	},
-	{
-	.field_info_mask = {
-		.description = "o_l4.sport",
-		.field_bit_size = 16,
+		.description = "mac0_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_l4.sport",
-		.field_bit_size = 16,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
-		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr2 = {
-			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_ipv4.ip_proto",
+		.description = "svif",
 		.field_bit_size = 8,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -3222,84 +9021,58 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "o_ipv4.ip_proto",
+		.description = "svif",
 		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 		.field_opr1 = {
-			ULP_WP_SYM_IP_PROTO_TCP},
-		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr2 = {
-			ULP_WP_SYM_IP_PROTO_UDP}
+			(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+			BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_ipv4.dst",
-		.field_bit_size = 32,
+		.description = "sparif",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_ipv4.dst",
-		.field_bit_size = 32,
+		.description = "sparif",
+		.field_bit_size = 4,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_ipv4.src",
-		.field_bit_size = 32,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_ipv4.src",
-		.field_bit_size = 32,
+		.description = "tl2_ivlan_vid",
+		.field_bit_size = 12,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_eth.smac",
-		.field_bit_size = 48,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "o_eth.smac",
-		.field_bit_size = 48,
+		.description = "tl2_ovlan_vid",
+		.field_bit_size = 12,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -3307,57 +9080,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "l2_cntxt_id",
-		.field_bit_size = 10,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "l2_cntxt_id",
-		.field_bit_size = 10,
+		.description = "mac1_addr",
+		.field_bit_size = 48,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "em_profile_id",
-		.field_bit_size = 8,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "em_profile_id",
-		.field_bit_size = 8,
+		.description = "l2_num_vtags",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
-	/* class_tid: 1, wh_plus, table: em.ipv6_0 */
 	{
 	.field_info_mask = {
-		.description = "spare",
-		.field_bit_size = 3,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "spare",
-		.field_bit_size = 3,
+		.description = "tl2_num_vtags",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -3365,17 +9128,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "local_cos",
-		.field_bit_size = 3,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		},
 	.field_info_spec = {
-		.description = "local_cos",
-		.field_bit_size = 3,
+		.description = "tun_hdr_type",
+		.field_bit_size = 4,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
@@ -3383,2477 +9144,1474 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
 	},
 	{
 	.field_info_mask = {
-		.description = "o_l4.dport",
-		.field_bit_size = 16,
+		.description = "key_type",
+		.field_bit_size = 2,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
-			0xff,
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "o_l4.dport",
-		.field_bit_size = 16,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
-		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr2 = {
-			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
+		.description = "key_type",
+		.field_bit_size = 2,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 		}
 	},
 	{
 	.field_info_mask = {
-		.description = "o_l4.sport",
-		.field_bit_size = 16,
+		.description = "valid",
+		.field_bit_size = 1,
 		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
-			0xff,
 			0xff}
 		},
 	.field_info_spec = {
-		.description = "o_l4.sport",
-		.field_bit_size = 16,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
+		.description = "valid",
+		.field_bit_size = 1,
+		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
-		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr2 = {
-			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
+			1}
 		}
+	}
+};
+
+struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
+	/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
+	{
+	.description = "l2_cntxt_id",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+	},
+	{
+	.description = "prof_func_id",
+	.field_bit_size = 7,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+	},
+	{
+	.description = "l2_byp_lkup_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "parif",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+	},
+	{
+	.description = "allowed_pri",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "default_pri",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "allowed_tpid",
+	.field_bit_size = 6,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "default_tpid",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "bd_act_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "sp_rec_ptr",
+	.field_bit_size = 16,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "byp_sp_lkup",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "pri_anti_spoof_ctl",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tpid_anti_spoof_ctl",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	/* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */
+	{
+	.description = "wc_key_id",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "wc_profile_id",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "wc_search_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "em_key_mask.0",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
+	},
+	{
+	.description = "em_key_mask.1",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+	},
+	{
+	.description = "em_key_mask.2",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
+	},
+	{
+	.description = "em_key_mask.3",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
+	},
+	{
+	.description = "em_key_mask.4",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "em_key_mask.5",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff}
+	},
+	{
+	.description = "em_key_mask.6",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff}
+	},
+	{
+	.description = "em_key_mask.7",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "em_key_mask.8",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "em_key_mask.9",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "em_key_id",
+	.field_bit_size = 5,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		3}
+	},
+	{
+	.description = "em_profile_id",
+	.field_bit_size = 8,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "o_ipv6.ip_proto",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_ipv6.ip_proto",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_IP_PROTO_TCP},
-		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr2 = {
-			ULP_WP_SYM_IP_PROTO_UDP}
-		}
+	.description = "em_search_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.field_info_mask = {
-		.description = "o_ipv6.dst",
-		.field_bit_size = 128,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
-		},
-	.field_info_spec = {
-		.description = "o_ipv6.dst",
-		.field_bit_size = 128,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
-		}
+	.description = "pl_byp_lkup_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */
 	{
-	.field_info_mask = {
-		.description = "o_ipv6.src",
-		.field_bit_size = 128,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
-		},
-	.field_info_spec = {
-		.description = "o_ipv6.src",
-		.field_bit_size = 128,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
-		}
+	.description = "wc_key_id",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "o_eth.smac",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_eth.smac",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "wc_profile_id",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "o_eth.dmac",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_eth.dmac",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "wc_search_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_cntxt_id",
-		.field_bit_size = 10,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "l2_cntxt_id",
-		.field_bit_size = 10,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
-		}
+	.description = "em_key_mask.0",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.field_info_mask = {
-		.description = "em_profile_id",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "em_profile_id",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
-		}
+	.description = "em_key_mask.1",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 1, wh_plus, table: eem.ipv6_0 */
 	{
-	.field_info_mask = {
-		.description = "spare",
-		.field_bit_size = 35,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "spare",
-		.field_bit_size = 35,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.2",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "local_cos",
-		.field_bit_size = 3,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "local_cos",
-		.field_bit_size = 3,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.3",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "o_l4.dport",
-		.field_bit_size = 16,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_l4.dport",
-		.field_bit_size = 16,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
-		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr2 = {
-			(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
-		}
+	.description = "em_key_mask.4",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+	},
+	{
+	.description = "em_key_mask.5",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "o_l4.sport",
-		.field_bit_size = 16,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_l4.sport",
-		.field_bit_size = 16,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
-		.field_src2 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr2 = {
-			(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
-		}
+	.description = "em_key_mask.6",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "o_ipv6.ip_proto",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_ipv6.ip_proto",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
-		.field_cond_opr = {
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
-			((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
-			(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_IP_PROTO_TCP},
-		.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr2 = {
-			ULP_WP_SYM_IP_PROTO_UDP}
-		}
+	.description = "em_key_mask.7",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "o_ipv6.dst",
-		.field_bit_size = 128,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
-		},
-	.field_info_spec = {
-		.description = "o_ipv6.dst",
-		.field_bit_size = 128,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
-		}
+	.description = "em_key_mask.8",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "o_ipv6.src",
-		.field_bit_size = 128,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
-		},
-	.field_info_spec = {
-		.description = "o_ipv6.src",
-		.field_bit_size = 128,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_HF,
-		.field_opr1 = {
-			(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
-			BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
-		}
+	.description = "em_key_mask.9",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "o_eth.smac",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_eth.smac",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_id",
+	.field_bit_size = 5,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		7}
 	},
 	{
-	.field_info_mask = {
-		.description = "o_eth.dmac",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "o_eth.dmac",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_profile_id",
+	.field_bit_size = 8,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_cntxt_id",
-		.field_bit_size = 10,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "l2_cntxt_id",
-		.field_bit_size = 10,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
-		}
+	.description = "em_search_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.field_info_mask = {
-		.description = "em_profile_id",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "em_profile_id",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-		.field_opr1 = {
-			(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-			BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
-		}
+	.description = "pl_byp_lkup_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
+	/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */
 	{
-	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "rid",
+	.field_bit_size = 32,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_RID & 0xff}
 	},
-	{
-	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	{
+	.description = "profile_tcam_index",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_profile_id",
+	.field_bit_size = 8,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
-		}
+	.description = "wm_profile_id",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "flow_sig_id",
+	.field_bit_size = 8,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
 	},
+	/* class_tid: 1, wh_plus, table: em.ipv4 */
 	{
-	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_ptr",
+	.field_bit_size = 33,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "ext_flow_cntr",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_size",
+	.field_bit_size = 5,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "key_size",
+	.field_bit_size = 9,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "reserved",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "strength",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		3}
 	},
 	{
-	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
+	.description = "l1_cacheable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
-		}
+	.description = "valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
-	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
+	/* class_tid: 1, wh_plus, table: eem.ipv4 */
 	{
-	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_ptr",
+	.field_bit_size = 33,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "ext_flow_cntr",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_EEM_ACT_REC_INT}
 	},
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "act_rec_size",
+	.field_bit_size = 5,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "key_size",
+	.field_bit_size = 9,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		(413 >> 8) & 0xff,
+		413 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "reserved",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "strength",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		3}
 	},
 	{
-	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "l1_cacheable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
+	/* class_tid: 1, wh_plus, table: em.ipv6 */
 	{
-	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_ptr",
+	.field_bit_size = 33,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "ext_flow_cntr",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "act_rec_size",
+	.field_bit_size = 5,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
+	.description = "key_size",
+	.field_bit_size = 9,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "reserved",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
 	{
-	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "strength",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		3}
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "l1_cacheable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
+	/* class_tid: 1, wh_plus, table: eem.ipv6 */
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "act_rec_ptr",
+	.field_bit_size = 33,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "ext_flow_cntr",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_EEM_ACT_REC_INT}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_size",
+	.field_bit_size = 5,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "key_size",
+	.field_bit_size = 9,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		(413 >> 8) & 0xff,
+		413 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "reserved",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "strength",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		3}
+	},
+	{
+	.description = "l1_cacheable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
+	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
 	{
-	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "l2_cntxt_id",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "prof_func_id",
+	.field_bit_size = 7,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
+	.description = "l2_byp_lkup_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "parif",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_CF,
+	.field_cond_opr = {
+		(BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff},
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_LOOPBACK_PARIF},
+	.field_src2 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr2 = {
+		(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "allowed_pri",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
 	{
-	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "default_pri",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "allowed_tpid",
+	.field_bit_size = 6,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "default_tpid",
+	.field_bit_size = 3,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "bd_act_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "sp_rec_ptr",
+	.field_bit_size = 16,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "byp_sp_lkup",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "pri_anti_spoof_ctl",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "tpid_anti_spoof_ctl",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */
 	{
-	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "wc_key_id",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "wc_profile_id",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "wc_search_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.0",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
+	.description = "em_key_mask.1",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "em_key_mask.2",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
 	{
-	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.3",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
-		}
+	.description = "em_key_mask.4",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.5",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "em_key_mask.6",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.7",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.8",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.9",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_id",
+	.field_bit_size = 5,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		4}
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			2}
-		}
+	.description = "em_profile_id",
+	.field_bit_size = 8,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_search_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_TUN_HDR_TYPE_NONE}
-		}
+	.description = "pl_byp_lkup_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */
 	{
-	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "wc_key_id",
+	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
+	.description = "wc_profile_id",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
 	{
-	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff,
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
-		}
+	.description = "wc_search_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.0",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.field_info_mask = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.1",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
-		}
+	.description = "em_key_mask.2",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "em_key_mask.3",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.4",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+	.field_opr1 = {
+		(BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.5",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.6",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_O_L4_SPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_L4_SPORT & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.7",
+	.field_bit_size = 1,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_O_L4_DPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_L4_DPORT & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
+	.description = "em_key_mask.8",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_key_mask.9",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			ULP_WP_SYM_TUN_HDR_TYPE_NONE}
-		}
+	.description = "em_key_id",
+	.field_bit_size = 5,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		7}
 	},
 	{
-	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "em_profile_id",
+	.field_bit_size = 8,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
+	.description = "em_search_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
-	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */
 	{
-	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "pl_byp_lkup_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */
 	{
-	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "rid",
+	.field_bit_size = 32,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_RID & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "profile_tcam_index",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+	},
+	{
+	.description = "em_profile_id",
+	.field_bit_size = 8,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
-		}
+	.description = "wm_profile_id",
+	.field_bit_size = 8,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "flow_sig_id",
+	.field_bit_size = 8,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
 	},
+	/* class_tid: 2, wh_plus, table: em.ipv4 */
 	{
-	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_ptr",
+	.field_bit_size = 33,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "ext_flow_cntr",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_size",
+	.field_bit_size = 5,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "key_size",
+	.field_bit_size = 9,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "reserved",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "strength",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		3}
 	},
 	{
-	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
+	.description = "l1_cacheable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
-		}
+	.description = "valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
-	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */
+	/* class_tid: 2, wh_plus, table: eem.ipv4 */
 	{
-	.field_info_mask = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_ptr",
+	.field_bit_size = 33,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+	},
+	{
+	.description = "ext_flow_cntr",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_EEM_ACT_REC_INT}
 	},
 	{
-	.field_info_mask = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac0_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_size",
+	.field_bit_size = 5,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "svif",
-		.field_bit_size = 8,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-		.field_opr1 = {
-			(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-			BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
-		}
+	.description = "key_size",
+	.field_bit_size = 9,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		(413 >> 8) & 0xff,
+		413 & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "sparif",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "reserved",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ivlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "strength",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		3}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_ovlan_vid",
-		.field_bit_size = 12,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "l1_cacheable",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "mac1_addr",
-		.field_bit_size = 48,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
+	/* class_tid: 2, wh_plus, table: em.ipv6 */
 	{
-	.field_info_mask = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "l2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_ptr",
+	.field_bit_size = 33,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
 	{
-	.field_info_mask = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tl2_num_vtags",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "ext_flow_cntr",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		},
-	.field_info_spec = {
-		.description = "tun_hdr_type",
-		.field_bit_size = 4,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_int",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "key_type",
-		.field_bit_size = 2,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-		}
+	.description = "act_rec_size",
+	.field_bit_size = 5,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.field_info_mask = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			0xff}
-		},
-	.field_info_spec = {
-		.description = "valid",
-		.field_bit_size = 1,
-		.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-		.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-		.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-		.field_opr1 = {
-			1}
-		}
-	}
-};
-
-struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
-	/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
-	{
-	.description = "l2_cntxt_id",
-	.field_bit_size = 10,
+	.description = "key_size",
+	.field_bit_size = 9,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "prof_func_id",
-	.field_bit_size = 7,
+	.description = "reserved",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "strength",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 	.field_opr1 = {
-		(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
+		3}
 	},
 	{
-	.description = "l2_byp_lkup_en",
+	.description = "l1_cacheable",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "parif",
-	.field_bit_size = 4,
+	.description = "valid",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+		1}
 	},
+	/* class_tid: 2, wh_plus, table: eem.ipv6 */
 	{
-	.description = "allowed_pri",
-	.field_bit_size = 8,
+	.description = "act_rec_ptr",
+	.field_bit_size = 33,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+	},
+	{
+	.description = "ext_flow_cntr",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "default_pri",
-	.field_bit_size = 3,
+	.description = "act_rec_int",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		ULP_WP_SYM_EEM_ACT_REC_INT}
 	},
 	{
-	.description = "allowed_tpid",
-	.field_bit_size = 6,
+	.description = "act_rec_size",
+	.field_bit_size = 5,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+	},
+	{
+	.description = "key_size",
+	.field_bit_size = 9,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		(413 >> 8) & 0xff,
+		413 & 0xff}
 	},
 	{
-	.description = "default_tpid",
-	.field_bit_size = 3,
+	.description = "reserved",
+	.field_bit_size = 11,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "bd_act_en",
-	.field_bit_size = 1,
+	.description = "strength",
+	.field_bit_size = 2,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		3}
 	},
 	{
-	.description = "sp_rec_ptr",
-	.field_bit_size = 16,
+	.description = "l1_cacheable",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "byp_sp_lkup",
+	.description = "valid",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -5861,259 +10619,270 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_opr1 = {
 		1}
 	},
+	/* class_tid: 3, wh_plus, table: int_full_act_record.0 */
 	{
-	.description = "pri_anti_spoof_ctl",
-	.field_bit_size = 2,
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "tpid_anti_spoof_ctl",
-	.field_bit_size = 2,
+	.description = "age_enable",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */
 	{
-	.description = "wc_key_id",
-	.field_bit_size = 4,
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "wc_profile_id",
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_key",
 	.field_bit_size = 8,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "wc_search_en",
+	.description = "tcpflags_mir",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "tcpflags_match",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "em_key_mask",
+	.description = "encap_ptr",
+	.field_bit_size = 11,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	},
+	{
+	.description = "dst_ip_ptr",
 	.field_bit_size = 10,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		(125 >> 8) & 0xff,
-		125 & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "em_key_id",
-	.field_bit_size = 5,
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		3}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "em_profile_id",
-	.field_bit_size = 8,
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "em_search_en",
-	.field_bit_size = 1,
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		1}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "pl_byp_lkup_en",
-	.field_bit_size = 1,
+	.description = "meter_id",
+	.field_bit_size = 10,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */
 	{
-	.description = "wc_key_id",
-	.field_bit_size = 4,
+	.description = "l3_rdir",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "wc_profile_id",
-	.field_bit_size = 8,
+	.description = "tl3_rdir",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "wc_search_en",
+	.description = "l3_ttl_dec",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "em_key_mask",
-	.field_bit_size = 10,
+	.description = "tl3_ttl_dec",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		(249 >> 8) & 0xff,
-		249 & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "em_key_id",
-	.field_bit_size = 5,
+	.description = "decap_func",
+	.field_bit_size = 4,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		7}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "em_profile_id",
-	.field_bit_size = 8,
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+		(BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
 	},
 	{
-	.description = "em_search_en",
+	.description = "pop_vlan",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		1}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "pl_byp_lkup_en",
+	.description = "meter",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */
 	{
-	.description = "rid",
-	.field_bit_size = 32,
+	.description = "mirror",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_RID & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "profile_tcam_index",
-	.field_bit_size = 10,
+	.description = "drop",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "em_profile_id",
-	.field_bit_size = 8,
+	.description = "hit",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "wm_profile_id",
-	.field_bit_size = 8,
+	.description = "type",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	{
-	.description = "flow_sig_id",
-	.field_bit_size = 8,
+	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
+	{
+	.description = "l2_cntxt_id",
+	.field_bit_size = 10,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+		(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
 	},
-	/* class_tid: 1, wh_plus, table: em.ipv4_0 */
 	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 33,
+	.description = "prof_func_id",
+	.field_bit_size = 7,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
 	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+		(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
 	},
 	{
-	.description = "ext_flow_cntr",
+	.description = "l2_byp_lkup_en",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "act_rec_int",
-	.field_bit_size = 1,
+	.description = "parif",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+	},
+	{
+	.description = "allowed_pri",
+	.field_bit_size = 8,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "act_rec_size",
-	.field_bit_size = 5,
+	.description = "default_pri",
+	.field_bit_size = 3,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "key_size",
-	.field_bit_size = 9,
+	.description = "allowed_tpid",
+	.field_bit_size = 6,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "reserved",
-	.field_bit_size = 11,
+	.description = "default_tpid",
+	.field_bit_size = 3,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "strength",
-	.field_bit_size = 2,
+	.description = "bd_act_en",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		3}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "l1_cacheable",
-	.field_bit_size = 1,
+	.description = "sp_rec_ptr",
+	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "valid",
+	.description = "byp_sp_lkup",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
@@ -6121,416 +10890,404 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_opr1 = {
 		1}
 	},
-	/* class_tid: 1, wh_plus, table: eem.ipv4_0 */
 	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 33,
+	.description = "pri_anti_spoof_ctl",
+	.field_bit_size = 2,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "ext_flow_cntr",
-	.field_bit_size = 1,
+	.description = "tpid_anti_spoof_ctl",
+	.field_bit_size = 2,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
 	{
-	.description = "act_rec_int",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "rid",
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		ULP_WP_SYM_EEM_ACT_REC_INT}
+		(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_RID & 0xff}
 	},
 	{
-	.description = "act_rec_size",
-	.field_bit_size = 5,
+	.description = "l2_cntxt_tcam_index",
+	.field_bit_size = 10,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+		(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
 	},
 	{
-	.description = "key_size",
-	.field_bit_size = 9,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "l2_cntxt_id",
+	.field_bit_size = 10,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		(173 >> 8) & 0xff,
-		173 & 0xff}
+		(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
 	},
 	{
-	.description = "reserved",
-	.field_bit_size = 11,
+	.description = "src_property_ptr",
+	.field_bit_size = 10,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */
 	{
-	.description = "strength",
-	.field_bit_size = 2,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "act_rec_ptr",
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		3}
-	},
-	{
-	.description = "l1_cacheable",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
+	/* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */
 	{
-	.description = "valid",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "act_rec_ptr",
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		1}
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
-	/* class_tid: 1, wh_plus, table: em.ipv6_0 */
+	/* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */
 	{
 	.description = "act_rec_ptr",
-	.field_bit_size = 33,
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
 		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
 		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
+	/* class_tid: 4, wh_plus, table: int_full_act_record.vfr */
 	{
-	.description = "ext_flow_cntr",
-	.field_bit_size = 1,
+	.description = "flow_cntr_ptr",
+	.field_bit_size = 14,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "act_rec_int",
+	.description = "age_enable",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "act_rec_size",
-	.field_bit_size = 5,
+	.description = "agg_cntr_en",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "key_size",
-	.field_bit_size = 9,
+	.description = "rate_cntr_en",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "reserved",
-	.field_bit_size = 11,
+	.description = "flow_cntr_en",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "strength",
-	.field_bit_size = 2,
+	.description = "tcpflags_key",
+	.field_bit_size = 8,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		3}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "l1_cacheable",
+	.description = "tcpflags_mir",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "valid",
+	.description = "tcpflags_match",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		1}
-	},
-	/* class_tid: 1, wh_plus, table: eem.ipv6_0 */
-	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 33,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "ext_flow_cntr",
-	.field_bit_size = 1,
+	.description = "encap_ptr",
+	.field_bit_size = 11,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "act_rec_int",
-	.field_bit_size = 1,
+	.description = "dst_ip_ptr",
+	.field_bit_size = 10,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		ULP_WP_SYM_EEM_ACT_REC_INT}
-	},
-	{
-	.description = "act_rec_size",
-	.field_bit_size = 5,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "key_size",
-	.field_bit_size = 9,
+	.description = "tcp_dst_port",
+	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		(413 >> 8) & 0xff,
-		413 & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "reserved",
-	.field_bit_size = 11,
+	.description = "src_ip_ptr",
+	.field_bit_size = 10,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "strength",
-	.field_bit_size = 2,
+	.description = "tcp_src_port",
+	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		3}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "l1_cacheable",
-	.field_bit_size = 1,
+	.description = "meter_id",
+	.field_bit_size = 10,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "valid",
+	.description = "l3_rdir",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		1}
-	},
-	/* class_tid: 2, wh_plus, table: int_full_act_record.0 */
-	{
-	.description = "flow_cntr_ptr",
-	.field_bit_size = 14,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "age_enable",
+	.description = "tl3_rdir",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "agg_cntr_en",
+	.description = "l3_ttl_dec",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "rate_cntr_en",
+	.description = "tl3_ttl_dec",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "flow_cntr_en",
-	.field_bit_size = 1,
+	.description = "decap_func",
+	.field_bit_size = 4,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "tcpflags_key",
-	.field_bit_size = 8,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "vnic_or_vport",
+	.field_bit_size = 12,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
 	},
 	{
-	.description = "tcpflags_mir",
+	.description = "pop_vlan",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "tcpflags_match",
+	.description = "meter",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "encap_ptr",
-	.field_bit_size = 11,
+	.description = "mirror",
+	.field_bit_size = 2,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "dst_ip_ptr",
-	.field_bit_size = 10,
+	.description = "drop",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "tcp_dst_port",
-	.field_bit_size = 16,
+	.description = "hit",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "src_ip_ptr",
-	.field_bit_size = 10,
+	.description = "type",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr */
 	{
-	.description = "tcp_src_port",
+	.description = "act_record_ptr",
 	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "meter_id",
-	.field_bit_size = 10,
+	.description = "reserved",
+	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "l3_rdir",
+	.description = "l2_byp_lkup_en",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.description = "tl3_rdir",
-	.field_bit_size = 1,
+	.description = "parif",
+	.field_bit_size = 4,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_opr1 = {
+		(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+	},
+	{
+	.description = "allowed_pri",
+	.field_bit_size = 8,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "l3_ttl_dec",
-	.field_bit_size = 1,
+	.description = "default_pri",
+	.field_bit_size = 3,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "tl3_ttl_dec",
-	.field_bit_size = 1,
+	.description = "allowed_tpid",
+	.field_bit_size = 6,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "decap_func",
-	.field_bit_size = 4,
+	.description = "default_tpid",
+	.field_bit_size = 3,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "vnic_or_vport",
-	.field_bit_size = 12,
+	.description = "bd_act_en",
+	.field_bit_size = 1,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
 	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+		1}
 	},
 	{
-	.description = "pop_vlan",
-	.field_bit_size = 1,
+	.description = "sp_rec_ptr",
+	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "meter",
+	.description = "byp_sp_lkup",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
-	.description = "mirror",
+	.description = "pri_anti_spoof_ctl",
 	.field_bit_size = 2,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "drop",
-	.field_bit_size = 1,
+	.description = "tpid_anti_spoof_ctl",
+	.field_bit_size = 2,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_vfr */
 	{
-	.description = "hit",
-	.field_bit_size = 1,
+	.description = "rid",
+	.field_bit_size = 32,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_RID & 0xff}
+	},
+	{
+	.description = "l2_cntxt_tcam_index",
+	.field_bit_size = 10,
+	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
+	.field_opr1 = {
+		(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+	},
+	{
+	.description = "l2_cntxt_id",
+	.field_bit_size = 10,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "type",
-	.field_bit_size = 1,
+	.description = "src_property_ptr",
+	.field_bit_size = 10,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */
 	{
 	.description = "l2_cntxt_id",
 	.field_bit_size = 10,
@@ -6562,8 +11319,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
 	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+		(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
 	},
 	{
 	.description = "allowed_pri",
@@ -6630,7 +11387,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */
 	{
 	.description = "rid",
 	.field_bit_size = 32,
@@ -6665,37 +11422,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */
-	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 32,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
-	},
-	/* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */
-	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 32,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
-	},
-	/* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */
-	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 32,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
-	},
-	/* class_tid: 3, wh_plus, table: int_full_act_record.0 */
+	/* class_tid: 4, wh_plus, table: int_full_act_record.0 */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -6880,140 +11607,66 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
+	/* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */
 	{
-	.description = "act_record_ptr",
-	.field_bit_size = 16,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "reserved",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "l2_byp_lkup_en",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "act_rec_ptr",
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		1}
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
+	/* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */
 	{
-	.description = "parif",
-	.field_bit_size = 4,
+	.description = "act_rec_ptr",
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
-	},
-	{
-	.description = "allowed_pri",
-	.field_bit_size = 8,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "default_pri",
-	.field_bit_size = 3,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "allowed_tpid",
-	.field_bit_size = 6,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "default_tpid",
-	.field_bit_size = 3,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
+	/* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */
 	{
-	.description = "bd_act_en",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
+	.description = "act_rec_ptr",
+	.field_bit_size = 32,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
 	.field_opr1 = {
-		1}
+		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
 	},
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
 	{
-	.description = "sp_rec_ptr",
+	.description = "act_record_ptr",
 	.field_bit_size = 16,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
-	.description = "byp_sp_lkup",
+	.description = "reserved",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		1}
-	},
-	{
-	.description = "pri_anti_spoof_ctl",
-	.field_bit_size = 2,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "tpid_anti_spoof_ctl",
-	.field_bit_size = 2,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
-	{
-	.description = "l2_cntxt_id",
-	.field_bit_size = 10,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
-	},
-	{
-	.description = "prof_func_id",
-	.field_bit_size = 7,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
-	.field_opr1 = {
-		(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
-	},
 	{
 	.description = "l2_byp_lkup_en",
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
 	.description = "parif",
 	.field_bit_size = 4,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "allowed_pri",
@@ -7048,7 +11701,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
 	.description = "sp_rec_ptr",
@@ -7080,7 +11735,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
 	{
 	.description = "rid",
 	.field_bit_size = 32,
@@ -7102,11 +11757,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	{
 	.description = "l2_cntxt_id",
 	.field_bit_size = 10,
+	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
 	{
 	.description = "src_property_ptr",
@@ -7115,37 +11768,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */
-	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 32,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
-	},
-	/* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */
-	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 32,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
-	},
-	/* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */
-	{
-	.description = "act_rec_ptr",
-	.field_bit_size = 32,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
-	},
-	/* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */
+	/* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */
 	{
 	.description = "ecv_tun_type",
 	.field_bit_size = 3,
@@ -7195,7 +11818,9 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_bit_size = 1,
 	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {
+		1}
 	},
 	{
 	.description = "vtag_tpid",
@@ -7237,7 +11862,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */
+	/* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -7425,138 +12050,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
-	{
-	.description = "act_record_ptr",
-	.field_bit_size = 16,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "reserved",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "l2_byp_lkup_en",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		1}
-	},
-	{
-	.description = "parif",
-	.field_bit_size = 4,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "allowed_pri",
-	.field_bit_size = 8,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "default_pri",
-	.field_bit_size = 3,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "allowed_tpid",
-	.field_bit_size = 6,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "default_tpid",
-	.field_bit_size = 3,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "bd_act_en",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		1}
-	},
-	{
-	.description = "sp_rec_ptr",
-	.field_bit_size = 16,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "byp_sp_lkup",
-	.field_bit_size = 1,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
-	.field_opr1 = {
-		1}
-	},
-	{
-	.description = "pri_anti_spoof_ctl",
-	.field_bit_size = 2,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "tpid_anti_spoof_ctl",
-	.field_bit_size = 2,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
-	{
-	.description = "rid",
-	.field_bit_size = 32,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_RID & 0xff}
-	},
-	{
-	.description = "l2_cntxt_tcam_index",
-	.field_bit_size = 10,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_RF,
-	.field_opr1 = {
-		(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-		BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
-	},
-	{
-	.description = "l2_cntxt_id",
-	.field_bit_size = 10,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	{
-	.description = "src_property_ptr",
-	.field_bit_size = 10,
-	.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
-	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
-	},
-	/* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */
+	/* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -7743,7 +12237,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
 	{
 	.description = "act_record_ptr",
 	.field_bit_size = 16,
@@ -7841,7 +12335,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
 	{
 	.description = "act_record_ptr",
 	.field_bit_size = 16,
@@ -7939,7 +12433,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */
+	/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */
 	{
 	.description = "l2_cntxt_id",
 	.field_bit_size = 10,
@@ -7969,10 +12463,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.description = "parif",
 	.field_bit_size = 4,
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
-	.field_src1 = BNXT_ULP_FIELD_SRC_CF,
-	.field_opr1 = {
-		(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff}
+	.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+	.field_opr1 = {ULP_WP_SYM_LOOPBACK_PARIF & 0xff}
 	},
 	{
 	.description = "allowed_pri",
@@ -8039,7 +12531,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
+	/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
 	{
 	.description = "rid",
 	.field_bit_size = 32,
@@ -8074,7 +12566,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */
+	/* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */
 	{
 	.description = "act_rec_ptr",
 	.field_bit_size = 32,
@@ -8084,7 +12576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 		(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
 		BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
 	},
-	/* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */
+	/* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */
 	{
 	.description = "act_rec_ptr",
 	.field_bit_size = 32,
@@ -8094,7 +12586,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 		(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
 		BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
 	},
-	/* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */
+	/* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */
 	{
 	.description = "act_rec_ptr",
 	.field_bit_size = 32,
@@ -8104,7 +12596,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 		(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
 		BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
 	},
-	/* class_tid: 5, wh_plus, table: int_full_act_record.ing */
+	/* class_tid: 6, wh_plus, table: int_full_act_record.ing */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -8289,7 +12781,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */
+	/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */
 	{
 	.description = "act_record_ptr",
 	.field_bit_size = 16,
@@ -8387,7 +12879,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 	.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
 	.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
 	},
-	/* class_tid: 6, wh_plus, table: int_full_act_record.0 */
+	/* class_tid: 7, wh_plus, table: int_full_act_record.0 */
 	{
 	.description = "flow_cntr_ptr",
 	.field_bit_size = 14,
@@ -8576,6 +13068,13 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
 };
 
 struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
+	/* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */
+	{
+	.description = "l2_cntxt_id",
+	.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 42
+	},
 	/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
 	{
 	.description = "l2_cntxt_id",
@@ -8587,10 +13086,10 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	},
 	/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */
 	{
-	.description = "profile_tcam_index",
-	.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
-	.ident_bit_size = 10,
-	.ident_bit_pos = 32
+	.description = "em_profile_id",
+	.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+	.ident_bit_size = 8,
+	.ident_bit_pos = 42
 	},
 	{
 	.description = "flow_sig_id",
@@ -8599,12 +13098,12 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	.ident_bit_pos = 58
 	},
 	{
-	.description = "em_profile_id",
-	.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
-	.ident_bit_size = 8,
-	.ident_bit_pos = 42
+	.description = "profile_tcam_index",
+	.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 32
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam.ipv4_0 */
+	/* class_tid: 1, wh_plus, table: profile_tcam.ipv4 */
 	{
 	.description = "em_profile_id",
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -8613,7 +13112,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	.ident_bit_size = 8,
 	.ident_bit_pos = 28
 	},
-	/* class_tid: 1, wh_plus, table: profile_tcam.ipv6_0 */
+	/* class_tid: 1, wh_plus, table: profile_tcam.ipv6 */
 	{
 	.description = "em_profile_id",
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -8622,6 +13121,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	.ident_bit_size = 8,
 	.ident_bit_pos = 28
 	},
+	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.rd */
+	{
+	.description = "l2_cntxt_id",
+	.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 42
+	},
 	/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
 	{
 	.description = "l2_cntxt_id",
@@ -8631,13 +13137,43 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	.ident_bit_size = 10,
 	.ident_bit_pos = 0
 	},
-	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */
+	/* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */
 	{
-	.description = "l2_cntxt_id",
-	.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
-	.ident_bit_size = 10,
+	.description = "em_profile_id",
+	.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+	.ident_bit_size = 8,
 	.ident_bit_pos = 42
 	},
+	{
+	.description = "flow_sig_id",
+	.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
+	.ident_bit_size = 8,
+	.ident_bit_pos = 58
+	},
+	{
+	.description = "profile_tcam_index",
+	.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 32
+	},
+	/* class_tid: 2, wh_plus, table: profile_tcam.ipv4 */
+	{
+	.description = "em_profile_id",
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+	.ident_bit_size = 8,
+	.ident_bit_pos = 28
+	},
+	/* class_tid: 2, wh_plus, table: profile_tcam.ipv6 */
+	{
+	.description = "em_profile_id",
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
+	.ident_bit_size = 8,
+	.ident_bit_pos = 28
+	},
 	/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
 	{
 	.description = "l2_cntxt_id",
@@ -8647,14 +13183,16 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	.ident_bit_size = 10,
 	.ident_bit_pos = 0
 	},
-	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd_egr0 */
+	/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */
 	{
-	.description = "l2_cntxt_tcam_index",
-	.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+	.description = "l2_cntxt_id",
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+	.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
 	.ident_bit_size = 10,
-	.ident_bit_pos = 32
+	.ident_bit_pos = 0
 	},
-	/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */
+	/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */
 	{
 	.description = "l2_cntxt_id",
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index af28283385..20a988a03a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -81,6 +81,8 @@ struct ulp_rte_parser_params {
 	struct bnxt_ulp_context		*ulp_ctx;
 	uint32_t			hdr_sig_id;
 	uint32_t			flow_sig_id;
+	uint32_t			flow_pattern_id;
+	uint32_t			act_pattern_id;
 };
 
 /* Flow Parser Header Information Structure */
@@ -128,6 +130,7 @@ struct bnxt_ulp_class_match_info {
 	uint8_t			wc_pri;
 	uint32_t		hdr_sig_id;
 	uint32_t		flow_sig_id;
+	uint32_t		flow_pattern_id;
 };
 
 /* Flow Matcher templates Structure for class entries */
@@ -144,6 +147,7 @@ struct bnxt_ulp_act_match_info {
 	struct ulp_rte_bitmap	act_sig;
 	uint32_t		act_hid;
 	uint32_t		act_tid;
+	uint32_t		act_pattern_id;
 };
 
 /* Flow Matcher templates Structure for action entries */
@@ -160,7 +164,8 @@ struct bnxt_ulp_mapper_cond_list_info {
 	enum bnxt_ulp_cond_list_opc cond_list_opcode;
 	uint32_t cond_start_idx;
 	uint32_t cond_nums;
-	uint32_t cond_goto;
+	int32_t cond_true_goto;
+	int32_t cond_false_goto;
 };
 
 struct bnxt_ulp_template_device_tbls {
