@@ -106,7 +106,7 @@ roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
return tries ? 0 : -ETIMEDOUT;
}
-static int __rte_unused
+static int
roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
uint64_t scr1, uint64_t *scr0)
{
@@ -206,3 +206,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
return 0;
}
+
+static bool
+roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+ return (lmac < MAX_LMACS_PER_CGX) &&
+ (roc_cgx->lmac_bmap & BIT_ULL(lmac));
+}
+
+int
+roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ struct roc_bphy_cgx_link_info *info)
+{
+ uint64_t scr1, scr0;
+ int ret;
+
+ if (!roc_cgx)
+ return -EINVAL;
+
+ if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+ return -ENODEV;
+
+ if (!info)
+ return -EINVAL;
+
+ scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
+ ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+ if (ret)
+ return ret;
+
+ info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
+ info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
+ info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
+ info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
+ info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
+ info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
+
+ return 0;
+}
@@ -9,6 +9,8 @@
#include "roc_api.h"
+#define MAX_LMACS_PER_CGX 4
+
struct roc_bphy_cgx {
uint64_t bar0_pa;
void *bar0_va;
@@ -18,7 +20,75 @@ struct roc_bphy_cgx {
pthread_mutex_t lock;
} __plt_cache_aligned;
+enum roc_bphy_cgx_eth_link_speed {
+ ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
+ __ROC_BPHY_CGX_ETH_LINK_SPEED_MAX
+};
+
+enum roc_bphy_cgx_eth_link_fec {
+ ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
+ ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+ ROC_BPHY_CGX_ETH_LINK_FEC_RS,
+ __ROC_BPHY_CGX_ETH_LINK_FEC_MAX
+};
+
+enum roc_bphy_cgx_eth_link_mode {
+ ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+ __ROC_BPHY_CGX_ETH_LINK_MODE_MAX
+};
+
+struct roc_bphy_cgx_link_info {
+ bool link_up;
+ bool full_duplex;
+ enum roc_bphy_cgx_eth_link_speed speed;
+ bool an;
+ enum roc_bphy_cgx_eth_link_fec fec;
+ enum roc_bphy_cgx_eth_link_mode mode;
+};
+
__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac,
+ struct roc_bphy_cgx_link_info *info);
+
#endif /* _ROC_BPHY_CGX_H_ */
@@ -7,6 +7,7 @@
/* REQUEST ID types. Input to firmware */
enum eth_cmd_id {
+ ETH_CMD_GET_LINK_STS = 4,
ETH_CMD_INTF_SHUTDOWN = 12,
};
@@ -41,6 +42,14 @@ enum eth_cmd_own {
/* struct eth_lnk_sts_s */
#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)
+#define SCR0_ETH_LNK_STS_S_LINK_UP BIT_ULL(9)
+#define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)
+#define SCR0_ETH_LNK_STS_S_SPEED GENMASK_ULL(14, 11)
+#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)
+#define SCR0_ETH_LNK_STS_S_AN BIT_ULL(25)
+#define SCR0_ETH_LNK_STS_S_FEC GENMASK_ULL(27, 26)
+#define SCR0_ETH_LNK_STS_S_LMAC_TYPE GENMASK_ULL(35, 28)
+#define SCR0_ETH_LNK_STS_S_MODE GENMASK_ULL(43, 36)
/* scratchx(1) CSR used for non-secure SW->ATF communication
* This CSR acts as a command register
@@ -11,6 +11,7 @@ INTERNAL {
cnxk_logtype_tm;
roc_bphy_cgx_dev_fini;
roc_bphy_cgx_dev_init;
+ roc_bphy_cgx_get_linkinfo;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;