diff mbox series

net/mlx5: fix threshold for mbuf replenishment in MPRQ

Message ID 20210712142910.314572-1-akozyrev@nvidia.com (mailing list archive)
State Superseded, archived
Headers
Series net/mlx5: fix threshold for mbuf replenishment in MPRQ |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/github-robot success github build: passed
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-abi-testing warning Testing issues
ci/iol-testing fail Testing issues
ci/Intel-compilation warning apply issues
ci/iol-intel-Performance fail Performance Testing issues

Commit Message

Alexander Kozyrev July 12, 2021, 2:29 p.m. UTC 
  The replenishment scheme for the vectorized MPRQ Rx burst aims
to improve the cache locality by allocating new mbufs only when
there are almost no mbufs left: one burst gap between allocated
and consumed indexes.

This gap is not big enough to accommodate a corner case when we
have a very aggressive CQE compression with up to 4 regular CQEs
and 64 zipped CQEs at the end.

Need to keep in mind this case and extend the replenishment
threshold by MLX5_VPMD_DESCS_PER_LOOP (4) to avoid mbuf overflow.

Fixes: 5fc2e5c27d6 ("net/mlx5: fix mbuf overflow in vectorized MPRQ")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/mlx5_rxtx_vec.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c
index d5af2d91ff..e22ab665df 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec.c
+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c
@@ -152,7 +152,8 @@  mlx5_rx_mprq_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq)
 	unsigned int i;
 
 	if (n >= rxq->rq_repl_thresh &&
-	    rxq->elts_ci - rxq->rq_pi <= rxq->rq_repl_thresh) {
+	    rxq->elts_ci - rxq->rq_pi <=
+	    (uint32_t)rxq->rq_repl_thresh + MLX5_VPMD_DESCS_PER_LOOP) {
 		MLX5_ASSERT(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(elts_n));
 		MLX5_ASSERT(MLX5_VPMD_RXQ_RPLNSH_THRESH(elts_n) >
 			     MLX5_VPMD_DESCS_PER_LOOP);