From patchwork Tue Aug 10 02:51:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 96760 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4843A0C54; Tue, 10 Aug 2021 04:50:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3D71A411E5; Tue, 10 Aug 2021 04:49:28 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 6980D411D0 for ; Tue, 10 Aug 2021 04:49:26 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10070"; a="202002199" X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="202002199" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2021 19:49:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="483823776" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:49:24 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang , Jacob Keller Date: Tue, 10 Aug 2021 10:51:33 +0800 Message-Id: <20210810025140.1698163-22-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210810025140.1698163-1-qi.z.zhang@intel.com> References: <20210810025140.1698163-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 21/28] net/ice/base: enable NVM update reset capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add logic to parse capabilities relating to the firmware update reset requirements. This includes both capability 0x76, which informs the driver if the firmware can sometimes skip PCIe resets, and 0x77, which informs the driver if the firmware might potentially restrict EMP resets. For capability 0x76, if the number is 1, the firmware will report the required reset level for a given update as part of its response to the last command sent to program the NVM bank. (Otherwise, if the firmware does not support this capability then it will always send a 0 in the field of the response). For capability 0x77, if the number is 1, the firmware will report when EMP reset is available as part of the response to the command for switching flash banks. (Otherwise, if the firmware does not support this capability, it will always send a 0 in the field of the response message). These capabilities are required to implement immediate firmware activation. If the capabilities are set, software can read the response data and determine what reset level is required to activate the firmware image. If only an EMP reset is required, and if the EMP reset is not restricted by firmware, then the driver can issue an EMP reset to immediately activate the new firmware. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang Acked-by: Junfeng Guo --- drivers/net/ice/base/ice_common.c | 12 ++++++++++++ drivers/net/ice/base/ice_type.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index a77bf32b1c..2744c3d119 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2281,6 +2281,18 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", prefix, caps->max_mtu); break; + case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: + caps->pcie_reset_avoidance = (number > 0); + ice_debug(hw, ICE_DBG_INIT, + "%s: pcie_reset_avoidance = %d\n", prefix, + caps->pcie_reset_avoidance); + break; + case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: + caps->reset_restrict_support = (number == 1); + ice_debug(hw, ICE_DBG_INIT, + "%s: reset_restrict_support = %d\n", prefix, + caps->reset_restrict_support); + break; case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0: case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1: case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2: diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index b76404f085..6ae39a345b 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -480,6 +480,10 @@ struct ice_hw_common_caps { #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) + /* PCIe reset avoidance */ + bool pcie_reset_avoidance; /* false: not supported, true: supported */ + /* Post update reset restriction */ + bool reset_restrict_support; /* false: not supported, true: supported */ /* External topology device images within the NVM */ #define ICE_EXT_TOPO_DEV_IMG_COUNT 4