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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.36 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.36; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.36) by CO1NAM11FT007.mail.protection.outlook.com (10.13.174.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4457.17 via Frontend Transport; Tue, 31 Aug 2021 20:40:10 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 31 Aug 2021 20:40:03 +0000 Received: from nvidia.com (172.20.187.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 31 Aug 2021 20:40:02 +0000 From: Michael Baum To: CC: Matan Azrad , Date: Tue, 31 Aug 2021 23:39:41 +0300 Message-ID: <20210831203941.3411351-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 33f7ace5-08a7-41af-92b6-08d96cbf86e2 X-MS-TrafficTypeDiagnostic: DM6PR12MB4235: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:386; 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CAT:NONE; SFS:(4636009)(346002)(39860400002)(136003)(396003)(376002)(46966006)(36840700001)(2906002)(426003)(82310400003)(478600001)(36756003)(6666004)(8936002)(316002)(70586007)(1076003)(8676002)(4326008)(450100002)(70206006)(5660300002)(7696005)(336012)(26005)(16526019)(186003)(2616005)(47076005)(36906005)(82740400003)(54906003)(356005)(6286002)(55016002)(7636003)(83380400001)(36860700001)(6916009)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2021 20:40:10.6165 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33f7ace5-08a7-41af-92b6-08d96cbf86e2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4235 Subject: [dpdk-dev] [PATCH] compress/mlx5: fix QP setup error flow X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The QP setup function allocates buffer for its opaque MR and register it into MR structure. After buffer alloction and before MR registration, it tries allocate MR Btree. When the MR Btree allocation fails, the buffer was not freed what caused a memory leak. Allocate the MR Btree before buffer alloction. Fixes: 0165bccdb45f ("compress/mlx5: add memory region management") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/compress/mlx5/mlx5_compress.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 883e720ec1..c5e0a83a8c 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -207,6 +207,13 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, return -rte_errno; } dev->data->queue_pairs[qp_id] = qp; + if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N, + priv->dev_config.socket_id)) { + DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", + (uint32_t)qp_id); + rte_errno = ENOMEM; + goto err; + } opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n, sizeof(struct mlx5_gga_compress_opaque), sizeof(struct mlx5_gga_compress_opaque)); @@ -215,13 +222,6 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, rte_errno = ENOMEM; goto err; } - if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N, - priv->dev_config.socket_id)) { - DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.", - (uint32_t)qp_id); - rte_errno = ENOMEM; - goto err; - } qp->entries_n = 1 << log_ops_n; qp->socket_id = socket_id; qp->qp_id = qp_id;