diff mbox series

[08/27] common/cnxk: dump cpt lf registers on error intr

Message ID	20210902021505.17607-9-ndabilpuram@marvell.com (mailing list archive)
State	Superseded, archived
Delegated to:	Jerin Jacob
Headers	From: Nithin Dabilpuram <ndabilpuram@marvell.com> To: Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com> CC: <jerinj@marvell.com>, <schalla@marvell.com>, <dev@dpdk.org> Date: Thu, 2 Sep 2021 07:44:46 +0530 Message-ID: <20210902021505.17607-9-ndabilpuram@marvell.com> In-Reply-To: <20210902021505.17607-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [dpdk-dev] [PATCH 08/27] common/cnxk: dump cpt lf registers on error intr Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	net/cnxk: support for inline ipsec \| [00/27] net/cnxk: support for inline ipsec [01/27] common/cnxk: add security support for cn9k fast path [02/27] common/cnxk: add helper API to dump cpt parse header [03/27] common/cnxk: allow reuse of SSO API for inline dev [04/27] common/cnxk: change nix debug API and queue API interface [05/27] common/cnxk: add nix inline device irq API [06/27] common/cnxk: add nix inline device init and fini [07/27] common/cnxk: add nix inline inbound and outbound support API [08/27] common/cnxk: dump cpt lf registers on error intr [09/27] common/cnxk: align cpt lf enable/disable sequence [10/27] common/cnxk: restore nix sqb pool limit before destroy [11/27] common/cnxk: add cq enable support in nix Tx path [12/27] common/cnxk: setup aura bp conf based on nix [13/27] common/cnxk: add anti-replay check implementation for cn9k [14/27] common/cnxk: add inline IPsec support in rte flow [15/27] net/cnxk: add inline security support for cn9k [16/27] net/cnxk: add inline security support for cn10k [17/27] net/cnxk: add cn9k Rx support for security offload [18/27] net/cnxk: add cn9k Tx support for security offload [19/27] net/cnxk: add cn10k Rx support for security offload [20/27] net/cnxk: add cn10k Tx support for security offload [21/27] net/cnxk: add cn9k anti replay support for security offload [22/27] net/cnxk: add cn10k IPsec transport mode support [23/27] net/cnxk: update ethertype for mixed IPsec tunnel versions [24/27] net/cnxk: allow zero udp6 checksum for non inline device [25/27] net/cnxk: add crypto capabilities for AES CBC and HMAC SHA1 [26/27] net/cnxk: add devargs for configuring channel mask [27/27] net/cnxk: reflect globally enabled offloads in queue conf

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Nithin Dabilpuram Sept. 2, 2021, 2:14 a.m. UTC

  Dump CPT LF registers on error interrupt.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_cpt.c       |  5 ++++-
 drivers/common/cnxk/roc_cpt_debug.c | 32 ++++++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_cpt_priv.h  |  1 +
 3 files changed, 35 insertions(+), 3 deletions(-)

diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 3222b3e..f08b5d0 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -51,6 +51,9 @@  cpt_lf_misc_irq(void *param)
 
 	plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
 
+	/* Dump lf registers */
+	cpt_lf_print(lf);
+
 	/* Clear interrupt */
 	plt_write64(intr, lf->rbase + CPT_LF_MISC_INT);
 }
@@ -203,7 +206,7 @@  cpt_lf_dump(struct roc_cpt_lf *lf)
 	plt_cpt_dbg("CPT LF REG:");
 	plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL,
 		    plt_read64(lf->rbase + CPT_LF_CTL));
-	plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG,
+	plt_cpt_dbg("LF_INPROG[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG,
 		    plt_read64(lf->rbase + CPT_LF_INPROG));
 
 	plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE,
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index a6c9004..847d969 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -157,11 +157,40 @@  roc_cpt_afs_print(struct roc_cpt *roc_cpt)
 	return 0;
 }
 
-static void
+void
 cpt_lf_print(struct roc_cpt_lf *lf)
 {
 	uint64_t reg_val;
 
+	reg_val = plt_read64(lf->rbase + CPT_LF_Q_BASE);
+	plt_print("    CPT_LF_Q_BASE:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_Q_SIZE);
+	plt_print("    CPT_LF_Q_SIZE:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_Q_INST_PTR);
+	plt_print("    CPT_LF_Q_INST_PTR:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR);
+	plt_print("    CPT_LF_Q_GRP_PTR:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTL);
+	plt_print("    CPT_LF_CTL:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
+	plt_print("    CPT_LF_MISC_INT_ENA_W1S:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT);
+	plt_print("    CPT_LF_MISC_INT:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_INPROG);
+	plt_print("    CPT_LF_INPROG:\t%016lx", reg_val);
+
+	if (roc_model_is_cn9k())
+		return;
+
+	plt_print("Count registers for CPT LF%d:", lf->lf_id);
+
 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);
 	plt_print("    Encrypted byte count:\t%" PRIu64, reg_val);
 
@@ -190,7 +219,6 @@  roc_cpt_lfs_print(struct roc_cpt *roc_cpt)
 		if (lf == NULL)
 			continue;
 
-		plt_print("Count registers for CPT LF%d:", lf_id);
 		cpt_lf_print(lf);
 	}
 
diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h
index 21911e5..61dec9a 100644
--- a/drivers/common/cnxk/roc_cpt_priv.h
+++ b/drivers/common/cnxk/roc_cpt_priv.h
@@ -31,5 +31,6 @@  int cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,
 		    uint8_t lf_id, bool ena);
 int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);
 uint64_t cpt_get_blkaddr(struct dev *dev);
+void cpt_lf_print(struct roc_cpt_lf *lf);
 
 #endif /* _ROC_CPT_PRIV_H_ */