diff mbox series

[v2] crypto/mlx5: fix timestamp format configuration

Message ID 20210905080415.3836354-1-michaelba@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series [v2] crypto/mlx5: fix timestamp format configuration |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/github-robot: build success github build: passed
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS

Commit Message

Michael Baum Sept. 5, 2021, 8:04 a.m. UTC 
  This patch adds support for the timestamp format settings for
the receive and send queues. If the firmware version x.30.1000
or above is installed and the NIC timestamps are configured
with the real-time format, the default zero values for newly
added fields cause the queue creation to fail.

The patch queries the timestamp formats supported by the hardware
and sets the configuration values in queue context accordingly.

Fixes: 6152534e211e ("crypto/mlx5: support queue pairs operations")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---

v2: Align title and description of the patch to a fix format.

 drivers/crypto/mlx5/mlx5_crypto.c | 2 ++
 drivers/crypto/mlx5/mlx5_crypto.h | 1 +
 2 files changed, 3 insertions(+)

Comments

Akhil Goyal Sept. 6, 2021, 6:15 p.m. UTC | #1 
> This patch adds support for the timestamp format settings for
> the receive and send queues. If the firmware version x.30.1000
> or above is installed and the NIC timestamps are configured
> with the real-time format, the default zero values for newly
> added fields cause the queue creation to fail.
> 
> The patch queries the timestamp formats supported by the hardware
> and sets the configuration values in queue context accordingly.
> 
> Fixes: 6152534e211e ("crypto/mlx5: support queue pairs operations")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Michael Baum <michaelba@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
> 
> v2: Align title and description of the patch to a fix format.
Applied to dpdk-next-crypto

Thanks
diff mbox series

Patch

diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c
index b3d5200ca3..e01be15ade 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.c
+++ b/drivers/crypto/mlx5/mlx5_crypto.c
@@ -707,6 +707,7 @@  mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 	attr.wq_umem_id = qp->umem_obj->umem_id;
 	attr.wq_umem_offset = 0;
 	attr.dbr_umem_id = qp->umem_obj->umem_id;
+	attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);
 	attr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size;
 	qp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
 	if (qp->qp_obj == NULL) {
@@ -1049,6 +1050,7 @@  mlx5_crypto_dev_probe(struct rte_device *dev)
 	priv->ctx = ctx;
 	priv->login_obj = login;
 	priv->crypto_dev = crypto_dev;
+	priv->qp_ts_format = attr.qp_ts_format;
 	if (mlx5_crypto_hw_global_prepare(priv) != 0) {
 		rte_cryptodev_pmd_destroy(priv->crypto_dev);
 		claim_zero(mlx5_glue->close_device(priv->ctx));
diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h
index d49b0001f0..722acb8d19 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.h
+++ b/drivers/crypto/mlx5/mlx5_crypto.h
@@ -25,6 +25,7 @@  struct mlx5_crypto_priv {
 	volatile uint64_t *uar_addr;
 	uint32_t pdn; /* Protection Domain number. */
 	uint32_t max_segs_num; /* Maximum supported data segs. */
+	uint8_t qp_ts_format; /* Whether QP supports timestamp formats. */
 	struct ibv_pd *pd;
 	struct mlx5_hlist *dek_hlist; /* Dek hash list. */
 	struct rte_cryptodev_config dev_config;