From patchwork Tue Sep 7 11:45:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 98175 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4116FA0C41; Tue, 7 Sep 2021 13:45:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 27CDC410ED; Tue, 7 Sep 2021 13:45:58 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id C3DC5410EC for ; Tue, 7 Sep 2021 13:45:56 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10099"; a="281189545" X-IronPort-AV: E=Sophos;i="5.85,274,1624345200"; d="scan'208";a="281189545" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2021 04:45:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,274,1624345200"; d="scan'208";a="448967817" Received: from silpixa00400308.ir.intel.com ([10.237.214.190]) by orsmga002.jf.intel.com with ESMTP; 07 Sep 2021 04:45:54 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, roy.fan.zhang@intel.com, Arek Kusztal Date: Tue, 7 Sep 2021 12:45:38 +0100 Message-Id: <20210907114538.29258-1-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-dev] [PATCH] crypto/qat: enable aes xts in gen4 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable AES-XTS legacy mode in gen4 devices of Intel QuickAssist Technology PMD. Signed-off-by: Arek Kusztal --- drivers/crypto/qat/qat_sym_capabilities.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h index cfb176ca94..636cfc2817 100644 --- a/drivers/crypto/qat/qat_sym_capabilities.h +++ b/drivers/crypto/qat/qat_sym_capabilities.h @@ -1199,6 +1199,26 @@ } \ }, } \ }, } \ + }, \ + { /* AES XTS */ \ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \ + {.sym = { \ + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, \ + {.cipher = { \ + .algo = RTE_CRYPTO_CIPHER_AES_XTS, \ + .block_size = 16, \ + .key_size = { \ + .min = 32, \ + .max = 64, \ + .increment = 32 \ + }, \ + .iv_size = { \ + .min = 16, \ + .max = 16, \ + .increment = 0 \ + } \ + }, } \ + }, } \ } \