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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.36 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.36; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.36) by CO1NAM11FT051.mail.protection.outlook.com (10.13.174.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:09 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:08 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:05 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:29 +0300 Message-ID: <20210914053833.7760-7-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a890622a-35d6-4ed5-e848-08d977421da2 X-MS-TrafficTypeDiagnostic: BN6PR1201MB0148: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:635; 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CAT:NONE; SFS:(4636009)(376002)(346002)(39860400002)(136003)(396003)(46966006)(36840700001)(6666004)(70206006)(70586007)(5660300002)(47076005)(26005)(16526019)(36860700001)(4326008)(186003)(8676002)(55016002)(356005)(86362001)(107886003)(82310400003)(478600001)(8936002)(7636003)(6916009)(2616005)(426003)(336012)(82740400003)(6286002)(83380400001)(36756003)(1076003)(36906005)(7696005)(54906003)(316002)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:09.7208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a890622a-35d6-4ed5-e848-08d977421da2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0148 Subject: [dpdk-dev] [RFC PATCH 06/10] crypto/mlx5: use OS agnostic functions for UMEM operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" use the functions mlx5_os_umem_reg, mlx5_os_umem_dereg mlx5_os_get_umem_id instead of the glue functions to support UMEM operations on all OSs. Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 14 +++++++------- drivers/crypto/mlx5/mlx5_crypto.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 3dac69f860..ccae113770 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -261,7 +261,7 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id) if (qp->qp_obj != NULL) claim_zero(mlx5_devx_cmd_destroy(qp->qp_obj)); if (qp->umem_obj != NULL) - claim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj)); + claim_zero(mlx5_os_umem_dereg(qp->umem_obj)); if (qp->umem_buf != NULL) rte_free(qp->umem_buf); mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); @@ -682,10 +682,10 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, rte_errno = ENOMEM; goto error; } - qp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx, - (void *)(uintptr_t)qp->umem_buf, - umem_size, - IBV_ACCESS_LOCAL_WRITE); + qp->umem_obj = mlx5_os_umem_reg(priv->ctx, + (void *)(uintptr_t)qp->umem_buf, + umem_size, + IBV_ACCESS_LOCAL_WRITE); if (qp->umem_obj == NULL) { DRV_LOG(ERR, "Failed to register QP umem."); goto error; @@ -705,9 +705,9 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, attr.rq_size = 0; attr.sq_size = RTE_BIT32(log_nb_desc); attr.dbr_umem_valid = 1; - attr.wq_umem_id = qp->umem_obj->umem_id; + attr.wq_umem_id = mlx5_os_get_umem_id(qp->umem_obj); attr.wq_umem_offset = 0; - attr.dbr_umem_id = qp->umem_obj->umem_id; + attr.dbr_umem_id = mlx5_os_get_umem_id(qp->umem_obj); attr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size; qp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr); if (qp->qp_obj == NULL) { diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index d49b0001f0..d5cc509e42 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -45,7 +45,7 @@ struct mlx5_crypto_qp { struct mlx5_devx_cq cq_obj; struct mlx5_devx_obj *qp_obj; struct rte_cryptodev_stats stats; - struct mlx5dv_devx_umem *umem_obj; + void *umem_obj; void *umem_buf; volatile uint32_t *db_rec; struct rte_crypto_op **ops;