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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.35 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.35; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.35) by CO1NAM11FT026.mail.protection.outlook.com (10.13.175.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:11 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:10 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:07 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:30 +0300 Message-ID: <20210914053833.7760-8-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d771d7ed-9b1c-47e1-9a71-08d977421e71 X-MS-TrafficTypeDiagnostic: DM6PR12MB3865: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:28; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(2906002)(8676002)(7696005)(82310400003)(4326008)(7636003)(6666004)(508600001)(336012)(426003)(6286002)(54906003)(36860700001)(316002)(47076005)(55016002)(36906005)(70206006)(83380400001)(2616005)(8936002)(1076003)(86362001)(356005)(26005)(16526019)(5660300002)(186003)(36756003)(6916009)(70586007)(107886003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:11.0874 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d771d7ed-9b1c-47e1-9a71-08d977421e71 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3865 Subject: [dpdk-dev] [RFC PATCH 07/10] crypto/mlx5: use OS agnostic functions for PD operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" use the functions mlx5_os_alloc_pd, mlx5_os_dealloc_pd mlx5_os_get_pdn instead of the glue functions to support PD operations on all OSs. Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 15 ++++++--------- drivers/crypto/mlx5/mlx5_crypto.h | 2 +- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index ccae113770..35319d0115 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -784,7 +784,7 @@ static void mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv) { if (priv->pd != NULL) { - claim_zero(mlx5_glue->dealloc_pd(priv->pd)); + claim_zero(mlx5_os_dealloc_pd(priv->pd)); priv->pd = NULL; } if (priv->uar != NULL) { @@ -801,21 +801,18 @@ mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv) struct mlx5dv_pd pd_info; int ret; - priv->pd = mlx5_glue->alloc_pd(priv->ctx); + priv->pd = mlx5_os_alloc_pd(priv->ctx); if (priv->pd == NULL) { DRV_LOG(ERR, "Failed to allocate PD."); return errno ? -errno : -ENOMEM; } - obj.pd.in = priv->pd; - obj.pd.out = &pd_info; - ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); + ret = mlx5_os_get_pdn(priv->pd, &priv->pdn); if (ret != 0) { - DRV_LOG(ERR, "Fail to get PD object info."); - mlx5_glue->dealloc_pd(priv->pd); + DRV_LOG(ERR, "Fail to get PDN."); + mlx5_os_dealloc_pd(priv->pd); priv->pd = NULL; return -errno; } - priv->pdn = pd_info.pdn; return 0; #else (void)priv; @@ -834,7 +831,7 @@ mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv) priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); if (priv->uar == NULL || priv->uar_addr == NULL) { rte_errno = errno; - claim_zero(mlx5_glue->dealloc_pd(priv->pd)); + claim_zero(mlx5_os_dealloc_pd(priv->pd)); DRV_LOG(ERR, "Failed to allocate UAR."); return -1; } diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index d5cc509e42..91e3f438b8 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -25,7 +25,7 @@ struct mlx5_crypto_priv { volatile uint64_t *uar_addr; uint32_t pdn; /* Protection Domain number. */ uint32_t max_segs_num; /* Maximum supported data segs. */ - struct ibv_pd *pd; + void *pd; struct mlx5_hlist *dek_hlist; /* Dek hash list. */ struct rte_cryptodev_config dev_config; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */