From patchwork Tue Sep 14 05:38:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 98832 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A6B6A0C47; Tue, 14 Sep 2021 07:40:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1EB5C4113C; Tue, 14 Sep 2021 07:40:18 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2042.outbound.protection.outlook.com [40.107.94.42]) by mails.dpdk.org (Postfix) with ESMTP id 859A341124 for ; Tue, 14 Sep 2021 07:40:15 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Zjrhf92F8rbatUx0nr1ChRh9W7wpbiU9T/EB+3K6IdERUDPxIBbH8BV+iwI5wU/n6TJwkr8ChbzBv+mye0py85naHcdSx+nlbIpp5jaAFbSa768Bj/ReNxINjQ8gg6p5M17niPTf9vjM/zPA2P7lx8yEa/Rk/cDpVZ85DboQp2e2xcBJy6AJxHW54G9nmKeLrCkNSFZiphTxMIVHUXsldRdZUpgaDcI+WCtqBa3OyKwQCz5+M2Pigq96B8pGCQ7rMyojjRYIhX1dW3IDImEMGu3aM1PhOVeTMs1IB4a1Q03sg8k9c3XWQi/Jbln+ngrhsmrawf0k9B+KpWS2qVhVrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=BhxJblF3J7t8HSsyBDGwXTbgdMdYz29V1/pUIO/ssEg=; b=h46IWpGnCxRc/rf5FuP1mrrhRLumoqU94f5iyMVWY4iHyec/ynQrB8WKaz7n8zwBYrlyNO7S2DlWDoh32DeSSfaU9ByRJ6lGeNPJKU88tmH0QBWuT/RHaOLaJPfOlrNNDWZPd0lBcUT3DQ5Q+7lOAM6+lW2fpNI3XJVyTT6rrsiDRXvclyf7xq9NxwIjti3gS9TDrGU2N7x++XKQkb/6jjlNIZxsikspmA3PjFR0q+2FcHN0hXw5lMjJxrIjEVULLCC6wtzs74C9VtJ2kYFjX3JDhMtZICBCvSVZRE7QT331MkSoNXLyMEO0dc/F2//UTq/xTiQTX1HjdbTke1z0TA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.32) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BhxJblF3J7t8HSsyBDGwXTbgdMdYz29V1/pUIO/ssEg=; b=OiQbeanfxV9UDmRlP25LLDJcnfIuWnLAlhvlLUQwXhma4Zj9CFjQuNAcCxqGMIPbjvLZF2+bB0I95fP+GAAq/y3/VWbRFlTQYkFEn4jGuafwuGB9bNOwBfRua40JVUqq6Aqh7l0BIHoWIIyGx4HK834iRdov/s+/TIC7kZnDyBU1Fw1beWNGtUUVTT3Txn1G5gKW90iLjheoiIvB9v6F5KmVk5p+hUeL0IZv86dz1l36hCvfGdJOq+cjQ6UcU3Nj2XL+Vg5DouuvqNfGSLH3bqrkuePKPPC8y12mazru8JwyxViFMVjC9qcuG3wa4cO03r7yHXEr6lKEzmgten0r8g== Received: from DM5PR15CA0067.namprd15.prod.outlook.com (2603:10b6:3:ae::29) by CH2PR12MB4921.namprd12.prod.outlook.com (2603:10b6:610:62::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.17; Tue, 14 Sep 2021 05:40:13 +0000 Received: from DM6NAM11FT019.eop-nam11.prod.protection.outlook.com (2603:10b6:3:ae:cafe::76) by DM5PR15CA0067.outlook.office365.com (2603:10b6:3:ae::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.32) smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by DM6NAM11FT019.mail.protection.outlook.com (10.13.172.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:13 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 13 Sep 2021 22:40:13 -0700 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:10 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:31 +0300 Message-ID: <20210914053833.7760-9-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: abaf2a6e-676e-4c14-842a-08d977421fe7 X-MS-TrafficTypeDiagnostic: CH2PR12MB4921: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LoCopUSqIaqb6F4+buodZUK2ryEMgplocTKVQbr4NkctTIuCE+vIhJ0EHhNdu5GBxNnu92QkxjK/0PnAaKy7KAw+scEFcanqFqUIU5+aztaD11DlqhM91qEHmQp3UoullJh4t8JipdHDMyDnIVwriZR4QeapKP2Ien3GNPrIsB/M4xcs2wX1wIIMdhyE65bp4YX+LM1+mM/9TkSHPJFttc4YnKSWWlf7jtktRZcu5qVoLIChg74J/u9x8TttwG6DWlQIGfnA5amo5+qz8HgI7JcdRWPS1Um8BhW/qUIcsj1Ds841TgtzjsOXdIi8avkmC6rZLz18k9Y2gW4DOzZvhc3YkSnAZ2+SokGwL7SCPIeLBtYmaeJ6xl/X3P1/Jo7svasvGvLxbzOhF0UzM1yGU2dbb/RINkKXdug4vH4/dH9tUTyfjYK1Fsrp9szIPlIaNXLDjzyLNg5DqBl+wqGR40ROUvuQGvefetI68Npd4cwRQTCAxQr1QxicPYznX25n/0fOTsLpPSEfTNRaFchIpT1fhOG7OSDgUKdKGch7PQBWMsvHPgl+v9BwK2vQOGkCdMujmmgt7Vw0jp4Bsi3RqOD7rODRpTjJBzv8/ih9J1sbZcVad/qNjVhrSJUZAqx4yyvhNswTtM5kccl6yxjaqAYpBlFEwn7/t2nSS4gcTQtfR0zfWf3P9amaN3pKk6mtrpRZH0ObA4UlG0L9R06Oiw== X-Forefront-Antispam-Report: CIP:216.228.112.32; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid01.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(39860400002)(396003)(346002)(376002)(46966006)(36840700001)(47076005)(5660300002)(2616005)(4326008)(86362001)(8676002)(70586007)(2906002)(186003)(1076003)(82310400003)(16526019)(26005)(36756003)(356005)(8936002)(83380400001)(70206006)(82740400003)(316002)(54906003)(55016002)(7696005)(36860700001)(426003)(107886003)(6916009)(6286002)(336012)(6666004)(7636003)(478600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:13.5309 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abaf2a6e-676e-4c14-842a-08d977421fe7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4921 Subject: [dpdk-dev] [RFC PATCH 08/10] crypto/mlx5: use OS agnostic functions for Verbs operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" use the functions mlx5_os_open_device_context, mlx5_os_get_ctx_device_name mlx5_os_reg_mr mlx5_os_dereg_mr instead of the ib verbs functions and variables to support device operations on all OSs. Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 41 +++++++++++++++++---------------------- drivers/crypto/mlx5/mlx5_crypto.h | 2 +- 2 files changed, 19 insertions(+), 24 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 35319d0115..3f5a6745dc 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -796,9 +796,6 @@ mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv) static int mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv) { -#ifdef HAVE_IBV_FLOW_DV_SUPPORT - struct mlx5dv_obj obj; - struct mlx5dv_pd pd_info; int ret; priv->pd = mlx5_os_alloc_pd(priv->ctx); @@ -814,11 +811,6 @@ mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv) return -errno; } return 0; -#else - (void)priv; - DRV_LOG(ERR, "Cannot get pdn - no DV support."); - return -ENOTSUP; -#endif /* HAVE_IBV_FLOW_DV_SUPPORT */ } static int @@ -964,8 +956,8 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, /* Iterate all the existing mlx5 devices. */ TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next) mlx5_free_mr_by_addr(&priv->mr_scache, - priv->ctx->device->name, - addr, len); + mlx5_os_get_ctx_device_name( + priv->ctx), addr, len); pthread_mutex_unlock(&priv_list_lock); break; case RTE_MEM_EVENT_ALLOC: @@ -977,9 +969,9 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, static int mlx5_crypto_dev_probe(struct rte_device *dev) { - struct ibv_device *ibv; struct rte_cryptodev *crypto_dev; - struct ibv_context *ctx; + void *ctx; + const char *device_name; struct mlx5_devx_obj *login; struct mlx5_crypto_priv *priv; struct mlx5_crypto_devarg_params devarg_prms = { 0 }; @@ -999,15 +991,19 @@ mlx5_crypto_dev_probe(struct rte_device *dev) rte_errno = ENOTSUP; return -rte_errno; } - ibv = mlx5_os_get_ibv_dev(dev); - if (ibv == NULL) - return -rte_errno; - ctx = mlx5_glue->dv_open_device(ibv); + ctx = mlx5_os_open_device_context(dev); if (ctx == NULL) { - DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); + DRV_LOG(ERR, "Failed to open IB device."); rte_errno = ENODEV; return -rte_errno; } + device_name = mlx5_os_get_ctx_device_name(ctx); + if (!device_name) { + DRV_LOG(ERR, "Failed getting device name"); + claim_zero(mlx5_glue->close_device(ctx)); + rte_errno = ENODEV; + return -ENODEV; + } if (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 || attr.crypto == 0 || attr.aes_xts == 0) { DRV_LOG(ERR, "Not enough capabilities to support crypto " @@ -1029,15 +1025,14 @@ mlx5_crypto_dev_probe(struct rte_device *dev) claim_zero(mlx5_glue->close_device(ctx)); return -rte_errno; } - crypto_dev = rte_cryptodev_pmd_create(ibv->name, dev, - &init_params); + crypto_dev = rte_cryptodev_pmd_create(device_name, dev, &init_params); if (crypto_dev == NULL) { - DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name); + DRV_LOG(ERR, "Failed to create device \"%s\".", device_name); claim_zero(mlx5_glue->close_device(ctx)); return -ENODEV; } DRV_LOG(INFO, - "Crypto device %s was created successfully.", ibv->name); + "Crypto device %s was created successfully.", device_name); crypto_dev->dev_ops = &mlx5_crypto_ops; crypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst; crypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst; @@ -1061,8 +1056,8 @@ mlx5_crypto_dev_probe(struct rte_device *dev) rte_errno = ENOMEM; return -rte_errno; } - priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; - priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; + priv->mr_scache.reg_mr_cb = mlx5_os_reg_mr; + priv->mr_scache.dereg_mr_cb = mlx5_os_dereg_mr; priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); priv->max_segs_num = devarg_prms.max_segs_num; priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 91e3f438b8..57461a8a33 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -19,7 +19,7 @@ struct mlx5_crypto_priv { TAILQ_ENTRY(mlx5_crypto_priv) next; - struct ibv_context *ctx; /* Device context. */ + void *ctx; /* Device context. */ struct rte_cryptodev *crypto_dev; void *uar; /* User Access Region. */ volatile uint64_t *uar_addr;