diff mbox series

[v1,1/3] common/cnxk: set key length setting for PDCP algos

Message ID 20210915061103.28375-1-vvelumuri@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series [v1,1/3] common/cnxk: set key length setting for PDCP algos |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Vidya Sagar Velumuri Sept. 15, 2021, 6:11 a.m. UTC 
  Set proper bits in the context based on key length for PDCP

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Comments

Akhil Goyal Sept. 29, 2021, 3:43 p.m. UTC | #1 
> Subject: [PATCH v1 1/3] common/cnxk: set key length setting for PDCP algos
> 
> Set proper bits in the context based on key length for PDCP
> 
> Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
> 
Series
Acked-by: Akhil Goyal <gakhil@marvell.com>

Applied to dpdk-next-crypto

Thanks.
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c
index 03fbc5f2f7..4edbc8e547 100644
--- a/drivers/common/cnxk/roc_se.c
+++ b/drivers/common/cnxk/roc_se.c
@@ -160,6 +160,13 @@  cpt_pdcp_mac_len_set(struct roc_se_zuc_snow3g_ctx *zs_ctx, uint16_t mac_len)
 {
 	roc_se_pdcp_mac_len_type mac_type = 0;
 
+	if (roc_model_is_cn9k()) {
+		if (mac_len != 4) {
+			plt_err("Only mac len 4 is supported on cn9k");
+			return -ENOTSUP;
+		}
+	}
+
 	switch (mac_len) {
 	case 4:
 		mac_type = ROC_SE_PDCP_MAC_LEN_32_BIT;
@@ -230,6 +237,9 @@  roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type,
 		case ROC_SE_ZUC_EIA3:
 			zs_ctx->zuc.otk_ctx.w0.s.alg_type =
 				ROC_SE_PDCP_ALG_TYPE_ZUC;
+			ret = cpt_pdcp_key_type_set(zs_ctx, key_len);
+			if (ret)
+				return ret;
 			ret = cpt_pdcp_mac_len_set(zs_ctx, mac_len);
 			if (ret)
 				return ret;