diff mbox series

[12/12] net/ice/base: update auto generated hardware register

Message ID 20210916095304.3058210-13-qi.z.zhang@intel.com (mailing list archive)
State Accepted
Delegated to: Qi Zhang
Headers show
Series ice base code batch 2 for DPDK 21.11 | expand

Checks

Context Check Description
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/intel-Testing fail Testing issues
ci/Intel-compilation success Compilation OK
ci/github-robot: build success github build: passed
ci/checkpatch warning coding style issues

Commit Message

Zhang, Qi Z Sept. 16, 2021, 9:53 a.m. UTC
Update ice_hw_autogen.h.
Remove duplicated one in ice_nvm.h.
Replace ICE_NVM_ACCESS_GL_HIBA_MAX with GL_HIBA_MAX_INDEX.

Signed-off-by: Scott W Taylor <scott.w.taylor@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_hw_autogen.h | 148 ++++++++++++++------------
 drivers/net/ice/base/ice_nvm.c        |   4 +-
 drivers/net/ice/base/ice_nvm.h        |  13 ---
 3 files changed, 81 insertions(+), 84 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h
index cbca4b0629..10b1116931 100644
--- a/drivers/net/ice/base/ice_hw_autogen.h
+++ b/drivers/net/ice/base/ice_hw_autogen.h
@@ -2,10 +2,20 @@ 
  * Copyright(c) 2001-2021 Intel Corporation
  */
 
-/* Machine-generated file; do not edit */
+/* Machine generated file. Do not edit. */
+
 #ifndef _ICE_HW_AUTOGEN_H_
 #define _ICE_HW_AUTOGEN_H_
 
+#define GL_HIDA(_i)			(0x00082000 + ((_i) * 4))
+#define GL_HIBA(_i)			(0x00081000 + ((_i) * 4))
+#define GL_HICR				0x00082040
+#define GL_HICR_EN			0x00082044
+#define GLGEN_CSR_DEBUG_C		0x00075750
+#define GLNVM_GENS			0x000B6100
+#define GLNVM_FLA			0x000B6108
+#define GL_HIDA_MAX_INDEX		15
+#define GL_HIBA_MAX_INDEX		1023
 #define GL_RDPU_CNTRL				0x00052054 /* Reset Source: CORER */
 #define GL_RDPU_CNTRL_RX_PAD_EN_S		0
 #define GL_RDPU_CNTRL_RX_PAD_EN_M		BIT(0)
@@ -448,8 +458,8 @@ 
 #define PF0INT_OICR_CPM_PAGE_RSV3_M		BIT(23)
 #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S	24
 #define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M	BIT(24)
-#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25
-#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)
+#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S	25
+#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M	BIT(25)
 #define PF0INT_OICR_CPM_PAGE_HMC_ERR_S		26
 #define PF0INT_OICR_CPM_PAGE_HMC_ERR_M		BIT(26)
 #define PF0INT_OICR_CPM_PAGE_PE_PUSH_S		27
@@ -512,8 +522,8 @@ 
 #define PF0INT_OICR_HLP_PAGE_RSV3_M		BIT(23)
 #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S	24
 #define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M	BIT(24)
-#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25
-#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)
+#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S	25
+#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M	BIT(25)
 #define PF0INT_OICR_HLP_PAGE_HMC_ERR_S		26
 #define PF0INT_OICR_HLP_PAGE_HMC_ERR_M		BIT(26)
 #define PF0INT_OICR_HLP_PAGE_PE_PUSH_S		27
@@ -561,8 +571,8 @@ 
 #define PF0INT_OICR_PSM_PAGE_RSV3_M		BIT(23)
 #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S	24
 #define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M	BIT(24)
-#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25
-#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)
+#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S	25
+#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M	BIT(25)
 #define PF0INT_OICR_PSM_PAGE_HMC_ERR_S		26
 #define PF0INT_OICR_PSM_PAGE_HMC_ERR_M		BIT(26)
 #define PF0INT_OICR_PSM_PAGE_PE_PUSH_S		27
@@ -702,8 +712,8 @@ 
 #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M	MAKEMASK(0x1F, 8)
 #define GL_ACL_PROFILE_DWSB_SEL(_i)		(0x00391088 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
 #define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX	15
-#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0
-#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)
+#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S	0
+#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M	MAKEMASK(0xF, 0)
 #define GL_ACL_PROFILE_PF_CFG(_i)		(0x003910C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
 #define GL_ACL_PROFILE_PF_CFG_MAX_INDEX		7
 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S	0
@@ -861,8 +871,8 @@ 
 #define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M	BIT(6)
 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7
 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)
-#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14
-#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)
+#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S	14
+#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M	MAKEMASK(0xFF, 14)
 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S	22
 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M	MAKEMASK(0x3FF, 22)
 #define GLTCLAN_CQ_CNTX0(_CQ)			(0x000F0800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
@@ -2205,8 +2215,8 @@ 
 #define PRTDCB_TX_DSCP2UP_CTL			0x00040980 /* Reset Source: CORER */
 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S	0
 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M	BIT(0)
-#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1
-#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)
+#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S	1
+#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M	MAKEMASK(0x7, 1)
 #define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i)		(0x000409A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */
 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX	7
 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0
@@ -2354,8 +2364,8 @@ 
 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS		0x00099320 /* Reset Source: CORER */
-#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
-#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S	0
+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M	MAKEMASK(0x3FFFF, 0)
 #define TPB_WB_RL_TC_CFG(_i)			(0x00099360 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
 #define TPB_WB_RL_TC_CFG_MAX_INDEX		31
 #define TPB_WB_RL_TC_CFG_TOKENS_S		0
@@ -2420,8 +2430,8 @@ 
 #define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX	2
 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S	0
 #define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M	MAKEMASK(0xF, 0)
-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
-#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S	31
+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M	BIT(31)
 #define GL_ACLEXT_FORCE_PID(_i)			(0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
 #define GL_ACLEXT_FORCE_PID_MAX_INDEX		2
 #define GL_ACLEXT_FORCE_PID_STATIC_PID_S	0
@@ -2614,8 +2624,8 @@ 
 #define GL_PREEXT_FORCE_L1CDID_MAX_INDEX	2
 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S	0
 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M	MAKEMASK(0xF, 0)
-#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
-#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S	31
+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M	BIT(31)
 #define GL_PREEXT_FORCE_PID(_i)			(0x0020F000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
 #define GL_PREEXT_FORCE_PID_MAX_INDEX		2
 #define GL_PREEXT_FORCE_PID_STATIC_PID_S	0
@@ -2816,8 +2826,8 @@ 
 #define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX	2
 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S	0
 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M	MAKEMASK(0xF, 0)
-#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
-#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S	31
+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M	BIT(31)
 #define GL_PSTEXT_FORCE_PID(_i)			(0x0020E000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
 #define GL_PSTEXT_FORCE_PID_MAX_INDEX		2
 #define GL_PSTEXT_FORCE_PID_STATIC_PID_S	0
@@ -2984,10 +2994,10 @@ 
 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)
 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8
 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)
-#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12
-#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)
-#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14
-#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)
+#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S	12
+#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M	MAKEMASK(0x3, 12)
+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S	14
+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M	MAKEMASK(0x3, 14)
 #define GLFLXP_RX_CMD_PROTIDS(_i, _j)		(0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 */ /* Reset Source: CORER */
 #define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX		255
 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S	0
@@ -3066,8 +3076,8 @@ 
 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M	MAKEMASK(0xFF, 0)
 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S	8
 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M	MAKEMASK(0x1F, 8)
-#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16
-#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)
+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S	16
+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M	MAKEMASK(0xFF, 16)
 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S	24
 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M	MAKEMASK(0x1F, 24)
 #define QRXFLXP_CNTXT(_QRX)			(0x00480000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
@@ -3280,18 +3290,18 @@ 
 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9
 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
-#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
-#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
+#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S	14
+#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M	MAKEMASK(0x3, 14)
 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S	16
 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M	MAKEMASK(0xF, 16)
-#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
-#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
+#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S	20
+#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M	BIT(20)
 #define GLGEN_ANA_TX_ABORT_PTYPE		0x0020D21C /* Reset Source: CORER */
 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S	0
 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M	MAKEMASK(0x3FF, 0)
 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT	0x0020D208 /* Reset Source: CORER */
-#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
-#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S	0
+#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M	MAKEMASK(0xFF, 0)
 #define GLGEN_ANA_TX_CFG_CTRL			0x0020D104 /* Reset Source: CORER */
 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S	0
 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M	MAKEMASK(0x3FFFF, 0)
@@ -3317,10 +3327,10 @@ 
 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S	0
 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT	0x0020D15C /* Reset Source: CORER */
-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0
-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1
-#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S	0
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M	BIT(0)
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S	1
+#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M	MAKEMASK(0x7, 1)
 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4
 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
 #define GLGEN_ANA_TX_CFG_WRDATA			0x0020D108 /* Reset Source: CORER */
@@ -3639,8 +3649,8 @@ 
 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S	0
 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLHMC_FWSDDATAHIGH_FPMAT		0x00102078 /* Reset Source: CORER */
-#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
-#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S	0
+#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLHMC_FWSDDATALOW			0x00522074 /* Reset Source: CORER */
 #define GLHMC_FWSDDATALOW_PMSDVALID_S		0
 #define GLHMC_FWSDDATALOW_PMSDVALID_M		BIT(0)
@@ -4038,8 +4048,8 @@ 
 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_M		MAKEMASK(0x1FFFFFFF, 0)
 #define GLHMC_VFPEOOISCBASE(_i)			(0x0052E600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
 #define GLHMC_VFPEOOISCBASE_MAX_INDEX		31
-#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0
-#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S	0
+#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLHMC_VFPEOOISCCNT(_i)			(0x0052E700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
 #define GLHMC_VFPEOOISCCNT_MAX_INDEX		31
 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S	0
@@ -4086,8 +4096,8 @@ 
 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLHMC_VFPERRFFLBASE(_i)			(0x0052EA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
 #define GLHMC_VFPERRFFLBASE_MAX_INDEX		31
-#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0
-#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S	0
+#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLHMC_VFPETIMERBASE(_i)			(0x0052DA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
 #define GLHMC_VFPETIMERBASE_MAX_INDEX		31
 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S	0
@@ -4114,8 +4124,8 @@ 
 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLHMC_VFSDDATAHIGH_FPMAT(_i)		(0x00108200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
 #define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX	31
-#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
-#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S	0
+#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLHMC_VFSDDATALOW(_i)			(0x00528100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
 #define GLHMC_VFSDDATALOW_MAX_INDEX		31
 #define GLHMC_VFSDDATALOW_PMSDVALID_S		0
@@ -4221,8 +4231,8 @@ 
 #define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M	BIT(7)
 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S	8
 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M	MAKEMASK(0xF, 8)
-#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16
-#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
+#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S	16
+#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M	MAKEMASK(0x1F, 16)
 #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S	31
 #define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M	BIT(31)
 #define PFHMC_PDINV				0x00520300 /* Reset Source: PFR */
@@ -4309,8 +4319,8 @@ 
 #define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)
 #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12
 #define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)
-#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13
-#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)
+#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S	13
+#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M	BIT(13)
 #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14
 #define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)
 #define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15
@@ -5205,10 +5215,10 @@ 
 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL	0x001E36C0 /* Reset Source: GLOBR */
 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0
 #define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1	0x001E3220 /* Reset Source: GLOBR */
 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0
 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)
-#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2	0x001E3240 /* Reset Source: GLOBR */
 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0
 #define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)
 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE		0x001E3180 /* Reset Source: GLOBR */
@@ -5309,10 +5319,10 @@ 
 #define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M	BIT(17)
 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S	18
 #define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M	BIT(18)
-#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19
-#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)
-#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20
-#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)
+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S	19
+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M	BIT(19)
+#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S	20
+#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M	BIT(20)
 #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S	21
 #define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M	BIT(21)
 #define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22
@@ -5331,8 +5341,8 @@ 
 #define GL_MDCK_TX_TDPU				0x00049348 /* Reset Source: CORER */
 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S	0
 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M	BIT(0)
-#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
-#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S	1
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M	BIT(1)
 #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S	2
 #define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M	BIT(2)
 #define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S	3
@@ -5345,8 +5355,8 @@ 
 #define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
 #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S	7
 #define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M	BIT(7)
-#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
-#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S	8
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M	BIT(8)
 #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
 #define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
 #define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S	10
@@ -5428,8 +5438,8 @@ 
 #define VP_MDET_TX_TDPU_VALID_M			BIT(0)
 #define GENERAL_MNG_FW_DBG_CSR(_i)		(0x000B6180 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: POR */
 #define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX	9
-#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0
-#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)
+#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S	0
+#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GL_FWRESETCNT				0x00083100 /* Reset Source: POR */
 #define GL_FWRESETCNT_FWRESETCNT_S		0
 #define GL_FWRESETCNT_FWRESETCNT_M		MAKEMASK(0xFFFFFFFF, 0)
@@ -5841,8 +5851,8 @@ 
 #define GL_XLR_MARKER_TRIG_RCU_PRS		0x002001C0 /* Reset Source: CORER */
 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S	0
 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M	MAKEMASK(0x3FF, 0)
-#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10
-#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)
+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S	10
+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M	MAKEMASK(0x3, 10)
 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S	12
 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M	MAKEMASK(0x7, 12)
 #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S	16
@@ -6721,11 +6731,11 @@ 
 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S	0
 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLPES_TCPRXFOURHOLEHI			0x0055E03C /* Reset Source: CORER */
-#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0
-#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)
+#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S	0
+#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M	MAKEMASK(0xFFFFFF, 0)
 #define GLPES_TCPRXFOURHOLELO			0x0055E038 /* Reset Source: CORER */
-#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0
-#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
+#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S	0
+#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M	MAKEMASK(0xFFFFFFFF, 0)
 #define GLPES_TCPRXONEHOLEHI			0x0055E024 /* Reset Source: CORER */
 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S	0
 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M	MAKEMASK(0xFFFFFF, 0)
@@ -8206,7 +8216,7 @@ 
 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S	0
 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M	MAKEMASK(0xFFFFFFFF, 0)
 #define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i)	(0x00099094 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
-#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63
+#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX	63
 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S	0
 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M	MAKEMASK(0xFFFFFFFF, 0)
 #define EMP_SWT_PRUNIND				0x00204020 /* Reset Source: CORER */
@@ -9448,5 +9458,5 @@ 
 #define VFPE_WQEALLOC1_PEQPID_M			MAKEMASK(0x3FFFF, 0)
 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_S		20
 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M		MAKEMASK(0xFFF, 20)
+#endif /* !_ICE_HW_AUTOGEN_H_ */
 
-#endif
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 2b76a11e22..7860006206 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -1214,11 +1214,11 @@  ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
 		break;
 	}
 
-	for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
+	for (i = 0; i <= GL_HIDA_MAX_INDEX; i++)
 		if (offset == (u32)GL_HIDA(i))
 			return ICE_SUCCESS;
 
-	for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
+	for (i = 0; i <= GL_HIBA_MAX_INDEX; i++)
 		if (offset == (u32)GL_HIBA(i))
 			return ICE_SUCCESS;
 
diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h
index af18344cf8..52e8853b19 100644
--- a/drivers/net/ice/base/ice_nvm.h
+++ b/drivers/net/ice/base/ice_nvm.h
@@ -67,19 +67,6 @@  union ice_nvm_access_data {
 	struct ice_nvm_features drv_features; /* NVM features */
 };
 
-/* NVM Access registers */
-#define GL_HIDA(_i)			(0x00082000 + ((_i) * 4))
-#define GL_HIBA(_i)			(0x00081000 + ((_i) * 4))
-#define GL_HICR				0x00082040
-#define GL_HICR_EN			0x00082044
-#define GLGEN_CSR_DEBUG_C		0x00075750
-#define GLPCI_LBARCTRL			0x0009DE74
-#define GLNVM_GENS			0x000B6100
-#define GLNVM_FLA			0x000B6108
-
-#define ICE_NVM_ACCESS_GL_HIDA_MAX	15
-#define ICE_NVM_ACCESS_GL_HIBA_MAX	1023
-
 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);
 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);
 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);