From patchwork Thu Sep 16 09:52:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 99013 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5296BA0C41; Thu, 16 Sep 2021 11:50:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1500941121; Thu, 16 Sep 2021 11:50:15 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id ED84F410E3 for ; Thu, 16 Sep 2021 11:50:12 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10108"; a="222185863" X-IronPort-AV: E=Sophos;i="5.85,298,1624345200"; d="scan'208";a="222185863" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 02:50:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,298,1624345200"; d="scan'208";a="509246944" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 16 Sep 2021 02:50:10 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang , Anirudh Venkataramanan Date: Thu, 16 Sep 2021 17:52:58 +0800 Message-Id: <20210916095304.3058210-7-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210916095304.3058210-1-qi.z.zhang@intel.com> References: <20210916095304.3058210-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 06/12] net/ice/base: allow tool access to MNG register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" E810-T supports signed netlists and to support this, the NVM update tool needs to be able to read the GL_MNG_DEF_DEVID register. Add said register to the allowlist in ice_validate_nvm_rw_reg. Signed-off-by: Anirudh Venkataramanan Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_nvm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index aeb4da9ed1..2b76a11e22 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -4,6 +4,8 @@ #include "ice_common.h" +#define GL_MNG_DEF_DEVID 0x000B611C + /** * ice_aq_read_nvm * @hw: pointer to the HW struct @@ -1203,6 +1205,7 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd) case GLGEN_CSR_DEBUG_C: case GLGEN_RSTAT: case GLPCI_LBARCTRL: + case GL_MNG_DEF_DEVID: case GLNVM_GENS: case GLNVM_FLA: case PF_FUNC_RID: