From patchwork Fri Sep 17 11:02:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 99130 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CF99FA0C46; Fri, 17 Sep 2021 13:02:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C342B41187; Fri, 17 Sep 2021 13:00:11 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 8ED1340E01 for ; Fri, 17 Sep 2021 13:00:08 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="286458787" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="286458787" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 04:00:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="699441204" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga006.fm.intel.com with ESMTP; 17 Sep 2021 04:00:06 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang Date: Fri, 17 Sep 2021 19:02:42 +0800 Message-Id: <20210917110242.3127658-21-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210917110242.3127658-1-qi.z.zhang@intel.com> References: <20210917110242.3127658-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 20/20] net/ice/base: add API for parser profile initialization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add API ice_parser_profile_init to init a parser profile base on a parser result and a mask buffer. The ice_parser_profile can feed to low level FXP engine to create HW profile / field vector directly. Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_parser.c | 112 ++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_parser.h | 24 +++++++ 2 files changed, 136 insertions(+) diff --git a/drivers/net/ice/base/ice_parser.c b/drivers/net/ice/base/ice_parser.c index c8272cb9c2..9180b358eb 100644 --- a/drivers/net/ice/base/ice_parser.c +++ b/drivers/net/ice/base/ice_parser.c @@ -442,3 +442,115 @@ enum ice_status ice_parser_ecpri_tunnel_set(struct ice_parser *psr, { return _tunnel_port_set(psr, "TNL_UDP_ECPRI", udp_port, on); } + +static bool _nearest_proto_id(struct ice_parser_result *rslt, u16 offset, + u8 *proto_id, u16 *proto_off) +{ + u16 dist = 0xffff; + u8 p = 0; + int i; + + for (i = 0; i < rslt->po_num; i++) { + if (offset < rslt->po[i].offset) + continue; + if (offset - rslt->po[i].offset < dist) { + p = rslt->po[i].proto_id; + dist = offset - rslt->po[i].offset; + } + } + + if (dist % 2) + return false; + + *proto_id = p; + *proto_off = dist; + + return true; +} + +/** default flag mask to cover GTP_EH_PDU, GTP_EH_PDU_LINK and TUN2 + * In future, the flag masks should learn from DDP + */ +#define ICE_KEYBUILD_FLAG_MASK_DEFAULT_SW 0x4002 +#define ICE_KEYBUILD_FLAG_MASK_DEFAULT_ACL 0x0000 +#define ICE_KEYBUILD_FLAG_MASK_DEFAULT_FD 0x6080 +#define ICE_KEYBUILD_FLAG_MASK_DEFAULT_RSS 0x6010 + +/** + * ice_parser_profile_init - initialize a FXP profile base on parser result + * @rslt: a instance of a parser result + * @pkt_buf: packet data buffer + * @pkt_msk: packet mask buffer + * @pkt_len: packet length + * @blk: FXP pipeline stage + * @prefix_match: match protocol stack exactly or only prefix + * @prof: input/output parameter to save the profile + */ +enum ice_status ice_parser_profile_init(struct ice_parser_result *rslt, + const u8 *pkt_buf, const u8 *msk_buf, + int buf_len, enum ice_block blk, + bool prefix_match, + struct ice_parser_profile *prof) +{ + u8 proto_id = 0xff; + u16 proto_off = 0; + u16 off; + + ice_memset(prof, 0, sizeof(*prof), ICE_NONDMA_MEM); + ice_set_bit(rslt->ptype, prof->ptypes); + if (blk == ICE_BLK_SW) { + prof->flags = rslt->flags_sw; + prof->flags_msk = ICE_KEYBUILD_FLAG_MASK_DEFAULT_SW; + } else if (blk == ICE_BLK_ACL) { + prof->flags = rslt->flags_acl; + prof->flags_msk = ICE_KEYBUILD_FLAG_MASK_DEFAULT_ACL; + } else if (blk == ICE_BLK_FD) { + prof->flags = rslt->flags_fd; + prof->flags_msk = ICE_KEYBUILD_FLAG_MASK_DEFAULT_FD; + } else if (blk == ICE_BLK_RSS) { + prof->flags = rslt->flags_rss; + prof->flags_msk = ICE_KEYBUILD_FLAG_MASK_DEFAULT_RSS; + } else { + return ICE_ERR_PARAM; + } + + for (off = 0; off < buf_len - 1; off++) { + if (msk_buf[off] == 0 && msk_buf[off + 1] == 0) + continue; + if (!_nearest_proto_id(rslt, off, &proto_id, &proto_off)) + continue; + if (prof->fv_num >= 32) + return ICE_ERR_PARAM; + + prof->fv[prof->fv_num].proto_id = proto_id; + prof->fv[prof->fv_num].offset = proto_off; + prof->fv[prof->fv_num].spec = *(const u16 *)&pkt_buf[off]; + prof->fv[prof->fv_num].msk = *(const u16 *)&msk_buf[off]; + prof->fv_num++; + } + + return ICE_SUCCESS; +} + +/** + * ice_parser_profile_dump - dump an FXP profile info + * @hw: pointer to the hardware structure + * @prof: profile info to dump + */ +void ice_parser_profile_dump(struct ice_hw *hw, struct ice_parser_profile *prof) +{ + u16 i; + + ice_info(hw, "ptypes:\n"); + for (i = 0; i < ICE_FLOW_PTYPE_MAX; i++) + if (ice_is_bit_set(prof->ptypes, i)) + ice_info(hw, "\t%d\n", i); + + for (i = 0; i < prof->fv_num; i++) + ice_info(hw, "proto = %d, offset = %d spec = 0x%04x, mask = 0x%04x\n", + prof->fv[i].proto_id, prof->fv[i].offset, + prof->fv[i].spec, prof->fv[i].msk); + + ice_info(hw, "flags = 0x%04x\n", prof->flags); + ice_info(hw, "flags_msk = 0x%04x\n", prof->flags_msk); +} diff --git a/drivers/net/ice/base/ice_parser.h b/drivers/net/ice/base/ice_parser.h index 5c77d7d98c..690144d77b 100644 --- a/drivers/net/ice/base/ice_parser.h +++ b/drivers/net/ice/base/ice_parser.h @@ -86,4 +86,28 @@ struct ice_parser_result { enum ice_status ice_parser_run(struct ice_parser *psr, const u8 *pkt_buf, int pkt_len, struct ice_parser_result *rslt); void ice_parser_result_dump(struct ice_hw *hw, struct ice_parser_result *rslt); + +struct ice_parser_fv { + u8 proto_id; /* hardware protocol ID */ + u16 offset; /* offset from the start of the protocol header */ + u16 spec; /* 16 bits pattern to match */ + u16 msk; /* 16 bits pattern mask */ +}; + +struct ice_parser_profile { + struct ice_parser_fv fv[48]; /* field vector arrary */ + int fv_num; /* field vector number must <= 48 */ + u16 flags; /* 16 bits key builder flag */ + u16 flags_msk; /* key builder flag masker */ + /* 1024 bits PTYPE bitmap */ + ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX); +}; + +enum ice_status ice_parser_profile_init(struct ice_parser_result *rslt, + const u8 *pkt_buf, const u8 *msk_buf, + int buf_len, enum ice_block blk, + bool prefix_match, + struct ice_parser_profile *prof); +void ice_parser_profile_dump(struct ice_hw *hw, + struct ice_parser_profile *prof); #endif /* _ICE_PARSER_H_ */