From patchwork Tue Sep 21 11:00:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 99346 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CC84A0C4C; Tue, 21 Sep 2021 13:00:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 33F6D40683; Tue, 21 Sep 2021 13:00:57 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8E2FD4003C for ; Tue, 21 Sep 2021 13:00:55 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18KMaovk005379 for ; Tue, 21 Sep 2021 04:00:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=IrY9LStoRtgq+a7x8+Q5YhWnG/kr80Yo183Cc0Nnl3Y=; b=JQ/ThE02JEtOAgKQtRXZjtfSqtYCAAdXiy+MuPGheZinfbSwD02GOYwACM4/7+yQfAV6 l+eSeewwXZxhmu0c6VB1cAUzBMG7SKsLxCaRzzJ0xR9Pfe2gIhYZQTS8pxetmMLatAec DwDz1XbC7ZBQvmSePF4kRz5UFbDrN71/Xhfo0OMmaDjZGA1NTtybMCMAqAOgkpBS2aj0 LAvdUwRX+qmLLb38Gxo0+Z4EJywGBjq7omIuBnvFjX89HcOln/HtnnuUG4Trqxj3L3cr JyNEH8jRXUk8Fu5Upsb6jDIpjPY8KCh1IYDyXOFdgg2atIxZmB4oeflfCmbqiMthRrMj 7Q== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3b7384hvr1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 21 Sep 2021 04:00:54 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 21 Sep 2021 04:00:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 21 Sep 2021 04:00:52 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id CA5D93F70A1; Tue, 21 Sep 2021 04:00:50 -0700 (PDT) From: Harman Kalra To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Harman Kalra Date: Tue, 21 Sep 2021 16:30:37 +0530 Message-ID: <20210921110038.115560-1-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Proofpoint-GUID: fmPp3reApBx4DQEECPaibSINGXWy3SAo X-Proofpoint-ORIG-GUID: fmPp3reApBx4DQEECPaibSINGXWy3SAo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-21_01,2021-09-20_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 1/2] common/cnxk: clear rvum interrupts X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As per an known HW issue RVUM interrupts may get dropped, If an RVUM interrupt event occurs when PCCPF_XXX_MSIX_CAP_HDR[MSIXEN]=0 then no interrupt is triggered, which is expected. But after MSIXEN is set to 1, subsequently if same interrupts event occurs again, still no interrupt will be triggered. As a workaround, all RVUM interrupt lines should be cleared between MSIXEN=0 and MSIXEN=1. Signed-off-by: Harman Kalra --- drivers/common/cnxk/roc_dev.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c index 4e204373dc..ce6980cbe4 100644 --- a/drivers/common/cnxk/roc_dev.c +++ b/drivers/common/cnxk/roc_dev.c @@ -884,6 +884,38 @@ vf_flr_register_irqs(struct plt_pci_device *pci_dev, struct dev *dev) return 0; } +static void +clear_rvum_interrupts(struct dev *dev) +{ + uint64_t intr; + int i; + + if (dev_is_vf(dev)) { + /* Clear VF mbox interrupt */ + intr = plt_read64(dev->bar2 + RVU_VF_INT); + if (intr) + plt_write64(intr, dev->bar2 + RVU_VF_INT); + } else { + /* Clear AF PF interrupt line */ + intr = plt_read64(dev->bar2 + RVU_PF_INT); + if (intr) + plt_write64(intr, dev->bar2 + RVU_PF_INT); + for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) { + /* Clear MBOX interrupts */ + intr = plt_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(i)); + if (intr) + plt_write64(intr, + dev->bar2 + + RVU_PF_VFPF_MBOX_INTX(i)); + /* Clear VF FLR interrupts */ + intr = plt_read64(dev->bar2 + RVU_PF_VFFLR_INTX(i)); + if (intr) + plt_write64(intr, + dev->bar2 + RVU_PF_VFFLR_INTX(i)); + } + } +} + int dev_active_vfs(struct dev *dev) { @@ -1090,6 +1122,9 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev) intr_offset = RVU_PF_INT; } + /* Clear all RVUM interrupts */ + clear_rvum_interrupts(dev); + /* Initialize the local mbox */ rc = mbox_init(&dev->mbox_local, mbox, bar2, direction, 1, intr_offset); if (rc)