diff mbox series

crypto/cnxk: add max queue pairs limit devargs

Message ID 20210930132043.24890-1-adwivedi@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series crypto/cnxk: add max queue pairs limit devargs |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/github-robot: build success github build: passed
ci/iol-spell-check-testing warning Testing issues
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing fail Testing issues
ci/iol-x86_64-compile-testing fail Testing issues
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS

Commit Message

Ankur Dwivedi Sept. 30, 2021, 1:20 p.m. UTC 
  Adds max queue pairs limit devargs for crypto cnxk driver. This
can be used to set a limit on the number of maximum queue pairs
supported by the device. The default value is 63.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Reviewed-by: Anoob Joseph <anoobj@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
---
 doc/guides/cryptodevs/cnxk.rst               | 15 +++++
 drivers/crypto/cnxk/cn10k_cryptodev.c        |  7 +++
 drivers/crypto/cnxk/cn9k_cryptodev.c         |  7 +++
 drivers/crypto/cnxk/cnxk_cryptodev.h         |  2 +
 drivers/crypto/cnxk/cnxk_cryptodev_devargs.c | 61 ++++++++++++++++++++
 drivers/crypto/cnxk/cnxk_cryptodev_ops.c     |  5 +-
 drivers/crypto/cnxk/meson.build              |  1 +
 7 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/cnxk/cnxk_cryptodev_devargs.c

Comments

Akhil Goyal Oct. 16, 2021, 1:35 p.m. UTC | #1 
> Adds max queue pairs limit devargs for crypto cnxk driver. This
> can be used to set a limit on the number of maximum queue pairs
> supported by the device. The default value is 63.
> 
> Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
> Reviewed-by: Anoob Joseph <anoobj@marvell.com>
> Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> ---
Applied to dpdk-next-crypto

Thanks.
diff mbox series

Patch

diff --git a/doc/guides/cryptodevs/cnxk.rst b/doc/guides/cryptodevs/cnxk.rst
index 752316fd37..85171a50a6 100644
--- a/doc/guides/cryptodevs/cnxk.rst
+++ b/doc/guides/cryptodevs/cnxk.rst
@@ -158,6 +158,21 @@  Bind the CPT VF device to the vfio_pci driver:
     ./usertools/dpdk-devbind.py -u 0002:20:00.1
     ./usertools/dpdk-devbind.py -b vfio-pci 0002:20:00.1
 
+Runtime Config Options
+----------------------
+
+- ``Maximum queue pairs limit`` (default ``63``)
+
+   The number of maximum queue pairs supported by the device, can be limited
+   during runtime by using ``max_qps_limit`` ``devargs`` parameter.
+
+   For example::
+
+      -a 0002:20:00.1,max_qps_limit=4
+
+   With the above configuration, the number of maximum queue pairs supported
+   by the device is limited to 4.
+
 Debugging Options
 -----------------
 
diff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c
index 012eb0c051..869d322d9b 100644
--- a/drivers/crypto/cnxk/cn10k_cryptodev.c
+++ b/drivers/crypto/cnxk/cn10k_cryptodev.c
@@ -68,6 +68,13 @@  cn10k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		roc_cpt->pci_dev = pci_dev;
+
+		rc = cnxk_cpt_parse_devargs(dev->device->devargs, vf);
+		if (rc) {
+			plt_err("Failed to parse devargs rc=%d", rc);
+			goto pmd_destroy;
+		}
+
 		rc = roc_cpt_dev_init(roc_cpt);
 		if (rc) {
 			plt_err("Failed to initialize roc cpt rc=%d", rc);
diff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c
index 6b8cb01a12..54df06eec0 100644
--- a/drivers/crypto/cnxk/cn9k_cryptodev.c
+++ b/drivers/crypto/cnxk/cn9k_cryptodev.c
@@ -68,6 +68,13 @@  cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		roc_cpt->pci_dev = pci_dev;
+
+		rc = cnxk_cpt_parse_devargs(dev->device->devargs, vf);
+		if (rc) {
+			plt_err("Failed to parse devargs rc=%d", rc);
+			goto pmd_destroy;
+		}
+
 		rc = roc_cpt_dev_init(roc_cpt);
 		if (rc) {
 			plt_err("Failed to initialize roc cpt rc=%d", rc);
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h
index 8e051fa0fa..cfb9d291a9 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev.h
+++ b/drivers/crypto/cnxk/cnxk_cryptodev.h
@@ -25,9 +25,11 @@  struct cnxk_cpt_vf {
 	struct rte_security_capability sec_caps[CNXK_SEC_MAX_CAPS];
 	uint64_t cnxk_fpm_iova[CNXK_AE_EC_ID_MAX];
 	struct roc_ae_ec_group *ec_grp[CNXK_AE_EC_ID_MAX];
+	uint16_t max_qps_limit;
 };
 
 uint64_t cnxk_cpt_default_ff_get(void);
 int cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt);
+int cnxk_cpt_parse_devargs(struct rte_devargs *devargs, struct cnxk_cpt_vf *vf);
 
 #endif /* _CNXK_CRYPTODEV_H_ */
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_devargs.c b/drivers/crypto/cnxk/cnxk_cryptodev_devargs.c
new file mode 100644
index 0000000000..c3e9bdb2d1
--- /dev/null
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_devargs.c
@@ -0,0 +1,61 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include <rte_devargs.h>
+
+#include "cnxk_cryptodev.h"
+
+#define CNXK_MAX_QPS_LIMIT     "max_qps_limit"
+#define CNXK_MAX_QPS_LIMIT_MIN 1
+#define CNXK_MAX_QPS_LIMIT_MAX (ROC_CPT_MAX_LFS - 1)
+
+static int
+parse_max_qps_limit(const char *key, const char *value, void *extra_args)
+{
+	RTE_SET_USED(key);
+	uint32_t val;
+
+	val = atoi(value);
+
+	if (val < CNXK_MAX_QPS_LIMIT_MIN || val > CNXK_MAX_QPS_LIMIT_MAX)
+		return -EINVAL;
+
+	*(uint16_t *)extra_args = val;
+
+	return 0;
+}
+
+int
+cnxk_cpt_parse_devargs(struct rte_devargs *devargs, struct cnxk_cpt_vf *vf)
+{
+	uint16_t max_qps_limit = CNXK_MAX_QPS_LIMIT_MAX;
+	struct rte_kvargs *kvlist;
+	int rc;
+
+	if (devargs == NULL)
+		goto null_devargs;
+
+	kvlist = rte_kvargs_parse(devargs->args, NULL);
+	if (kvlist == NULL)
+		goto exit;
+
+	rc = rte_kvargs_process(kvlist, CNXK_MAX_QPS_LIMIT,
+				&parse_max_qps_limit, &max_qps_limit);
+	if (rc < 0) {
+		plt_err("max_qps_limit should in the range <%d-%d>",
+			CNXK_MAX_QPS_LIMIT_MIN, CNXK_MAX_QPS_LIMIT_MAX);
+		rte_kvargs_free(kvlist);
+		goto exit;
+	}
+	rte_kvargs_free(kvlist);
+
+null_devargs:
+	vf->max_qps_limit = max_qps_limit;
+	return 0;
+
+exit:
+	return -EINVAL;
+}
+
+RTE_PMD_REGISTER_PARAM_STRING(crypto_cnxk, CNXK_MAX_QPS_LIMIT "=<1-63>");
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index 41d8fe49e1..e49f826225 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -150,7 +150,10 @@  cnxk_cpt_dev_info_get(struct rte_cryptodev *dev,
 	struct cnxk_cpt_vf *vf = dev->data->dev_private;
 	struct roc_cpt *roc_cpt = &vf->cpt;
 
-	info->max_nb_queue_pairs = roc_cpt->nb_lf_avail;
+	info->max_nb_queue_pairs =
+		RTE_MIN(roc_cpt->nb_lf_avail, vf->max_qps_limit);
+	plt_cpt_dbg("max_nb_queue_pairs %u", info->max_nb_queue_pairs);
+
 	info->feature_flags = cnxk_cpt_default_ff_get();
 	info->capabilities = cnxk_crypto_capabilities_get(vf);
 	info->sym.max_nb_sessions = 0;
diff --git a/drivers/crypto/cnxk/meson.build b/drivers/crypto/cnxk/meson.build
index 437d208b5a..024109f7e9 100644
--- a/drivers/crypto/cnxk/meson.build
+++ b/drivers/crypto/cnxk/meson.build
@@ -17,6 +17,7 @@  sources = files(
         'cn10k_ipsec.c',
         'cnxk_cryptodev.c',
         'cnxk_cryptodev_capabilities.c',
+        'cnxk_cryptodev_devargs.c',
         'cnxk_cryptodev_ops.c',
         'cnxk_cryptodev_sec.c',
 )