diff mbox series

[v2,09/28] common/cnxk: dump CPT LF registers on error intr

Message ID 20210930170113.29030-10-ndabilpuram@marvell.com (mailing list archive)
State Changes Requested, archived
Delegated to: Jerin Jacob
Headers show
Series net/cnxk: support for inline ipsec | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram Sept. 30, 2021, 5 p.m. UTC 
Dump CPT LF registers on error interrupt for debugging
purpose.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_cpt.c       |  5 ++++-
 drivers/common/cnxk/roc_cpt_debug.c | 32 ++++++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_cpt_priv.h  |  1 +
 3 files changed, 35 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 48a378b..6ddbaa2 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -51,6 +51,9 @@  cpt_lf_misc_irq(void *param)
 
 	plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
 
+	/* Dump lf registers */
+	cpt_lf_print(lf);
+
 	/* Clear interrupt */
 	plt_write64(intr, lf->rbase + CPT_LF_MISC_INT);
 }
@@ -203,7 +206,7 @@  cpt_lf_dump(struct roc_cpt_lf *lf)
 	plt_cpt_dbg("CPT LF REG:");
 	plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL,
 		    plt_read64(lf->rbase + CPT_LF_CTL));
-	plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG,
+	plt_cpt_dbg("LF_INPROG[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG,
 		    plt_read64(lf->rbase + CPT_LF_INPROG));
 
 	plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE,
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index a6c9004..847d969 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -157,11 +157,40 @@  roc_cpt_afs_print(struct roc_cpt *roc_cpt)
 	return 0;
 }
 
-static void
+void
 cpt_lf_print(struct roc_cpt_lf *lf)
 {
 	uint64_t reg_val;
 
+	reg_val = plt_read64(lf->rbase + CPT_LF_Q_BASE);
+	plt_print("    CPT_LF_Q_BASE:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_Q_SIZE);
+	plt_print("    CPT_LF_Q_SIZE:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_Q_INST_PTR);
+	plt_print("    CPT_LF_Q_INST_PTR:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR);
+	plt_print("    CPT_LF_Q_GRP_PTR:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTL);
+	plt_print("    CPT_LF_CTL:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
+	plt_print("    CPT_LF_MISC_INT_ENA_W1S:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT);
+	plt_print("    CPT_LF_MISC_INT:\t%016lx", reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_INPROG);
+	plt_print("    CPT_LF_INPROG:\t%016lx", reg_val);
+
+	if (roc_model_is_cn9k())
+		return;
+
+	plt_print("Count registers for CPT LF%d:", lf->lf_id);
+
 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);
 	plt_print("    Encrypted byte count:\t%" PRIu64, reg_val);
 
@@ -190,7 +219,6 @@  roc_cpt_lfs_print(struct roc_cpt *roc_cpt)
 		if (lf == NULL)
 			continue;
 
-		plt_print("Count registers for CPT LF%d:", lf_id);
 		cpt_lf_print(lf);
 	}
 
diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h
index 21911e5..61dec9a 100644
--- a/drivers/common/cnxk/roc_cpt_priv.h
+++ b/drivers/common/cnxk/roc_cpt_priv.h
@@ -31,5 +31,6 @@  int cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,
 		    uint8_t lf_id, bool ena);
 int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);
 uint64_t cpt_get_blkaddr(struct dev *dev);
+void cpt_lf_print(struct roc_cpt_lf *lf);
 
 #endif /* _ROC_CPT_PRIV_H_ */