From patchwork Thu Sep 30 17:00:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 100142 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 95159A0C43; Thu, 30 Sep 2021 19:02:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16C9A41140; Thu, 30 Sep 2021 19:02:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 275FE41100 for ; Thu, 30 Sep 2021 19:01:59 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18UF7lBw018456 for ; Thu, 30 Sep 2021 10:01:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=3NvcO7fH0TlSKAazKmJC/M5/EBYIhT649nQ+GHoyYpM=; b=d3+rQyizQvQPhNeJAToCZ1CFJZ8wkuQHmkRtV9TFVb8M6eEPGqd+xqVu4O/gatAerAKJ j43VJPHUJUemh6YOEa72UJmz22t/TjtX+u+n/rq/fbWqLSKrFp2X46MMhFURXhup+KDw r7spyazVRnAPFERgIY/GJQLWskYdGMEciCHZ5QBvysVCqx17CuP7BlV8fn6nH1CqNgIi s4fQo8HFYIUXbxLnCVWQ05MBx7XCgYBNPLW4EFzkjNqNyvGKFcZH3z+vKtz3qiD1ZI+i t0pna89VqUWpif875EyQDZy+CtopfMBdlyUpnUgXENh0lq8QZLibQ1qSXppx/xMy7t+E og== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g3b9v5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 30 Sep 2021 10:01:57 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 10:01:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 10:01:55 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id F3BB63F7067; Thu, 30 Sep 2021 10:01:53 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Thu, 30 Sep 2021 22:30:58 +0530 Message-ID: <20210930170113.29030-14-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210930170113.29030-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> <20210930170113.29030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: VWAvGZjqCR4vLwrHRd7HFN9Mlrtzfo7S X-Proofpoint-ORIG-GUID: VWAvGZjqCR4vLwrHRd7HFN9Mlrtzfo7S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_06,2021-09-30_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 13/28] common/cnxk: setup aura BP conf based on nix X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently only NIX0 conf is setup in AURA for backpressure. This patch adds support for NIX1 as well. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_fc.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index f17eba4..7eac7d0 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -284,8 +284,18 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, limit = rsp->aura.limit; /* BP is already enabled. */ if (rsp->aura.bp_ena) { + uint16_t bpid; + bool nix1; + + nix1 = !!(rsp->aura.bp_ena & 0x2); + if (nix1) + bpid = rsp->aura.nix1_bpid; + else + bpid = rsp->aura.nix0_bpid; + /* If BP ids don't match disable BP. */ - if ((rsp->aura.nix0_bpid != nix->bpid[0]) && !force) { + if (((nix1 != nix->is_nix1) || (bpid != nix->bpid[0])) && + !force) { req = mbox_alloc_msg_npa_aq_enq(mbox); if (req == NULL) return; @@ -315,14 +325,19 @@ rox_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, req->op = NPA_AQ_INSTOP_WRITE; if (ena) { - req->aura.nix0_bpid = nix->bpid[0]; - req->aura_mask.nix0_bpid = ~(req->aura_mask.nix0_bpid); + if (nix->is_nix1) { + req->aura.nix1_bpid = nix->bpid[0]; + req->aura_mask.nix1_bpid = ~(req->aura_mask.nix1_bpid); + } else { + req->aura.nix0_bpid = nix->bpid[0]; + req->aura_mask.nix0_bpid = ~(req->aura_mask.nix0_bpid); + } req->aura.bp = NIX_RQ_AURA_THRESH( limit > 128 ? 256 : limit); /* 95% of size*/ req->aura_mask.bp = ~(req->aura_mask.bp); } - req->aura.bp_ena = !!ena; + req->aura.bp_ena = (!!ena << nix->is_nix1); req->aura_mask.bp_ena = ~(req->aura_mask.bp_ena); mbox_process(mbox);