From patchwork Thu Sep 30 17:28:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 100172 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8DDB2A0C45; Thu, 30 Sep 2021 19:40:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 050CD4111A; Thu, 30 Sep 2021 19:39:49 +0200 (CEST) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1anam02on2077.outbound.protection.outlook.com [40.107.96.77]) by mails.dpdk.org (Postfix) with ESMTP id DA49C410E5 for ; Thu, 30 Sep 2021 19:28:51 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MILtwMyqfq1ecXaD6RN7PSHI532JFjaYEM5G1/6q3PWpIfEhXCAs8n5VM9H5QkzBw2lXGLeyBo6XxFPXRRP93Qv7aAXY5oP4xrG9Sj+k8L5qEzZ0p16s9lSOm8MpVnqKSFge5OwybLL4jvt/RNnvQnbzbSINytzOO6M1wskIOX/Vl39/K1C1XeTMtUtxmYvoJwhtlm7upKgwA4J6QzO2zmSBcnwunPVYIhW6oyerXx7gfBRM2wiPGskDV0sUs7LdDKefeQ09kwXH947+INaPYPK4pYx2nRvX8wSrU4wEsWW7zc/8YGr/PYIuGiFZDzBUJe7eBwd37tsCc2gUNRCWOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=ZSaEx8BAjsFLwbWvDZTbR+MSmZYJ2S3GAw/wksr1nfY=; b=SwDV/dNR4Td0hn+3Rf1h2fnzYHTelqQfawSg99K0KR4ZDRDwHD33EO6GH2MkIOMuAaD4ii2aajfDep4tt5K76VHaMRKXGYLLhUjXCEj0OBHpjIlcAhGT8JpwA/BfrbTtx7bnD6U2/ZrUhtQenJMaODw4xzT39GkhHeaEL1hzRlx4+Sd79wt/tMRuWWKTKbb8WLQdNy3ndNDCSXeSlSKmA/E/7D2vmxjp0WGt3A+eUbSThJmWaEbN2judwInquxzVkze7JXywY4PuuSVEKfOnbs/ZJHUlmqHPzPabmw1lVxNIOSjc2edULY7THRqlU3huNVKH+So75r1pJcI1oIUdUA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZSaEx8BAjsFLwbWvDZTbR+MSmZYJ2S3GAw/wksr1nfY=; b=fx75jctM+k1iXnh7QWvWQN4aJQO9RTX6dMpu9uXPLxdZCCEk0E+P14S/trlUIQPx38HOb9WRhs0HSkHllPMU8+/Etvgrc4kMPCTWz5LFkh5ymOUhzkBtmuYuwo9J+UZ7/+0v/MmxwGZ5dXPdr6a73MizsReyaEpRA9LeAVNuWBhSspeLzvqpmboAuT7667TXDo8LbDv2hDwXWBDfMQ7JfQ1XDrxjFP8sXrvY7XAh0z94hvNh3DlK002jfqV9C/B90sIpdR5/BDLi7ZV3u9XAzHOxVoZoh7F18TGMBsIEAJ8l3LdG98i+DKBMXwTOO7VY7gC+VMhJbHLAxGdq1qGj9A== Received: from BN9PR03CA0883.namprd03.prod.outlook.com (2603:10b6:408:13c::18) by MWHPR1201MB0272.namprd12.prod.outlook.com (2603:10b6:301:52::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.20; Thu, 30 Sep 2021 17:28:50 +0000 Received: from BN8NAM11FT058.eop-nam11.prod.protection.outlook.com (2603:10b6:408:13c:cafe::26) by BN9PR03CA0883.outlook.office365.com (2603:10b6:408:13c::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 17:28:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT058.mail.protection.outlook.com (10.13.177.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 17:28:49 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 17:28:47 +0000 From: To: CC: Matan Azrad , Thomas Monjalon , Michael Baum Date: Thu, 30 Sep 2021 20:28:07 +0300 Message-ID: <20210930172822.1949969-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930172822.1949969-1-michaelba@nvidia.com> References: <20210930172822.1949969-1-michaelba@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0cc78333-4397-47c4-d661-08d98437c40e X-MS-TrafficTypeDiagnostic: MWHPR1201MB0272: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:264; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hlJcDBk/ae4RV43ihxcXbRRs00dqvp+FYxmFmJELw9HRePNnm5JV/gldPPYbSMB59L1cT5yek3U3pqUcstAiRIds4L3bxrNUXURd/iV0LSgzwwcZI0kOF4gF+thITG5jSqMLqmXXrbWpDq7iOtZW/flKpUljtmhXV0jRsYL85MobEzMmPjIM238AyF2rdlH/8SUQxZ82wkxuBApKrJZbC7YI9B++RlRLQN1c4KhgbJA+UWyJxL3xti6VExmWZ9uCJb2+FBh93d8EyTOI4mR/antd45xheQ9xa2oEqghp5voh/PSYLk6PqJpJ5z2vyQ6s/pjN0OzhsnL5/N7ruR6HiWpOjkQaH/MSW+kimvlbLqQ6ThGNUZhOUqMomfkqfASYfmPo2hFTs+k6bi+URZlgLBvqg+3cWH8HkdzqFupbEkNNMczcpOjo87MfCadAjT3+DpdAVCiGsHPmVswvhUi16XVgRJmjOwGxOiyuKuWIaGeqnRcVr7Z0iw7nPBNSLD3KOffjmwWHIIMFtE+mDgNBzMOQUDwAS/V1EiY+0Xu0JzIbxK/lkQ45RY1V1DsbOP4zAuY8DmOCG5c8LZKEFQjkCEIezsJWWrA9Akvw3p5UjOSCfmR9lxSTfcYSF2TFWKkD06mTUFlzMBX56ohg48v4VZ2Mv7zjo2zSOVyEXahHjRW8gSW8tTmNjtPdIWEz9uY16PA3TTSmHvJPc7bY9yICpA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(70586007)(82310400003)(36860700001)(2616005)(6916009)(5660300002)(6666004)(7696005)(7636003)(47076005)(83380400001)(55016002)(54906003)(316002)(36756003)(70206006)(8936002)(356005)(6286002)(336012)(4326008)(426003)(1076003)(8676002)(508600001)(86362001)(2906002)(2876002)(26005)(107886003)(186003)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 17:28:49.5371 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cc78333-4397-47c4-d661-08d98437c40e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0272 X-Mailman-Approved-At: Thu, 30 Sep 2021 19:39:43 +0200 Subject: [dpdk-dev] [PATCH 03/18] common/mlx5: share common definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Michael Baum Create MACRO definitions file in the common driver as preparation for MR and basic probe sharing. Move relevant definitions from the net driver to the above file. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_common.c | 1 + drivers/common/mlx5/mlx5_common_defs.h | 42 ++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_common_mr.h | 5 +-- drivers/common/mlx5/mlx5_devx_cmds.h | 12 ++------ drivers/net/mlx5/mlx5.h | 4 +-- drivers/net/mlx5/mlx5_defs.h | 22 ++------------ 6 files changed, 49 insertions(+), 37 deletions(-) create mode 100644 drivers/common/mlx5/mlx5_common_defs.h diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c index 91de7b3e2c..8e3ea073e3 100644 --- a/drivers/common/mlx5/mlx5_common.c +++ b/drivers/common/mlx5/mlx5_common.c @@ -14,6 +14,7 @@ #include "mlx5_common.h" #include "mlx5_common_os.h" #include "mlx5_common_log.h" +#include "mlx5_common_defs.h" #include "mlx5_common_private.h" uint8_t haswell_broadwell_cpu; diff --git a/drivers/common/mlx5/mlx5_common_defs.h b/drivers/common/mlx5/mlx5_common_defs.h new file mode 100644 index 0000000000..6fd30f2c97 --- /dev/null +++ b/drivers/common/mlx5/mlx5_common_defs.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2021 6WIND S.A. + * Copyright 2021 Mellanox Technologies, Ltd + */ + +#ifndef RTE_PMD_MLX5_COMMON_DEFS_H_ +#define RTE_PMD_MLX5_COMMON_DEFS_H_ + +#include "mlx5_autoconf.h" + +/* Size of per-queue MR cache array for linear search. */ +#define MLX5_MR_CACHE_N 8 + +/* Size of MR cache table for binary search. */ +#define MLX5_MR_BTREE_CACHE_N 256 + +/* + * Defines the amount of retries to allocate the first UAR in the page. + * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as + * UAR base address if UAR was not the first object in the UAR page. + * It caused the PMD failure and we should try to get another UAR + * till we get the first one with non-NULL base address returned. + */ +#define MLX5_ALLOC_UAR_RETRY 32 + +/* Environment variable to control the doorbell register mapping. */ +#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" +#if defined(RTE_ARCH_ARM64) +#define MLX5_SHUT_UP_BF_DEFAULT "0" +#else +#define MLX5_SHUT_UP_BF_DEFAULT "1" +#endif + +/* Default PMD specific parameter value. */ +#define MLX5_ARG_UNSET (-1) + +/* MLX5_TX_DB_NC supported values. */ +#define MLX5_TXDB_CACHED 0 +#define MLX5_TXDB_NCACHED 1 +#define MLX5_TXDB_HEURISTIC 2 + +#endif /* RTE_PMD_MLX5_COMMON_DEFS_H_ */ diff --git a/drivers/common/mlx5/mlx5_common_mr.h b/drivers/common/mlx5/mlx5_common_mr.h index 685ac98e08..15489cd399 100644 --- a/drivers/common/mlx5/mlx5_common_mr.h +++ b/drivers/common/mlx5/mlx5_common_mr.h @@ -18,10 +18,7 @@ #include "mlx5_glue.h" #include "mlx5_common_mp.h" - -/* Size of per-queue MR cache array for linear search. */ -#define MLX5_MR_CACHE_N 8 -#define MLX5_MR_BTREE_CACHE_N 256 +#include "mlx5_common_defs.h" /* mlx5 PMD MR struct. */ struct mlx5_pmd_mr { diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index e576e30f24..a7c92c9e40 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -5,18 +5,10 @@ #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ #define RTE_PMD_MLX5_DEVX_CMDS_H_ -#include "mlx5_glue.h" -#include "mlx5_prm.h" #include -/* - * Defines the amount of retries to allocate the first UAR in the page. - * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as - * UAR base address if UAR was not the first object in the UAR page. - * It caused the PMD failure and we should try to get another UAR - * till we get the first one with non-NULL base address returned. - */ -#define MLX5_ALLOC_UAR_RETRY 32 +#include "mlx5_glue.h" +#include "mlx5_prm.h" /* This is limitation of libibverbs: in length variable type is u16. */ #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index f441352a63..2e93ce2a3e 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -27,6 +27,7 @@ #include #include #include +#include #include "mlx5_defs.h" #include "mlx5_utils.h" @@ -214,9 +215,6 @@ struct mlx5_stats_ctrl { uint64_t imissed; }; -/* Default PMD specific parameter value. */ -#define MLX5_ARG_UNSET (-1) - #define MLX5_LRO_SUPPORTED(dev) \ (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index fe86bb40d3..376e34a946 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -9,6 +9,8 @@ #include #include +#include + #include "mlx5_autoconf.h" /* Maximum number of simultaneous VLAN filters. */ @@ -33,13 +35,6 @@ */ #define MLX5_TX_COMP_MAX_CQE 2u - -/* Size of per-queue MR cache array for linear search. */ -#define MLX5_MR_CACHE_N 8 - -/* Size of MR cache table for binary search. */ -#define MLX5_MR_BTREE_CACHE_N 256 - /* * If defined, only use software counters. The PMD will never ask the hardware * for these, and many of them won't be available. @@ -121,14 +116,6 @@ #define MLX5_UAR_MMAP_CMD_SHIFT 8 #define MLX5_UAR_MMAP_CMD_MASK 0xff -/* Environment variable to control the doorbell register mapping. */ -#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" -#if defined(RTE_ARCH_ARM64) -#define MLX5_SHUT_UP_BF_DEFAULT "0" -#else -#define MLX5_SHUT_UP_BF_DEFAULT "1" -#endif - #ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD #define MLX5_MMAP_GET_NC_PAGES_CMD 3 #endif @@ -161,11 +148,6 @@ /* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */ #define MLX5_XMETA_MODE_MISS_INFO 3 -/* MLX5_TX_DB_NC supported values. */ -#define MLX5_TXDB_CACHED 0 -#define MLX5_TXDB_NCACHED 1 -#define MLX5_TXDB_HEURISTIC 2 - /* Tx accurate scheduling on timestamps parameters. */ #define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ #define MLX5_TXPP_CLKQ_SIZE 1