diff mbox series

[v2,1/2] eal/x86: fix some CPU extended features definitions

Message ID 20211008120715.17810-1-david.marchand@redhat.com (mailing list archive)
State Accepted, archived
Delegated to: David Marchand
Headers
Series [v2,1/2] eal/x86: fix some CPU extended features definitions |

Checks

Context Check Description
ci/checkpatch warning coding style issues
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS

Commit Message

David Marchand Oct. 8, 2021, 12:07 p.m. UTC 
  Caught while checking CPUID related stuff in OVS.

According to [1], for Structured Extended Feature Flags Enumeration Leaf
(EAX = 0x07H, ECX = 0):

- BMI1 is associated to EBX, bit 3 (was incorrectly 2),
- SMEP is associated to EBX, bit 7 (was incorrectly 6),
- BMI2 is associated to EBX, bit 8 (was incorrectly 7),
- ERMS is associated to EBX, bit 9 (was incorrectly 8),

1: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
---
 lib/eal/x86/rte_cpuflags.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

David Marchand Oct. 12, 2021, 7:06 p.m. UTC | #1 
On Fri, Oct 8, 2021 at 2:07 PM David Marchand <david.marchand@redhat.com> wrote:
>
> Caught while checking CPUID related stuff in OVS.
>
> According to [1], for Structured Extended Feature Flags Enumeration Leaf
> (EAX = 0x07H, ECX = 0):
>
> - BMI1 is associated to EBX, bit 3 (was incorrectly 2),
> - SMEP is associated to EBX, bit 7 (was incorrectly 6),
> - BMI2 is associated to EBX, bit 8 (was incorrectly 7),
> - ERMS is associated to EBX, bit 9 (was incorrectly 8),
>
> 1: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> Fixes: af75078fece3 ("first public release")
> Cc: stable@dpdk.org
>
> Signed-off-by: David Marchand <david.marchand@redhat.com>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Series applied, thanks.
diff mbox series

Patch

diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c
index d339734a8c..378fc95396 100644
--- a/lib/eal/x86/rte_cpuflags.c
+++ b/lib/eal/x86/rte_cpuflags.c
@@ -100,12 +100,12 @@  const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX,  3)
 
 	FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX,  0)
-	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  2)
+	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  3)
 	FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX,  4)
 	FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX,  5)
-	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  6)
-	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  7)
-	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  8)
+	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  7)
+	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  8)
+	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  9)
 	FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
 	FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
 	FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)