From patchwork Tue Oct 12 08:06:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 101182 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 51A74A0C47; Tue, 12 Oct 2021 10:07:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C9DEF4111E; Tue, 12 Oct 2021 10:07:03 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2084.outbound.protection.outlook.com [40.107.93.84]) by mails.dpdk.org (Postfix) with ESMTP id 468E2410F6 for ; Tue, 12 Oct 2021 10:07:02 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f2s7pG5W4HTPXBRpTlMvjILz4NFec/p83Rw3+0fU3uQ6uTqhWAioVaHl4jUGvSgAkdNmjIdc2nC+iFG/0vPh+DOJ/yfva3yaLAPMUam/B9oKINqjrCwHjLcdUYqhSdjEklIzdIP+9A4NfSzXa59808JYXA6qv3wTO5rV0IRRaqHnvFMX/MW1GACOcxKFYrVM7MTW2InuO8KMTYTHAyhSOP075zIrBGRHzNEBcjY+QGFe4KI7VyfdrF70kMCus3thDcQ7LsCnD0w18Hgq/hAIfgmoy75Wp1SKHlO7fIyeA8vL1OB8GIyMkLkAYcHQn8kmDUGCR8eOPkS0ltvlCZuPlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BOwMKzepGTCygzx2JmZsW4nLTyHpCUfHp3kh4oVQrJY=; b=DkWNAEem+Yl+94aMEQoII3JziDqeq6GzdrBFmWJxRghY/71JNG4hYHKAcChchPIoZBqWgw1hmJwWrP/KMHDSKVjrPYXUIbcuFFu0zJBk6AlCmBxipxHG8DJV/1o4xfaN1iB+ODzBvaOO816WjXnhkyAYCdUzIUudo+mfWlvFsUu8t0yVc5l6KVdBKB29redScu1DFK0MLk795xbYQAF8/Vrd7ZBn/OwJBwpl/ayiC77WpG/Is+9BPB2NQQtsBwt8FZ/gOuO5OoDIJQS9dXdCnu6fxNU1mr73ot8DDxvR8HZWKN0uUTDJ2BgMF7290MxkO1MtczsyaJqUVJRhYeLOyQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BOwMKzepGTCygzx2JmZsW4nLTyHpCUfHp3kh4oVQrJY=; b=CKtuWVMcMHOPRECrV7ON12J/ODYfu9inSmRzFZ5yh++A5S+4fTxn08QA8bR/CKQdPKzsOsl4SfjFpExPTwqRkme0TJKbuLSR7S2IxZvvERiChLz1nryxFeRl/Rxm6OXVBeJUDBy2KHC2OaFVBfPzDm4x/yPR3TB3WY5cW0Nbkos5dgdlyh2sRcBFmoKi3D5P3Cm4XO5dymvc0ntNUcxakY2ca1DAgsrmTM8O561lUuDXflg3dVumwPFtSsZuOopFlOhFeq6Vby6MUi3aZ4xQt2aRtTFDmY3hJMznye+LjVnjHTFqU7d1a0vdlAWCO4fv0pk2zMgnHmXysx5U+au1sg== Received: from MWHPR20CA0035.namprd20.prod.outlook.com (2603:10b6:300:ed::21) by DM6PR12MB4579.namprd12.prod.outlook.com (2603:10b6:5:2ac::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.25; Tue, 12 Oct 2021 08:07:00 +0000 Received: from CO1NAM11FT007.eop-nam11.prod.protection.outlook.com (2603:10b6:300:ed:cafe::c8) by MWHPR20CA0035.outlook.office365.com (2603:10b6:300:ed::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.18 via Frontend Transport; Tue, 12 Oct 2021 08:07:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT007.mail.protection.outlook.com (10.13.174.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4587.18 via Frontend Transport; Tue, 12 Oct 2021 08:06:59 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 12 Oct 2021 08:06:57 +0000 From: Viacheslav Ovsiienko To: CC: , , , , , Date: Tue, 12 Oct 2021 11:06:31 +0300 Message-ID: <20211012080631.28504-6-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20211012080631.28504-1-viacheslavo@nvidia.com> References: <20210910141609.8410-1-viacheslavo@nvidia.com> <20211012080631.28504-1-viacheslavo@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c52bdf76-29b5-405a-3358-08d98d574478 X-MS-TrafficTypeDiagnostic: DM6PR12MB4579: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +HJkRhFvo0zoUfDgJPR5W4ZN985t8itw759SjI65u7QjYNEu53huZEG36Jrz2u8ut2nvpVAf914WA56y/W9bi+EXqPATsfI92JvtiE9Jnzuu2SkOJw5pFIMknxA96Vxz/hLJS90c6/rd6P63z9k97srSLQbuKB78Qn0EJs+JVYV8s/bNOeyUx3t/KljOseYTvDcyyr0wpwj52MTSjU/FK57j0i++fPaLHObWTpVKcTdT38062iZEsZnfKJtrlMJb96W8HXROJfC/0Rqt4AfHRtfyWPlf8a17ABbRKW6jJRCdy+qQrqIez4AlWRkWOqNdk4LUoHEHcGS6oh24LfsDJ4dC6jKVI/RYjLmsoyZbQxL096Pu5vEmeJM7Jhsnf/I66PIObhkdj9bXh0gIx+fNHQB3FIkBObAUAoSIwL7zOwGdDMEjruzxEAMAw4ZFCsCjf+oM04XhHBq+wPU0xVuN++EeuEiidx/0S93X7uGnAQi6swjoVydhVFEn81utvzus29PQa0zMy1S6K1VlS+31P3whVoFraSU7JQDyjXcjcnT4hwe5Hs0wnY9gfXJfU+bTX/jMoerbI34Qc2mgN7RxwhB1FR4BH0kzIUbkp69xjtfzFRmv+GH9A2ILlY6d0qEoA00Fo42FLvVi1TkcvD9q/H/LUDkv/LWgl0/YWzlaNJ1vbJfkm1sD2T+i7qj5e05H8GdBcsuOrrmhx+7Qt+Dtjw== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(8676002)(16526019)(47076005)(26005)(5660300002)(508600001)(336012)(7696005)(36756003)(83380400001)(54906003)(2616005)(70586007)(8936002)(186003)(55016002)(6666004)(15650500001)(6916009)(426003)(356005)(6286002)(36860700001)(2906002)(316002)(1076003)(70206006)(86362001)(7636003)(82310400003)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2021 08:06:59.8413 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c52bdf76-29b5-405a-3358-08d98d574478 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4579 Subject: [dpdk-dev] [PATCH v3 5/5] net/mlx5: update modify field action X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Update immediate value/pointer source operand support for modify field RTE Flow action: - source operand data can be presented by byte buffer (instead of former uint64_t) or by pointer - no host byte ordering is assumed anymore for immediate data buffer (not uint64_t anymore) - no immediate value offset is expected Signed-off-by: Viacheslav Ovsiienko Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow_dv.c | 50 +++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index c6370cd1d6..867f587960 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1391,7 +1391,7 @@ flow_dv_convert_action_modify_ipv6_dscp static int mlx5_flow_item_field_width(struct mlx5_priv *priv, - enum rte_flow_field_id field) + enum rte_flow_field_id field, int inherit) { switch (field) { case RTE_FLOW_FIELD_START: @@ -1442,7 +1442,8 @@ mlx5_flow_item_field_width(struct mlx5_priv *priv, return __builtin_popcount(priv->sh->dv_meta_mask); case RTE_FLOW_FIELD_POINTER: case RTE_FLOW_FIELD_VALUE: - return 64; + MLX5_ASSERT(inherit >= 0); + return inherit < 0 ? 0 : inherit; default: MLX5_ASSERT(false); } @@ -1462,7 +1463,8 @@ mlx5_flow_field_id_to_modify_info struct mlx5_priv *priv = dev->data->dev_private; uint32_t idx = 0; uint32_t off = 0; - uint64_t val = 0; + uint8_t *pval; + switch (data->field) { case RTE_FLOW_FIELD_START: /* not supported yet */ @@ -1838,32 +1840,37 @@ mlx5_flow_field_id_to_modify_info break; case RTE_FLOW_FIELD_POINTER: case RTE_FLOW_FIELD_VALUE: - if (data->field == RTE_FLOW_FIELD_POINTER) - memcpy(&val, (void *)(uintptr_t)data->value, - sizeof(uint64_t)); - else - val = data->value; + pval = data->field == RTE_FLOW_FIELD_POINTER ? + (uint8_t *)(uintptr_t)data->pvalue : + (uint8_t *)(uintptr_t)&data->value; for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) { + if (!dst_width) + break; if (mask[idx]) { if (dst_width == 48) { /*special case for MAC addresses */ - value[idx] = rte_cpu_to_be_16(val); - val >>= 16; + value[idx] = rte_cpu_to_be_16 + (*(unaligned_uint16_t *)pval); + pval += sizeof(uint16_t); dst_width -= 16; } else if (dst_width > 16) { - value[idx] = rte_cpu_to_be_32(val); - val >>= 32; + value[idx] = rte_cpu_to_be_32 + (*(unaligned_uint32_t *)pval); + pval += sizeof(uint32_t); + dst_width -= RTE_MIN(32u, dst_width); } else if (dst_width > 8) { - value[idx] = rte_cpu_to_be_16(val); - val >>= 16; + value[idx] = rte_cpu_to_be_16 + (*(unaligned_uint16_t *)pval); + pval += sizeof(uint16_t); + dst_width -= RTE_MIN(16u, dst_width); } else { - value[idx] = (uint8_t)val; - val >>= 8; + value[idx] = *pval++; + dst_width -= RTE_MIN(8u, dst_width); } if (*shift) value[idx] <<= *shift; - if (!val) - break; + } else { + pval += sizeof(uint32_t); } } break; @@ -1910,8 +1917,9 @@ flow_dv_convert_action_modify_field uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0}; uint32_t type; uint32_t shift = 0; - uint32_t dst_width = mlx5_flow_item_field_width(priv, conf->dst.field); + uint32_t dst_width; + dst_width = mlx5_flow_item_field_width(priv, conf->dst.field, -1); if (conf->src.field == RTE_FLOW_FIELD_POINTER || conf->src.field == RTE_FLOW_FIELD_VALUE) { type = MLX5_MODIFICATION_TYPE_SET; @@ -4874,9 +4882,9 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, const struct rte_flow_action_modify_field *action_modify_field = action->conf; uint32_t dst_width = mlx5_flow_item_field_width(priv, - action_modify_field->dst.field); + action_modify_field->dst.field, -1); uint32_t src_width = mlx5_flow_item_field_width(priv, - action_modify_field->src.field); + action_modify_field->src.field, dst_width); ret = flow_dv_validate_action_modify_hdr(action_flags, action, error); if (ret)