| Message ID | 20211016080732.1781622-4-xuemingl@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Raslan Darawsheh |
| Headers |
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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(82310400003)(8676002)(2616005)(8936002)(36860700001)(7696005)(70586007)(6916009)(508600001)(55016002)(1076003)(6286002)(336012)(70206006)(26005)(2906002)(47076005)(83380400001)(316002)(356005)(4326008)(36756003)(186003)(6666004)(5660300002)(54906003)(426003)(86362001)(107886003)(7636003)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2021 08:08:05.5755 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c05d820-c51e-49bb-b20c-08d9907c154f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4043 Subject: [dpdk-dev] [PATCH v2 3/8] net/mlx5: improve Verbs flow priority discover for scalable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> |
| Series |
net/mlx5: support more than 255 representors
|
|
Checks
| Context | Check | Description |
|---|---|---|
| ci/checkpatch | success | coding style OK |
Commit Message
Xueming Li
Oct. 16, 2021, 8:07 a.m. UTC
To detect number flow Verbs flow priorities, PMD try to create Verbs
flows in different priority. While Verbs is not designed to support
ports larger than 255.
When DevX supported by kernel driver, 16 Verbs priorities must be
supported, no need to create Verbs flows.
Signed-off-by: Xueming Li <xuemingl@nvidia.com>
---
drivers/net/mlx5/mlx5_flow_verbs.c | 8 ++++++++
1 file changed, 8 insertions(+)
Comments
> -----Original Message----- > From: Xueming(Steven) Li <xuemingl@nvidia.com> > Sent: Saturday, October 16, 2021 11:07 > To: dev@dpdk.org > Cc: Xueming(Steven) Li <xuemingl@nvidia.com>; Slava Ovsiienko > <viacheslavo@nvidia.com>; Lior Margalit <lmargalit@nvidia.com>; Matan > Azrad <matan@nvidia.com> > Subject: [PATCH v2 3/8] net/mlx5: improve Verbs flow priority discover for > scalable > > To detect number flow Verbs flow priorities, PMD try to create Verbs flows in > different priority. While Verbs is not designed to support ports larger than > 255. > > When DevX supported by kernel driver, 16 Verbs priorities must be supported, > no need to create Verbs flows. > > Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c index b93fd4d2c96..178eabed163 100644 --- a/drivers/net/mlx5/mlx5_flow_verbs.c +++ b/drivers/net/mlx5/mlx5_flow_verbs.c @@ -83,6 +83,11 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev) int i; int priority = 0; +#if defined(HAVE_MLX5DV_DR_DEVX_PORT) || defined(HAVE_MLX5DV_DR_DEVX_PORT_V35) + /* If DevX supported, driver must support 16 verbs flow priorities. */ + priority = RTE_DIM(priority_map_5); + goto out; +#endif if (!drop->qp) { rte_errno = ENOTSUP; return -rte_errno; @@ -109,6 +114,9 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev) dev->data->port_id, priority); return -rte_errno; } +#if defined(HAVE_MLX5DV_DR_DEVX_PORT) || defined(HAVE_MLX5DV_DR_DEVX_PORT_V35) +out: +#endif DRV_LOG(INFO, "port %u supported flow priorities:" " 0-%d for ingress or egress root table," " 0-%d for non-root table or transfer root table.",