From patchwork Wed Oct 20 12:47:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 102433 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B406DA0C43; Wed, 20 Oct 2021 14:48:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 73C3D41221; Wed, 20 Oct 2021 14:47:53 +0200 (CEST) Received: from shelob.oktetlabs.ru (shelob.oktetlabs.ru [91.220.146.113]) by mails.dpdk.org (Postfix) with ESMTP id B924C41226 for ; Wed, 20 Oct 2021 14:47:49 +0200 (CEST) Received: by shelob.oktetlabs.ru (Postfix, from userid 122) id 8B3187F6B8; Wed, 20 Oct 2021 15:47:49 +0300 (MSK) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on shelob.oktetlabs.ru X-Spam-Level: X-Spam-Status: No, score=0.8 required=5.0 tests=ALL_TRUSTED, DKIM_ADSP_DISCARD, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from aros.oktetlabs.ru (aros.oktetlabs.ru [192.168.38.17]) by shelob.oktetlabs.ru (Postfix) with ESMTP id E4E2E7F6F9; Wed, 20 Oct 2021 15:47:31 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 shelob.oktetlabs.ru E4E2E7F6F9 Authentication-Results: shelob.oktetlabs.ru/E4E2E7F6F9; dkim=none; dkim-atps=neutral From: Andrew Rybchenko To: Ferruh Yigit , Thomas Monjalon Cc: dev@dpdk.org Date: Wed, 20 Oct 2021 15:47:22 +0300 Message-Id: <20211020124727.2829268-5-andrew.rybchenko@oktetlabs.ru> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211020124727.2829268-1-andrew.rybchenko@oktetlabs.ru> References: <20211014083704.2542493-1-andrew.rybchenko@oktetlabs.ru> <20211020124727.2829268-1-andrew.rybchenko@oktetlabs.ru> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 04/10] ethdev: fix DCB and VMDq spelling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix both in one changeset since they share line in a number of cases. Signed-off-by: Andrew Rybchenko --- lib/ethdev/ethdev_driver.h | 2 +- lib/ethdev/rte_ethdev.h | 42 +++++++++++++++++++------------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h index dbd32bc1cd..94878f94fc 100644 --- a/lib/ethdev/ethdev_driver.h +++ b/lib/ethdev/ethdev_driver.h @@ -661,7 +661,7 @@ typedef int (*eth_tm_ops_get_t)(struct rte_eth_dev *dev, void *ops); /** @internal Get Traffic Metering and Policing (MTR) operations. */ typedef int (*eth_mtr_ops_get_t)(struct rte_eth_dev *dev, void *ops); -/** @internal Get dcb information on an Ethernet device. */ +/** @internal Get DCB information on an Ethernet device. */ typedef int (*eth_get_dcb_info)(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info); diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 6ae6d9ba99..d903f51196 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -83,7 +83,7 @@ * - MTU * - flow control settings * - receive mode configuration (promiscuous mode, all-multicast mode, - * hardware checksum mode, RSS/VMDQ settings etc.) + * hardware checksum mode, RSS/VMDq settings etc.) * - VLAN filtering configuration * - default MAC address * - MAC addresses supplied to MAC address array @@ -365,7 +365,7 @@ struct rte_eth_thresh { * packets to multiple queues. */ enum rte_eth_rx_mq_mode { - /** None of DCB,RSS or VMDQ mode */ + /** None of DCB, RSS or VMDq mode */ ETH_MQ_RX_NONE = 0, /** For Rx side, only RSS is on */ @@ -375,13 +375,13 @@ enum rte_eth_rx_mq_mode { /** Both DCB and RSS enable */ ETH_MQ_RX_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG, - /** Only VMDQ, no RSS nor DCB */ + /** Only VMDq, no RSS nor DCB */ ETH_MQ_RX_VMDQ_ONLY = ETH_MQ_RX_VMDQ_FLAG, - /** RSS mode with VMDQ */ + /** RSS mode with VMDq */ ETH_MQ_RX_VMDQ_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_VMDQ_FLAG, - /** Use VMDQ+DCB to route traffic to queues */ + /** Use VMDq+DCB to route traffic to queues */ ETH_MQ_RX_VMDQ_DCB = ETH_MQ_RX_VMDQ_FLAG | ETH_MQ_RX_DCB_FLAG, - /** Enable both VMDQ and DCB in VMDq */ + /** Enable both VMDq and DCB in VMDq */ ETH_MQ_RX_VMDQ_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG | ETH_MQ_RX_VMDQ_FLAG, }; @@ -805,9 +805,9 @@ rte_eth_rss_hf_refine(uint64_t rss_hf) #define RTE_RETA_GROUP_SIZE 64 /**@{@name VMDq and DCB maximums */ -#define ETH_VMDQ_MAX_VLAN_FILTERS 64 /**< Maximum nb. of VMDQ vlan filters. */ +#define ETH_VMDQ_MAX_VLAN_FILTERS 64 /**< Maximum nb. of VMDq vlan filters. */ #define ETH_DCB_NUM_USER_PRIORITIES 8 /**< Maximum nb. of DCB priorities. */ -#define ETH_VMDQ_DCB_NUM_QUEUES 128 /**< Maximum nb. of VMDQ DCB queues. */ +#define ETH_VMDQ_DCB_NUM_QUEUES 128 /**< Maximum nb. of VMDq DCB queues. */ #define ETH_DCB_NUM_QUEUES 128 /**< Maximum nb. of DCB queues. */ /**@}*/ @@ -869,7 +869,7 @@ enum rte_eth_nb_tcs { /** * This enum indicates the possible number of queue pools - * in VMDQ configurations. + * in VMDq configurations. */ enum rte_eth_nb_pools { ETH_8_POOLS = 8, /**< 8 VMDq pools. */ @@ -902,7 +902,7 @@ struct rte_eth_vmdq_tx_conf { }; /** - * A structure used to configure the VMDQ+DCB feature + * A structure used to configure the VMDq+DCB feature * of an Ethernet port. * * Using this feature, packets are routed to a pool of queues, based @@ -926,7 +926,7 @@ struct rte_eth_vmdq_dcb_conf { }; /** - * A structure used to configure the VMDQ feature of an Ethernet port when + * A structure used to configure the VMDq feature of an Ethernet port when * not combined with the DCB feature. * * Using this feature, packets are routed to a pool of queues. By default, @@ -1321,19 +1321,19 @@ struct rte_eth_conf { are defined in implementation of each driver. */ struct { struct rte_eth_rss_conf rss_conf; /**< Port RSS configuration */ - /** Port vmdq+dcb configuration. */ + /** Port VMDq+DCB configuration. */ struct rte_eth_vmdq_dcb_conf vmdq_dcb_conf; - /** Port dcb Rx configuration. */ + /** Port DCB Rx configuration. */ struct rte_eth_dcb_rx_conf dcb_rx_conf; - /** Port vmdq Rx configuration. */ + /** Port VMDq Rx configuration. */ struct rte_eth_vmdq_rx_conf vmdq_rx_conf; } rx_adv_conf; /**< Port Rx filtering configuration. */ union { - /** Port vmdq+dcb Tx configuration. */ + /** Port VMDq+DCB Tx configuration. */ struct rte_eth_vmdq_dcb_tx_conf vmdq_dcb_tx_conf; - /** Port dcb Tx configuration. */ + /** Port DCB Tx configuration. */ struct rte_eth_dcb_tx_conf dcb_tx_conf; - /** Port vmdq Tx configuration. */ + /** Port VMDq Tx configuration. */ struct rte_eth_vmdq_tx_conf vmdq_tx_conf; } tx_adv_conf; /**< Port Tx DCB configuration (union). */ /** Currently,Priority Flow Control(PFC) are supported,if DCB with PFC @@ -1561,9 +1561,9 @@ struct rte_eth_dev_info { uint64_t flow_type_rss_offloads; struct rte_eth_rxconf default_rxconf; /**< Default Rx configuration */ struct rte_eth_txconf default_txconf; /**< Default Tx configuration */ - uint16_t vmdq_queue_base; /**< First queue ID for VMDQ pools. */ - uint16_t vmdq_queue_num; /**< Queue number for VMDQ pools. */ - uint16_t vmdq_pool_base; /**< First ID of VMDQ pools. */ + uint16_t vmdq_queue_base; /**< First queue ID for VMDq pools. */ + uint16_t vmdq_queue_num; /**< Queue number for VMDq pools. */ + uint16_t vmdq_pool_base; /**< First ID of VMDq pools. */ struct rte_eth_desc_lim rx_desc_lim; /**< Rx descriptors limits */ struct rte_eth_desc_lim tx_desc_lim; /**< Tx descriptors limits */ uint32_t speed_capa; /**< Supported speeds bitmap (ETH_LINK_SPEED_). */ @@ -4113,7 +4113,7 @@ rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id, * @param port_id * The port identifier of the Ethernet device. * @param dcb_info - * dcb information. + * DCB information. * @return * - (0) if successful. * - (-ENODEV) if port identifier is invalid.