From patchwork Thu Oct 21 09:50:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 102558 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 11D88A0547; Thu, 21 Oct 2021 11:52:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6A5ED41245; Thu, 21 Oct 2021 11:51:06 +0200 (CEST) Received: from smtpbg501.qq.com (smtpbg501.qq.com [203.205.250.101]) by mails.dpdk.org (Postfix) with ESMTP id 915DE4122A for ; Thu, 21 Oct 2021 11:51:00 +0200 (CEST) X-QQ-mid: bizesmtp38t1634809856tr3law0n Received: from jiawenwu.trustnetic.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Thu, 21 Oct 2021 17:50:56 +0800 (CST) X-QQ-SSF: 01400000000000E0I000000A0000000 X-QQ-FEAT: nnjWNCC3Pd2CzyvBEeQwrzooIfyRerEggHqd03RwnPRv+gL/51OLTXFJ6aRE1 8FmrVQILF5HoeFFmN1yCFT2e/rDNd8cUhEj9dvd0yyZVAO8ySUiMqEVrjlaqXkW5UcCmMNa 0oeqJEItx4LoEqRH4j148s5zziYOq5Dn0gQR/JaD642pq6/A4e9pOjfOIzT0RyBquRBuYA/ xnm8v1KvSlKWUCh2aynVU8lccwU6TAM/yATDmkdGIHXR5tpUG894smrsKAfYjq1aaImLiir Jm46toQdkvJ4GVgctI3giT5fhWeBpoKdHCUyCTsMFkR5rIkon1HwzHNWrdHvEdT10Qcig4s 7bA/Iy+/W6bDcpwnZ8xeAQqmzUeAVyhWisBHe6Vy5qt3S3OXYs478zEqk1iWw== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Date: Thu, 21 Oct 2021 17:50:12 +0800 Message-Id: <20211021095023.18288-16-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20211021095023.18288-1-jiawenwu@trustnetic.com> References: <20211021095023.18288-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign5 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH v2 15/26] net/ngbe: support MAC filters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add MAC addresses to filter incoming packets, support to set multicast addresses to filter. And support to set unicast table array. Signed-off-by: Jiawen Wu --- doc/guides/nics/features/ngbe.ini | 2 + doc/guides/nics/ngbe.rst | 2 +- doc/guides/rel_notes/release_21_11.rst | 2 +- drivers/net/ngbe/base/ngbe_dummy.h | 6 + drivers/net/ngbe/base/ngbe_hw.c | 135 ++++++++++++++++++- drivers/net/ngbe/base/ngbe_hw.h | 4 + drivers/net/ngbe/base/ngbe_type.h | 11 ++ drivers/net/ngbe/ngbe_ethdev.c | 175 +++++++++++++++++++++++++ drivers/net/ngbe/ngbe_ethdev.h | 12 ++ 9 files changed, 346 insertions(+), 3 deletions(-) diff --git a/doc/guides/nics/features/ngbe.ini b/doc/guides/nics/features/ngbe.ini index 209ab4ae5a..9ff1814265 100644 --- a/doc/guides/nics/features/ngbe.ini +++ b/doc/guides/nics/features/ngbe.ini @@ -15,6 +15,8 @@ Scattered Rx = Y TSO = Y Promiscuous mode = Y Allmulticast mode = Y +Unicast MAC filter = Y +Multicast MAC filter = Y VLAN filter = Y CRC offload = Y VLAN offload = Y diff --git a/doc/guides/nics/ngbe.rst b/doc/guides/nics/ngbe.rst index b8211fc66e..e460daf616 100644 --- a/doc/guides/nics/ngbe.rst +++ b/doc/guides/nics/ngbe.rst @@ -11,7 +11,7 @@ for Wangxun 1 Gigabit Ethernet NICs. Features -------- -- VLAN filtering +- MAC/VLAN filtering - Packet type information - Checksum offload - VLAN/QinQ stripping and inserting diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 9b3000c978..d6e6a41666 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -148,7 +148,7 @@ New Features * **Updated Wangxun ngbe driver.** * Added offloads and packet type on RxTx. - * Added VLAN filters. + * Added VLAN and MAC filters. * Added device basic statistics and extended stats. * **Added multi-process support for testpmd.** diff --git a/drivers/net/ngbe/base/ngbe_dummy.h b/drivers/net/ngbe/base/ngbe_dummy.h index aeeb46ccf9..7814fd6226 100644 --- a/drivers/net/ngbe/base/ngbe_dummy.h +++ b/drivers/net/ngbe/base/ngbe_dummy.h @@ -127,6 +127,11 @@ static inline s32 ngbe_mac_init_rx_addrs_dummy(struct ngbe_hw *TUP0) { return NGBE_ERR_OPS_DUMMY; } +static inline s32 ngbe_mac_update_mc_addr_list_dummy(struct ngbe_hw *TUP0, + u8 *TUP1, u32 TUP2, ngbe_mc_addr_itr TUP3, bool TUP4) +{ + return NGBE_ERR_OPS_DUMMY; +} static inline s32 ngbe_mac_clear_vfta_dummy(struct ngbe_hw *TUP0) { return NGBE_ERR_OPS_DUMMY; @@ -207,6 +212,7 @@ static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw) hw->mac.set_vmdq = ngbe_mac_set_vmdq_dummy; hw->mac.clear_vmdq = ngbe_mac_clear_vmdq_dummy; hw->mac.init_rx_addrs = ngbe_mac_init_rx_addrs_dummy; + hw->mac.update_mc_addr_list = ngbe_mac_update_mc_addr_list_dummy; hw->mac.clear_vfta = ngbe_mac_clear_vfta_dummy; hw->mac.init_thermal_sensor_thresh = ngbe_mac_init_thermal_ssth_dummy; hw->mac.check_overtemp = ngbe_mac_check_overtemp_dummy; diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c index f9fa721b67..6d2cac3137 100644 --- a/drivers/net/ngbe/base/ngbe_hw.c +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -570,6 +570,138 @@ s32 ngbe_init_rx_addrs(struct ngbe_hw *hw) return 0; } +/** + * ngbe_mta_vector - Determines bit-vector in multicast table to set + * @hw: pointer to hardware structure + * @mc_addr: the multicast address + * + * Extracts the 12 bits, from a multicast address, to determine which + * bit-vector to set in the multicast table. The hardware uses 12 bits, from + * incoming rx multicast addresses, to determine the bit-vector to check in + * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set + * by the MO field of the PSRCTRL. The MO field is set during initialization + * to mc_filter_type. + **/ +static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr) +{ + u32 vector = 0; + + DEBUGFUNC("ngbe_mta_vector"); + + switch (hw->mac.mc_filter_type) { + case 0: /* use bits [47:36] of the address */ + vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); + break; + case 1: /* use bits [46:35] of the address */ + vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); + break; + case 2: /* use bits [45:34] of the address */ + vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); + break; + case 3: /* use bits [43:32] of the address */ + vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); + break; + default: /* Invalid mc_filter_type */ + DEBUGOUT("MC filter type param set incorrectly\n"); + ASSERT(0); + break; + } + + /* vector can only be 12-bits or boundary will be exceeded */ + vector &= 0xFFF; + return vector; +} + +/** + * ngbe_set_mta - Set bit-vector in multicast table + * @hw: pointer to hardware structure + * @mc_addr: Multicast address + * + * Sets the bit-vector in the multicast table. + **/ +void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr) +{ + u32 vector; + u32 vector_bit; + u32 vector_reg; + + DEBUGFUNC("ngbe_set_mta"); + + hw->addr_ctrl.mta_in_use++; + + vector = ngbe_mta_vector(hw, mc_addr); + DEBUGOUT(" bit-vector = 0x%03X\n", vector); + + /* + * The MTA is a register array of 128 32-bit registers. It is treated + * like an array of 4096 bits. We want to set bit + * BitArray[vector_value]. So we figure out what register the bit is + * in, read it, OR in the new bit, then write back the new value. The + * register is determined by the upper 7 bits of the vector value and + * the bit within that register are determined by the lower 5 bits of + * the value. + */ + vector_reg = (vector >> 5) & 0x7F; + vector_bit = vector & 0x1F; + hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); +} + +/** + * ngbe_update_mc_addr_list - Updates MAC list of multicast addresses + * @hw: pointer to hardware structure + * @mc_addr_list: the list of new multicast addresses + * @mc_addr_count: number of addresses + * @next: iterator function to walk the multicast address list + * @clear: flag, when set clears the table beforehand + * + * When the clear flag is set, the given list replaces any existing list. + * Hashes the given addresses into the multicast table. + **/ +s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list, + u32 mc_addr_count, ngbe_mc_addr_itr next, + bool clear) +{ + u32 i; + u32 vmdq; + + DEBUGFUNC("ngbe_update_mc_addr_list"); + + /* + * Set the new number of MC addresses that we are being requested to + * use. + */ + hw->addr_ctrl.num_mc_addrs = mc_addr_count; + hw->addr_ctrl.mta_in_use = 0; + + /* Clear mta_shadow */ + if (clear) { + DEBUGOUT(" Clearing MTA\n"); + memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); + } + + /* Update mta_shadow */ + for (i = 0; i < mc_addr_count; i++) { + DEBUGOUT(" Adding the multicast addresses:\n"); + ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); + } + + /* Enable mta */ + for (i = 0; i < hw->mac.mcft_size; i++) + wr32a(hw, NGBE_MCADDRTBL(0), i, + hw->mac.mta_shadow[i]); + + if (hw->addr_ctrl.mta_in_use > 0) { + u32 psrctl = rd32(hw, NGBE_PSRCTL); + psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA); + psrctl |= NGBE_PSRCTL_MCHFENA | + NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); + wr32(hw, NGBE_PSRCTL, psrctl); + } + + DEBUGOUT("ngbe update mc addr list complete\n"); + return 0; +} + /** * ngbe_acquire_swfw_sync - Acquire SWFW semaphore * @hw: pointer to hardware structure @@ -1126,10 +1258,11 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw) mac->disable_sec_rx_path = ngbe_disable_sec_rx_path; mac->enable_sec_rx_path = ngbe_enable_sec_rx_path; - /* RAR, VLAN */ + /* RAR, VLAN, Multicast */ mac->set_rar = ngbe_set_rar; mac->clear_rar = ngbe_clear_rar; mac->init_rx_addrs = ngbe_init_rx_addrs; + mac->update_mc_addr_list = ngbe_update_mc_addr_list; mac->set_vmdq = ngbe_set_vmdq; mac->clear_vmdq = ngbe_clear_vmdq; mac->clear_vfta = ngbe_clear_vfta; diff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h index c4b94beb40..a27bd3e650 100644 --- a/drivers/net/ngbe/base/ngbe_hw.h +++ b/drivers/net/ngbe/base/ngbe_hw.h @@ -36,6 +36,9 @@ s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq, u32 enable_addr); s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index); s32 ngbe_init_rx_addrs(struct ngbe_hw *hw); +s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list, + u32 mc_addr_count, + ngbe_mc_addr_itr func, bool clear); s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw); s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw); @@ -52,6 +55,7 @@ s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw); s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw); void ngbe_disable_rx(struct ngbe_hw *hw); void ngbe_enable_rx(struct ngbe_hw *hw); +void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr); s32 ngbe_init_shared_code(struct ngbe_hw *hw); s32 ngbe_set_mac_type(struct ngbe_hw *hw); s32 ngbe_init_ops_pf(struct ngbe_hw *hw); diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index 5caefc99e5..5a88d38e84 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -12,6 +12,7 @@ #define NGBE_FRAME_SIZE_DFT (1522) /* Default frame size, +FCS */ #define NGBE_NUM_POOL (32) #define NGBE_MAX_QP (8) +#define NGBE_MAX_UTA 128 #define NGBE_ALIGN 128 /* as intel did */ #define NGBE_ISB_SIZE 16 @@ -69,6 +70,7 @@ enum ngbe_media_type { struct ngbe_hw; struct ngbe_addr_filter_info { + u32 num_mc_addrs; u32 mta_in_use; }; @@ -201,6 +203,10 @@ struct ngbe_hw_stats { }; +/* iterator type for walking multicast address lists */ +typedef u8* (*ngbe_mc_addr_itr) (struct ngbe_hw *hw, u8 **mc_addr_ptr, + u32 *vmdq); + struct ngbe_rom_info { s32 (*init_params)(struct ngbe_hw *hw); s32 (*read32)(struct ngbe_hw *hw, u32 addr, u32 *data); @@ -244,6 +250,9 @@ struct ngbe_mac_info { s32 (*set_vmdq)(struct ngbe_hw *hw, u32 rar, u32 vmdq); s32 (*clear_vmdq)(struct ngbe_hw *hw, u32 rar, u32 vmdq); s32 (*init_rx_addrs)(struct ngbe_hw *hw); + s32 (*update_mc_addr_list)(struct ngbe_hw *hw, u8 *mc_addr_list, + u32 mc_addr_count, + ngbe_mc_addr_itr func, bool clear); s32 (*clear_vfta)(struct ngbe_hw *hw); /* Manageability interface */ @@ -253,6 +262,8 @@ struct ngbe_mac_info { enum ngbe_mac_type type; u8 addr[ETH_ADDR_LEN]; u8 perm_addr[ETH_ADDR_LEN]; +#define NGBE_MAX_MTA 128 + u32 mta_shadow[NGBE_MAX_MTA]; s32 mc_filter_type; u32 mcft_size; u32 vft_size; diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index b91437840e..c72559d137 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -1627,12 +1627,16 @@ ngbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) static int ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct ngbe_hw *hw = ngbe_dev_hw(dev); dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; dev_info->min_rx_bufsize = 1024; dev_info->max_rx_pktlen = 15872; + dev_info->max_mac_addrs = hw->mac.num_rar_entries; + dev_info->max_hash_mac_addrs = NGBE_VMDQ_NUM_UC_MAC; + dev_info->max_vfs = pci_dev->max_vfs; dev_info->rx_queue_offload_capa = ngbe_get_rx_queue_offloads(dev); dev_info->rx_offload_capa = (ngbe_get_rx_port_offloads(dev) | dev_info->rx_queue_offload_capa); @@ -2129,6 +2133,36 @@ ngbe_dev_interrupt_handler(void *param) ngbe_dev_interrupt_action(dev); } +static int +ngbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, + uint32_t index, uint32_t pool) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + uint32_t enable_addr = 1; + + return ngbe_set_rar(hw, index, mac_addr->addr_bytes, + pool, enable_addr); +} + +static void +ngbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + + ngbe_clear_rar(hw, index); +} + +static int +ngbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + + ngbe_remove_rar(dev, 0); + ngbe_add_rar(dev, addr, 0, pci_dev->max_vfs); + + return 0; +} + static int ngbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) { @@ -2156,6 +2190,116 @@ ngbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) return 0; } +static uint32_t +ngbe_uta_vector(struct ngbe_hw *hw, struct rte_ether_addr *uc_addr) +{ + uint32_t vector = 0; + + switch (hw->mac.mc_filter_type) { + case 0: /* use bits [47:36] of the address */ + vector = ((uc_addr->addr_bytes[4] >> 4) | + (((uint16_t)uc_addr->addr_bytes[5]) << 4)); + break; + case 1: /* use bits [46:35] of the address */ + vector = ((uc_addr->addr_bytes[4] >> 3) | + (((uint16_t)uc_addr->addr_bytes[5]) << 5)); + break; + case 2: /* use bits [45:34] of the address */ + vector = ((uc_addr->addr_bytes[4] >> 2) | + (((uint16_t)uc_addr->addr_bytes[5]) << 6)); + break; + case 3: /* use bits [43:32] of the address */ + vector = ((uc_addr->addr_bytes[4]) | + (((uint16_t)uc_addr->addr_bytes[5]) << 8)); + break; + default: /* Invalid mc_filter_type */ + break; + } + + /* vector can only be 12-bits or boundary will be exceeded */ + vector &= 0xFFF; + return vector; +} + +static int +ngbe_uc_hash_table_set(struct rte_eth_dev *dev, + struct rte_ether_addr *mac_addr, uint8_t on) +{ + uint32_t vector; + uint32_t uta_idx; + uint32_t reg_val; + uint32_t uta_mask; + uint32_t psrctl; + + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_uta_info *uta_info = NGBE_DEV_UTA_INFO(dev); + + vector = ngbe_uta_vector(hw, mac_addr); + uta_idx = (vector >> 5) & 0x7F; + uta_mask = 0x1UL << (vector & 0x1F); + + if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask)) + return 0; + + reg_val = rd32(hw, NGBE_UCADDRTBL(uta_idx)); + if (on) { + uta_info->uta_in_use++; + reg_val |= uta_mask; + uta_info->uta_shadow[uta_idx] |= uta_mask; + } else { + uta_info->uta_in_use--; + reg_val &= ~uta_mask; + uta_info->uta_shadow[uta_idx] &= ~uta_mask; + } + + wr32(hw, NGBE_UCADDRTBL(uta_idx), reg_val); + + psrctl = rd32(hw, NGBE_PSRCTL); + if (uta_info->uta_in_use > 0) + psrctl |= NGBE_PSRCTL_UCHFENA; + else + psrctl &= ~NGBE_PSRCTL_UCHFENA; + + psrctl &= ~NGBE_PSRCTL_ADHF12_MASK; + psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); + wr32(hw, NGBE_PSRCTL, psrctl); + + return 0; +} + +static int +ngbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + struct ngbe_uta_info *uta_info = NGBE_DEV_UTA_INFO(dev); + uint32_t psrctl; + int i; + + if (on) { + for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { + uta_info->uta_shadow[i] = ~0; + wr32(hw, NGBE_UCADDRTBL(i), ~0); + } + } else { + for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { + uta_info->uta_shadow[i] = 0; + wr32(hw, NGBE_UCADDRTBL(i), 0); + } + } + + psrctl = rd32(hw, NGBE_PSRCTL); + if (on) + psrctl |= NGBE_PSRCTL_UCHFENA; + else + psrctl &= ~NGBE_PSRCTL_UCHFENA; + + psrctl &= ~NGBE_PSRCTL_ADHF12_MASK; + psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); + wr32(hw, NGBE_PSRCTL, psrctl); + + return 0; +} + /** * Set the IVAR registers, mapping interrupt causes to vectors * @param hw @@ -2248,6 +2392,31 @@ ngbe_configure_msix(struct rte_eth_dev *dev) | NGBE_ITR_WRDSA); } +static u8 * +ngbe_dev_addr_list_itr(__rte_unused struct ngbe_hw *hw, + u8 **mc_addr_ptr, u32 *vmdq) +{ + u8 *mc_addr; + + *vmdq = 0; + mc_addr = *mc_addr_ptr; + *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr)); + return mc_addr; +} + +int +ngbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, + struct rte_ether_addr *mc_addr_set, + uint32_t nb_mc_addr) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + u8 *mc_addr_list; + + mc_addr_list = (u8 *)mc_addr_set; + return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, + ngbe_dev_addr_list_itr, TRUE); +} + static const struct eth_dev_ops ngbe_eth_dev_ops = { .dev_configure = ngbe_dev_configure, .dev_infos_get = ngbe_dev_info_get, @@ -2282,6 +2451,12 @@ static const struct eth_dev_ops ngbe_eth_dev_ops = { .rx_queue_release = ngbe_dev_rx_queue_release, .tx_queue_setup = ngbe_dev_tx_queue_setup, .tx_queue_release = ngbe_dev_tx_queue_release, + .mac_addr_add = ngbe_add_rar, + .mac_addr_remove = ngbe_remove_rar, + .mac_addr_set = ngbe_set_default_mac_addr, + .uc_hash_table_set = ngbe_uc_hash_table_set, + .uc_all_hash_table_set = ngbe_uc_all_hash_table_set, + .set_mc_addr_list = ngbe_dev_set_mc_addr_list, .rx_burst_mode_get = ngbe_rx_burst_mode_get, .tx_burst_mode_get = ngbe_tx_burst_mode_get, }; diff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h index 8ffb60b8ac..e08f2e4029 100644 --- a/drivers/net/ngbe/ngbe_ethdev.h +++ b/drivers/net/ngbe/ngbe_ethdev.h @@ -59,6 +59,12 @@ struct ngbe_hwstrip { uint32_t bitmap[NGBE_HWSTRIP_BITMAP_SIZE]; }; +struct ngbe_uta_info { + uint8_t uc_filter_type; + uint16_t uta_in_use; + uint32_t uta_shadow[NGBE_MAX_UTA]; +}; + /* * Structure to store private data for each driver instance (for each port). */ @@ -69,6 +75,7 @@ struct ngbe_adapter { struct ngbe_stat_mappings stat_mappings; struct ngbe_vfta shadow_vfta; struct ngbe_hwstrip hwstrip; + struct ngbe_uta_info uta_info; bool rx_bulk_alloc_allowed; }; @@ -109,6 +116,8 @@ ngbe_dev_intr(struct rte_eth_dev *dev) #define NGBE_DEV_HWSTRIP(dev) \ (&((struct ngbe_adapter *)(dev)->data->dev_private)->hwstrip) +#define NGBE_DEV_UTA_INFO(dev) \ + (&((struct ngbe_adapter *)(dev)->data->dev_private)->uta_info) /* * Rx/Tx function prototypes @@ -218,6 +227,9 @@ struct rte_ngbe_xstats_name_off { }; const uint32_t *ngbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); +int ngbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, + struct rte_ether_addr *mc_addr_set, + uint32_t nb_mc_addr); void ngbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on); void ngbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,