diff mbox series

[v4,3/8] net/mlx5: improve Verbs flow priority discover for scalable

Message ID 20211022091142.51397-4-xuemingl@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers show
Series net/mlx5: support more than 255 representors | expand


Context Check Description
ci/checkpatch success coding style OK

Commit Message

Xueming(Steven) Li Oct. 22, 2021, 9:11 a.m. UTC
To detect number flow Verbs flow priorities, PMD try to create Verbs
flows in different priority. While Verbs is not designed to support
ports larger than 255.

When DevX supported by kernel driver, 16 Verbs priorities must be
supported, no need to create Verbs flows.

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
 drivers/net/mlx5/mlx5_flow_verbs.c | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series


diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c
index 60029f71178..3f5aaa885fb 100644
--- a/drivers/net/mlx5/mlx5_flow_verbs.c
+++ b/drivers/net/mlx5/mlx5_flow_verbs.c
@@ -83,6 +83,11 @@  mlx5_flow_discover_priorities(struct rte_eth_dev *dev)
 	int i;
 	int priority = 0;
+#if defined(HAVE_MLX5DV_DR_DEVX_PORT) || defined(HAVE_MLX5DV_DR_DEVX_PORT_V35)
+	/* If DevX supported, driver must support 16 verbs flow priorities. */
+	priority = RTE_DIM(priority_map_5);
+	goto out;
 	if (!drop->qp) {
 		rte_errno = ENOTSUP;
 		return -rte_errno;
@@ -109,6 +114,9 @@  mlx5_flow_discover_priorities(struct rte_eth_dev *dev)
 			dev->data->port_id, priority);
 		return -rte_errno;
+#if defined(HAVE_MLX5DV_DR_DEVX_PORT) || defined(HAVE_MLX5DV_DR_DEVX_PORT_V35)
 	DRV_LOG(INFO, "port %u supported flow priorities:"
 		" 0-%d for ingress or egress root table,"
 		" 0-%d for non-root table or transfer root table.",