diff mbox series

[2/2] compress/mlx5: add block size devarg

Message ID 20211026015242.21156-3-rzidane@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers show
Series fix level configuration in compress | expand

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ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-mellanox-Performance fail Performance Testing issues
ci/intel-Testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-spell-check-testing warning Testing issues
ci/github-robot: build success github build: passed
ci/checkpatch success coding style OK

Commit Message

Raja Zidane Oct. 26, 2021, 1:52 a.m. UTC
Currently, the compression block size is 15 by default, which
is the maximum.

Add "log-block-size" devarg to select compression block size manually.
The value provided should be between 4 to 15.
Any out-of-range value will be defaulted to 15.

Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 doc/guides/compressdevs/mlx5.rst       | 10 ++++
 doc/guides/rel_notes/release_21_11.rst |  2 +
 drivers/compress/mlx5/mlx5_compress.c  | 63 +++++++++++++++++++++++++-
 3 files changed, 74 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/doc/guides/compressdevs/mlx5.rst b/doc/guides/compressdevs/mlx5.rst
index 38230d4a2e..a4e17f65b3 100644
--- a/doc/guides/compressdevs/mlx5.rst
+++ b/doc/guides/compressdevs/mlx5.rst
@@ -82,6 +82,16 @@  Limitations
 * Scatter-Gather, SHA and Stateful are not supported.
 * Non-compressed block is not supported in compress (supported in decompress).
 
+Driver options
+--------------
+
+- ``log-block-size`` parameter [int]
+
+  Log of the Huffman block size in the Deflate algorithm.
+  Values from [4-15]; value x means block size is 2^x.
+  The default value is 15.
+
+
 Supported NICs
 --------------
 
diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst
index 1ccac87b73..4dccbcb386 100644
--- a/doc/guides/rel_notes/release_21_11.rst
+++ b/doc/guides/rel_notes/release_21_11.rst
@@ -305,6 +305,8 @@  New Features
     * Pcapng format with timestamps and meta-data.
     * Fixes packet capture with stripped VLAN tags.
 
+* **Updated mlx5 compress PMD.**
+  * Added devarg to allow manual setting of Huffman block size.
 
 Removed Items
 -------------
diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 9adc0e41e0..d13abba39f 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -25,6 +25,10 @@ 
 #define MLX5_COMPRESS_MAX_QPS 1024
 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
 
+struct mlx5_compress_devarg_params {
+	uint32_t log_block_sz;
+};
+
 struct mlx5_compress_xform {
 	LIST_ENTRY(mlx5_compress_xform) next;
 	enum rte_comp_xform_type type;
@@ -51,6 +55,7 @@  struct mlx5_compress_priv {
 	uint32_t mmo_comp_qp:1;
 	uint32_t mmo_dma_sq:1;
 	uint32_t mmo_dma_qp:1;
+	uint32_t log_block_sz;
 #ifndef RTE_ARCH_64
 	rte_spinlock_t uar32_sl;
 #endif /* RTE_ARCH_64 */
@@ -343,7 +348,7 @@  mlx5_compress_xform_create(struct rte_compressdev *dev,
 			xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 					 MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 						WQE_GGA_COMP_WIN_SIZE_OFFSET;
-			size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
+			size = priv->log_block_sz;
 			xfrm->gga_ctrl1 += size <<
 						WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 			xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
@@ -693,12 +698,66 @@  mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv)
 	return 0;
 }
 
+static int
+mlx5_compress_args_check_handler(const char *key, const char *val, void *opaque)
+{
+	struct mlx5_compress_devarg_params *devarg_prms = opaque;
+
+	if (strcmp(key, "log-block-size") == 0) {
+		errno = 0;
+		devarg_prms->log_block_sz = (uint32_t)strtoul(val, NULL, 10);
+		if (errno) {
+			DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer."
+				, key, val);
+			return -errno;
+		}
+		return 0;
+	}
+	return 0;
+}
+
+static int
+mlx5_compress_handle_devargs(struct rte_devargs *devargs,
+			  struct mlx5_compress_devarg_params *devarg_prms,
+			  struct mlx5_hca_attr *att)
+{
+	struct rte_kvargs *kvlist;
+
+	devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
+	if (devargs == NULL)
+		return 0;
+	kvlist = rte_kvargs_parse(devargs->args, NULL);
+	if (kvlist == NULL) {
+		DRV_LOG(ERR, "Failed to parse devargs.");
+		rte_errno = EINVAL;
+		return -1;
+	}
+	if (rte_kvargs_process(kvlist, NULL, mlx5_compress_args_check_handler,
+			   devarg_prms) != 0) {
+		DRV_LOG(ERR, "Devargs handler function Failed.");
+		rte_kvargs_free(kvlist);
+		rte_errno = EINVAL;
+		return -1;
+	}
+	rte_kvargs_free(kvlist);
+	if (devarg_prms->log_block_sz > MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX ||
+		devarg_prms->log_block_sz < att->compress_min_block_size) {
+		DRV_LOG(WARNING, "Log block size provided is out of range("
+			"%u); default it to %u.",
+			devarg_prms->log_block_sz,
+			MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX);
+		devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
+	}
+	return 0;
+}
+
 static int
 mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
 {
 	struct rte_compressdev *compressdev;
 	struct mlx5_compress_priv *priv;
 	struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
+	struct mlx5_compress_devarg_params devarg_prms = {0};
 	struct rte_compressdev_pmd_init_params init_params = {
 		.name = "",
 		.socket_id = cdev->dev->numa_node,
@@ -718,6 +777,7 @@  mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
 		rte_errno = ENOTSUP;
 		return -ENOTSUP;
 	}
+	mlx5_compress_handle_devargs(cdev->dev->devargs, &devarg_prms, attr);
 	compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,
 						 sizeof(*priv), &init_params);
 	if (compressdev == NULL) {
@@ -731,6 +791,7 @@  mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
 	compressdev->enqueue_burst = mlx5_compress_enqueue_burst;
 	compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 	priv = compressdev->data->dev_private;
+	priv->log_block_sz = devarg_prms.log_block_sz;
 	priv->mmo_decomp_sq = attr->mmo_decompress_sq_en;
 	priv->mmo_decomp_qp = attr->mmo_decompress_qp_en;
 	priv->mmo_comp_sq = attr->mmo_compress_sq_en;