From patchwork Tue Oct 26 01:52:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raja Zidane X-Patchwork-Id: 102801 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 379BDA0C47; Tue, 26 Oct 2021 03:53:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 29B5B41165; Tue, 26 Oct 2021 03:53:14 +0200 (CEST) Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam08on2041.outbound.protection.outlook.com [40.107.102.41]) by mails.dpdk.org (Postfix) with ESMTP id 9D48D410E2 for ; Tue, 26 Oct 2021 03:53:10 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=A6ZKz6dAazLh0nWWr5jS32fytZ+T4YS87U01gLRDKRSiQUG8zpmkfZj18MA7vTSLHIMDZiXzClycEEfGs1OcV9Z7XXHgIa+SAkFVYE9TddekXiG8ULRoY5dlHUYNq45Ohy09mAY5oOej3kgBTALZecDtx0wPR41dZAOiPBcDW/sE6KWf8GnF3/oknIkb8djQ+N1u7jt8jC1jCTr0+9oU4+RKxWkZnfNZvaRNMyoZFrbmn1WEZx9P+em6Qdp5CFp702e29jlfJ8GaG7XpprDoCQKhQybNfEn5pM74Ah3dmdLOqEDyVaBmhh9CubZFl9cBhXWB26mSiio12U9i3mklQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PxHFBcy8D1ZCuSWKrsoaumGdd5ZvA6fXbs5wH3OLKvc=; b=cpuSzrXlySfv9YjIVJX/mbpKwayZ5NZaDcnH2S3Fx2efZcGIfRflFSnISqkpg1KlBlsUe1Sfj6Duuc11gyzoOgody3fKee277g6Obn2/scLHlQktKZ4iMDwQe5AJ0RTjGQ5vSTysPEhjxLDCvRWXNz96l4TlMyN4XFdZHvNEzlZt1h3rLeFrPgjBMFE3kwfQaYVjkdC9Ze9gV560XU2XYtNhQ7tqikAmagQQFnLNW25DpoAmf1/RZuC0xt0ZaMFogI65ELDBn40u3oZmPGBvy5E+6rEM4u057y6xlCXZrvB8wgNcXozG8ELvYp8uj/Ec3ZyKYEfwPl5vsROwRHEJlg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PxHFBcy8D1ZCuSWKrsoaumGdd5ZvA6fXbs5wH3OLKvc=; b=QARoTaPj/C33RZOh0Kr84EWjb1pVyK3CZaUhCkyj+R1+8ON8nsB/IyrugcakcG8IvfZoMcwRGX7/uWTfFcHf17yTgi1UbarvMgAfi/tJWtfAwAwW8QwPz0Zoq6ijIFzFh5/saehFxnzABUVJdo+3TN1WdLQ3jWg8R1/tAGHTegS3qoITQAwcno0pPVdNFSdif0k/AHBCjOXX/EuhaaUHx5LROjvO/3sDPb51ayyyZLFbW3UGssf5zfE/W76jhyM+zg62p2/DjHTDa4EvXehBSBLYIPDIiJtAvRpkoId/qk3+Z2sm+4ggiq3B4gd5d4L/6Ll4Z35tm0VYHOJwRwHz6g== Received: from MWHPR12CA0059.namprd12.prod.outlook.com (2603:10b6:300:103::21) by MWHPR12MB1422.namprd12.prod.outlook.com (2603:10b6:300:10::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18; Tue, 26 Oct 2021 01:53:08 +0000 Received: from CO1NAM11FT028.eop-nam11.prod.protection.outlook.com (2603:10b6:300:103:cafe::3f) by MWHPR12CA0059.outlook.office365.com (2603:10b6:300:103::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.16 via Frontend Transport; Tue, 26 Oct 2021 01:53:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT028.mail.protection.outlook.com (10.13.175.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4628.16 via Frontend Transport; Tue, 26 Oct 2021 01:53:07 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 26 Oct 2021 01:53:05 +0000 From: Raja Zidane To: Date: Tue, 26 Oct 2021 01:52:42 +0000 Message-ID: <20211026015242.21156-3-rzidane@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211026015242.21156-1-rzidane@nvidia.com> References: <20211026015242.21156-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2995463e-5287-4242-ee67-08d998235bb0 X-MS-TrafficTypeDiagnostic: MWHPR12MB1422: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:800; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1tszZf88l9bH+0sU/Lk4auP28/j/IPJ9gY/HrfcRcwzGxKdMQJxr25iESgD+dU11L5I/zqIoo8tAm6OACsciGUoFcjeg8d3udTvHQTwe3Ocx5+6U3Eo8V7lupTGYG/OZIG4kAp3l+KKLC+Kn/2GbsxTGRsVsnXKiS+PbGZPacb8gi45Zhu9l97t6DZfT1/CrFMSS1XuAjRpuiQELJNubG4PShsz6IRTKT3fLoCXch8PUQBIrNVE7rff+EDPmX+Ugfv5K+CHB4LGfpOZP+A4qdBWpKSmavd+g90KIlzuNy39fADLvhXCsLetv2BlKbzsVv/h3s2ynVRsS/DyrEA1+bmNTPoIxURGTMyjuyXTRNCPJj7swoxn7AhZdqbpiSr6DoDn1Sz8xTPgr1TzoQcNehM2O4UhRhlnp/75KIIxJCjNSqB1IrHiUavWlRJ3uIvNGRvVEqjv3SK9CfZFij+m/y7nIVwbldHs9X2LrQpZ0w6rhokwS0sv1tnyxGedSvP2YGzE6gnsS11EDJVWgHSXiib1GwWdQYaQEFiVgfi5duvPHJRfKr5hFluNcd63ePLuXnFI5xjzBqInNr0870kHhD7+OVpr0Ad9JJStFpmeTJjqGIHQ1QpaB3trgWXcAi/0UaztERRHuPoYIqIJLaEXgaPlBg8Dj2qe/ff+lnNmv2kl3OE4X+9cUpSqfeTZw8Pc6E30GPnXhtTCuIhAtYYiL0Q== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(6916009)(6666004)(82310400003)(36860700001)(83380400001)(26005)(7696005)(36756003)(47076005)(336012)(1076003)(8936002)(86362001)(316002)(5660300002)(356005)(55016002)(2906002)(70586007)(70206006)(2616005)(426003)(8676002)(6286002)(508600001)(7636003)(186003)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2021 01:53:07.7845 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2995463e-5287-4242-ee67-08d998235bb0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1422 Subject: [dpdk-dev] [PATCH 2/2] compress/mlx5: add block size devarg X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the compression block size is 15 by default, which is the maximum. Add "log-block-size" devarg to select compression block size manually. The value provided should be between 4 to 15. Any out-of-range value will be defaulted to 15. Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- doc/guides/compressdevs/mlx5.rst | 10 ++++ doc/guides/rel_notes/release_21_11.rst | 2 + drivers/compress/mlx5/mlx5_compress.c | 63 +++++++++++++++++++++++++- 3 files changed, 74 insertions(+), 1 deletion(-) diff --git a/doc/guides/compressdevs/mlx5.rst b/doc/guides/compressdevs/mlx5.rst index 38230d4a2e..a4e17f65b3 100644 --- a/doc/guides/compressdevs/mlx5.rst +++ b/doc/guides/compressdevs/mlx5.rst @@ -82,6 +82,16 @@ Limitations * Scatter-Gather, SHA and Stateful are not supported. * Non-compressed block is not supported in compress (supported in decompress). +Driver options +-------------- + +- ``log-block-size`` parameter [int] + + Log of the Huffman block size in the Deflate algorithm. + Values from [4-15]; value x means block size is 2^x. + The default value is 15. + + Supported NICs -------------- diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 1ccac87b73..4dccbcb386 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -305,6 +305,8 @@ New Features * Pcapng format with timestamps and meta-data. * Fixes packet capture with stripped VLAN tags. +* **Updated mlx5 compress PMD.** + * Added devarg to allow manual setting of Huffman block size. Removed Items ------------- diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 9adc0e41e0..d13abba39f 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -25,6 +25,10 @@ #define MLX5_COMPRESS_MAX_QPS 1024 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u +struct mlx5_compress_devarg_params { + uint32_t log_block_sz; +}; + struct mlx5_compress_xform { LIST_ENTRY(mlx5_compress_xform) next; enum rte_comp_xform_type type; @@ -51,6 +55,7 @@ struct mlx5_compress_priv { uint32_t mmo_comp_qp:1; uint32_t mmo_dma_sq:1; uint32_t mmo_dma_qp:1; + uint32_t log_block_sz; #ifndef RTE_ARCH_64 rte_spinlock_t uar32_sl; #endif /* RTE_ARCH_64 */ @@ -343,7 +348,7 @@ mlx5_compress_xform_create(struct rte_compressdev *dev, xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), MLX5_COMP_MAX_WIN_SIZE_CONF) << WQE_GGA_COMP_WIN_SIZE_OFFSET; - size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; + size = priv->log_block_sz; xfrm->gga_ctrl1 += size << WQE_GGA_COMP_BLOCK_SIZE_OFFSET; xfrm->opcode += MLX5_OPC_MOD_MMO_COMP << @@ -693,12 +698,66 @@ mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv) return 0; } +static int +mlx5_compress_args_check_handler(const char *key, const char *val, void *opaque) +{ + struct mlx5_compress_devarg_params *devarg_prms = opaque; + + if (strcmp(key, "log-block-size") == 0) { + errno = 0; + devarg_prms->log_block_sz = (uint32_t)strtoul(val, NULL, 10); + if (errno) { + DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer." + , key, val); + return -errno; + } + return 0; + } + return 0; +} + +static int +mlx5_compress_handle_devargs(struct rte_devargs *devargs, + struct mlx5_compress_devarg_params *devarg_prms, + struct mlx5_hca_attr *att) +{ + struct rte_kvargs *kvlist; + + devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; + if (devargs == NULL) + return 0; + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) { + DRV_LOG(ERR, "Failed to parse devargs."); + rte_errno = EINVAL; + return -1; + } + if (rte_kvargs_process(kvlist, NULL, mlx5_compress_args_check_handler, + devarg_prms) != 0) { + DRV_LOG(ERR, "Devargs handler function Failed."); + rte_kvargs_free(kvlist); + rte_errno = EINVAL; + return -1; + } + rte_kvargs_free(kvlist); + if (devarg_prms->log_block_sz > MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX || + devarg_prms->log_block_sz < att->compress_min_block_size) { + DRV_LOG(WARNING, "Log block size provided is out of range(" + "%u); default it to %u.", + devarg_prms->log_block_sz, + MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX); + devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; + } + return 0; +} + static int mlx5_compress_dev_probe(struct mlx5_common_device *cdev) { struct rte_compressdev *compressdev; struct mlx5_compress_priv *priv; struct mlx5_hca_attr *attr = &cdev->config.hca_attr; + struct mlx5_compress_devarg_params devarg_prms = {0}; struct rte_compressdev_pmd_init_params init_params = { .name = "", .socket_id = cdev->dev->numa_node, @@ -718,6 +777,7 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev) rte_errno = ENOTSUP; return -ENOTSUP; } + mlx5_compress_handle_devargs(cdev->dev->devargs, &devarg_prms, attr); compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev, sizeof(*priv), &init_params); if (compressdev == NULL) { @@ -731,6 +791,7 @@ mlx5_compress_dev_probe(struct mlx5_common_device *cdev) compressdev->enqueue_burst = mlx5_compress_enqueue_burst; compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; priv = compressdev->data->dev_private; + priv->log_block_sz = devarg_prms.log_block_sz; priv->mmo_decomp_sq = attr->mmo_decompress_sq_en; priv->mmo_decomp_qp = attr->mmo_decompress_qp_en; priv->mmo_comp_sq = attr->mmo_compress_sq_en;