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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT023.mail.protection.outlook.com (10.13.173.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4628.16 via Frontend Transport; Tue, 26 Oct 2021 09:25:58 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 26 Oct 2021 09:25:56 +0000 From: Gregory Etelson To: , CC: , , Viacheslav Ovsiienko Date: Tue, 26 Oct 2021 12:25:42 +0300 Message-ID: <20211026092543.13224-1-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 131750c4-eb54-41b5-b8b8-08d998629ee2 X-MS-TrafficTypeDiagnostic: BYAPR12MB2965: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(7696005)(83380400001)(36860700001)(70206006)(47076005)(336012)(8676002)(2616005)(426003)(70586007)(508600001)(55016002)(86362001)(82310400003)(6286002)(8936002)(36906005)(2906002)(110136005)(16526019)(36756003)(4326008)(7636003)(1076003)(356005)(7049001)(186003)(316002)(5660300002)(6666004)(54906003)(107886003)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2021 09:25:58.8421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 131750c4-eb54-41b5-b8b8-08d998629ee2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2965 Subject: [dpdk-dev] [PATCH 1/2] net/mlx5: fix integrity matching for inner and outer headers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" MLX5 PMD can match on integrity bits for inner and outer headers in a single flow. That means a single flow rule can reference both inner and outer integrity bits. That is implemented by adding 2 flow integrity items to a rule - one item for outer integrity bits and other for inner integrity bits. Integrity item `level` parameter specifies what part is being targeted. Current PMD treated integrity items for outer and inner headers as the same. The patch separates PMD verifications for inner and outer integrity items. Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.h | 7 ++++--- drivers/net/mlx5/mlx5_flow_dv.c | 29 ++++++++++++++++++++++------- 2 files changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 4a16f30fb7..41e24deec5 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -170,11 +170,12 @@ enum mlx5_feature_name { #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) -/* INTEGRITY item bit */ -#define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34) +/* INTEGRITY item bits */ +#define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34) +#define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35) /* Conntrack item. */ -#define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 35) +#define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36) /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 9cba22ca2d..c27c2df5c4 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6679,6 +6679,7 @@ static int flow_dv_validate_item_integrity(struct rte_eth_dev *dev, const struct rte_flow_item *rule_items, const struct rte_flow_item *integrity_item, + uint64_t item_flags, uint64_t *last_item, struct rte_flow_error *error) { struct mlx5_priv *priv = dev->data->dev_private; @@ -6694,6 +6695,11 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ITEM, integrity_item, "packet integrity integrity_item not supported"); + if (!spec) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + integrity_item, + "no spec for integrity item"); if (!mask) mask = &rte_flow_item_integrity_mask; if (!mlx5_validate_integrity_item(mask)) @@ -6703,6 +6709,11 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev, "unsupported integrity filter"); tunnel_item = mlx5_flow_find_tunnel_item(rule_items); if (spec->level > 1) { + if (item_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) + return rte_flow_error_set + (error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, "multiple inner integrity items not supported"); if (!tunnel_item) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, @@ -6711,6 +6722,11 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev, item = tunnel_item; end_item = mlx5_find_end_item(tunnel_item); } else { + if (item_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) + return rte_flow_error_set + (error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, "multiple outer integrity items not supported"); end_item = tunnel_item ? tunnel_item : mlx5_find_end_item(integrity_item); } @@ -6730,6 +6746,8 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev, integrity_item, "missing L4 protocol"); } + *last_item |= spec->level > 1 ? MLX5_FLOW_ITEM_INNER_INTEGRITY : + MLX5_FLOW_ITEM_OUTER_INTEGRITY; return 0; } @@ -7152,16 +7170,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, last_item = MLX5_FLOW_LAYER_ECPRI; break; case RTE_FLOW_ITEM_TYPE_INTEGRITY: - if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) - return rte_flow_error_set - (error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ITEM, - NULL, "multiple integrity items not supported"); ret = flow_dv_validate_item_integrity(dev, rule_items, - items, error); + items, + item_flags, + &last_item, + error); if (ret < 0) return ret; - last_item = MLX5_FLOW_ITEM_INTEGRITY; break; case RTE_FLOW_ITEM_TYPE_CONNTRACK: ret = flow_dv_validate_item_aso_ct(dev, items,