diff mbox series

mempool/cnxk: fix max pools argument parsing

Message ID 20211026121001.2421732-1-vfialko@marvell.com (mailing list archive)
State Rejected, archived
Headers show
Series mempool/cnxk: fix max pools argument parsing | expand

Checks

Context Check Description
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-intel-Functional fail Functional Testing issues
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/intel-Testing success Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/Intel-compilation success Compilation OK
ci/github-robot: build success github build: passed
ci/checkpatch success coding style OK

Commit Message

Volodymyr Fialko Oct. 26, 2021, 12:10 p.m. UTC
roc_idev_npa_maxpools_set expects max_pools original value, not the aura

Fixes: 0a50a5aad299 ("mempool/cnxk: add device probe/remove")
Cc: stable@dpdk.org

Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/mempool/cnxk/cnxk_mempool.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c
index dc36be54f6..828bf3fc36 100644
--- a/drivers/mempool/cnxk/cnxk_mempool.c
+++ b/drivers/mempool/cnxk/cnxk_mempool.c
@@ -31,25 +31,25 @@  npa_aura_size_to_u32(uint8_t val)
 }
 
 static int
-parse_max_pools(const char *key, const char *value, void *extra_args)
+parse_max_pools_handler(const char *key, const char *value, void *extra_args)
 {
 	RTE_SET_USED(key);
 	uint32_t val;
 
-	val = atoi(value);
+	val = rte_align32pow2(atoi(value));
 	if (val < npa_aura_size_to_u32(NPA_AURA_SZ_128))
 		val = 128;
 	if (val > npa_aura_size_to_u32(NPA_AURA_SZ_1M))
 		val = BIT_ULL(20);
 
-	*(uint8_t *)extra_args = rte_log2_u32(val) - 6;
+	*(uint32_t *)extra_args = val;
 	return 0;
 }
 
-static inline uint8_t
-parse_aura_size(struct rte_devargs *devargs)
+static inline uint32_t
+parse_max_pools(struct rte_devargs *devargs)
 {
-	uint8_t aura_sz = NPA_AURA_SZ_128;
+	uint32_t max_pools = npa_aura_size_to_u32(NPA_AURA_SZ_128);
 	struct rte_kvargs *kvlist;
 
 	if (devargs == NULL)
@@ -58,11 +58,11 @@  parse_aura_size(struct rte_devargs *devargs)
 	if (kvlist == NULL)
 		goto exit;
 
-	rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM, &parse_max_pools,
-			   &aura_sz);
+	rte_kvargs_process(kvlist, CNXK_NPA_MAX_POOLS_PARAM,
+			   &parse_max_pools_handler, &max_pools);
 	rte_kvargs_free(kvlist);
 exit:
-	return aura_sz;
+	return max_pools;
 }
 
 static inline char *
@@ -92,7 +92,7 @@  npa_init(struct rte_pci_device *pci_dev)
 	dev = mz->addr;
 	dev->pci_dev = pci_dev;
 
-	roc_idev_npa_maxpools_set(parse_aura_size(pci_dev->device.devargs));
+	roc_idev_npa_maxpools_set(parse_max_pools(pci_dev->device.devargs));
 	rc = roc_npa_dev_init(dev);
 	if (rc)
 		goto mz_free;