From patchwork Tue Oct 26 17:25:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ji, Kai" X-Patchwork-Id: 102985 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 20D0FA0547; Tue, 26 Oct 2021 19:25:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1EB7B410FA; Tue, 26 Oct 2021 19:25:27 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 781AC40E0F for ; Tue, 26 Oct 2021 19:25:23 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10149"; a="228723392" X-IronPort-AV: E=Sophos;i="5.87,184,1631602800"; d="scan'208";a="228723392" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2021 10:25:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,184,1631602800"; d="scan'208";a="494305756" Received: from silpixa00400272.ir.intel.com (HELO silpixa00400272.ger.corp.intel.com) ([10.237.223.111]) by fmsmga007.fm.intel.com with ESMTP; 26 Oct 2021 10:25:21 -0700 From: Kai Ji To: dev@dpdk.org Cc: Kai Ji Date: Tue, 26 Oct 2021 18:25:12 +0100 Message-Id: <20211026172518.20183-2-kai.ji@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211026172518.20183-1-kai.ji@intel.com> References: <20211026172518.20183-1-kai.ji@intel.com> Subject: [dpdk-dev] [dpdk-dev v1 1/7] crypro/qat: qat driver refactor skeleton X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add-in enqueue/dequeue op burst and build-request skeleton functions for qat crypto driver refactor. Signed-off-by: Kai Ji Acked-by: Fan Zhang --- drivers/common/qat/qat_qp.c | 16 +++++++++++++ drivers/common/qat/qat_qp.h | 22 +++++++++++++++++ drivers/crypto/qat/qat_asym.c | 35 ++++++++++++++++++++++++++++ drivers/crypto/qat/qat_asym.h | 15 ++++++++++++ drivers/crypto/qat/qat_sym.c | 25 ++++++++++++++++++++ drivers/crypto/qat/qat_sym.h | 16 +++++++++++++ drivers/crypto/qat/qat_sym_session.h | 6 +++++ 7 files changed, 135 insertions(+) diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c index cde421eb77..0fda890075 100644 --- a/drivers/common/qat/qat_qp.c +++ b/drivers/common/qat/qat_qp.c @@ -549,6 +549,22 @@ adf_modulo(uint32_t data, uint32_t modulo_mask) return data & modulo_mask; } +uint16_t +refactor_qat_enqueue_op_burst(__rte_unused void *qp, + __rte_unused qat_op_build_request_t op_build_request, + __rte_unused void **ops, __rte_unused uint16_t nb_ops) +{ + return 0; +} + +uint16_t +refactor_qat_dequeue_op_burst(__rte_unused void *qp, __rte_unused void **ops, + __rte_unused qat_op_dequeue_t qat_dequeue_process_response, + __rte_unused uint16_t nb_ops) +{ + return 0; +} + uint16_t qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops) { diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h index deafb407b3..c5f115310c 100644 --- a/drivers/common/qat/qat_qp.h +++ b/drivers/common/qat/qat_qp.h @@ -36,6 +36,19 @@ struct qat_queue { /* number of responses processed since last CSR head write */ }; +/** + * @brief Function prototype to build a QAT request. + * @param opaque: an opaque data may be used to store context may be useful + * between 2 enqueue operations. + **/ +typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg, + void *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen); + +typedef int (*qat_op_dequeue_t)(void **op, uint8_t *resp, void *op_cookie, + uint64_t *dequeue_err_count __rte_unused); + +#define QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE 2 + struct qat_qp { void *mmap_bar_addr; struct qat_queue tx_q; @@ -44,6 +57,7 @@ struct qat_qp { struct rte_mempool *op_cookie_pool; void **op_cookies; uint32_t nb_descriptors; + uint64_t opaque[QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE]; enum qat_device_gen qat_dev_gen; enum qat_service_type service_type; struct qat_pci_device *qat_dev; @@ -77,6 +91,14 @@ struct qat_qp_config { const char *service_str; }; +uint16_t +refactor_qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request, + void **ops, uint16_t nb_ops); + +uint16_t +refactor_qat_dequeue_op_burst(void *qp, void **ops, + qat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops); + uint16_t qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops); diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c index 85973812a8..d5b4c66d68 100644 --- a/drivers/crypto/qat/qat_asym.c +++ b/drivers/crypto/qat/qat_asym.c @@ -456,6 +456,41 @@ qat_asym_fill_arrays(struct rte_crypto_asym_op *asym_op, return 0; } +static __rte_always_inline int +refactor_qat_asym_build_request(__rte_unused void *in_op, + __rte_unused uint8_t *out_msg, __rte_unused void *op_cookie, + __rte_unused uint64_t *opaque, + __rte_unused enum qat_device_gen dev_gen) +{ + return 0; +} + +int +refactor_qat_asym_process_response(__rte_unused void **op, + __rte_unused uint8_t *resp, + __rte_unused void *op_cookie, + __rte_unused uint64_t *dequeue_err_count) +{ + return 0; +} + +uint16_t +qat_asym_crypto_enqueue_op_burst(void *qp, struct rte_crypto_op **ops, + uint16_t nb_ops) +{ + return refactor_qat_enqueue_op_burst(qp, + refactor_qat_asym_build_request, + (void **)ops, nb_ops); +} + +uint16_t +qat_asym_crypto_dequeue_op_burst(void *qp, struct rte_crypto_op **ops, + uint16_t nb_ops) +{ + return refactor_qat_dequeue_op_burst(qp, (void **)ops, + refactor_qat_asym_process_response, nb_ops); +} + int qat_asym_build_request(void *in_op, uint8_t *out_msg, diff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h index 308b6b2e0b..50c2641eba 100644 --- a/drivers/crypto/qat/qat_asym.h +++ b/drivers/crypto/qat/qat_asym.h @@ -92,4 +92,19 @@ void qat_asym_process_response(void __rte_unused **op, uint8_t *resp, void *op_cookie); +int +refactor_qat_asym_process_response(__rte_unused void **op, + __rte_unused uint8_t *resp, + __rte_unused void *op_cookie, + __rte_unused uint64_t *dequeue_err_count); + +uint16_t +qat_asym_crypto_enqueue_op_burst(void *qp, struct rte_crypto_op **ops, + uint16_t nb_ops); + + +uint16_t +qat_asym_crypto_dequeue_op_burst(void *qp, struct rte_crypto_op **ops, + uint16_t nb_ops); + #endif /* _QAT_ASYM_H_ */ diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 93b257522b..a92874cd27 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -210,6 +210,31 @@ handle_spc_gmac(struct qat_sym_session *ctx, struct rte_crypto_op *op, ICP_QAT_FW_LA_NO_PROTO); } +static __rte_always_inline int +refactor_qat_sym_build_request(__rte_unused void *in_op, + __rte_unused uint8_t *out_msg, __rte_unused void *op_cookie, + __rte_unused uint64_t *opaque, + __rte_unused enum qat_device_gen dev_gen) +{ + return 0; +} + +uint16_t +refactor_qat_sym_enqueue_burst(void *qp, struct rte_crypto_op **ops, + uint16_t nb_ops) +{ + return refactor_qat_enqueue_op_burst(qp, refactor_qat_sym_build_request, + (void **)ops, nb_ops); +} + +uint16_t +refactor_qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops, + uint16_t nb_ops) +{ + return refactor_qat_dequeue_op_burst(qp, (void **)ops, + refactor_qat_sym_process_response, nb_ops); +} + int qat_sym_build_request(void *in_op, uint8_t *out_msg, void *op_cookie, enum qat_device_gen qat_dev_gen) diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h index e3ec7f0de4..17b2c871bd 100644 --- a/drivers/crypto/qat/qat_sym.h +++ b/drivers/crypto/qat/qat_sym.h @@ -54,6 +54,22 @@ struct qat_sym_op_cookie { } opt; }; +static __rte_always_inline int +refactor_qat_sym_process_response(__rte_unused void **op, + __rte_unused uint8_t *resp, __rte_unused void *op_cookie, + __rte_unused uint64_t *dequeue_err_count) +{ + return 0; +} + +uint16_t +refactor_qat_sym_enqueue_burst(void *qp, struct rte_crypto_op **ops, + uint16_t nb_ops); + +uint16_t +refactor_qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops, + uint16_t nb_ops); + int qat_sym_build_request(void *in_op, uint8_t *out_msg, void *op_cookie, enum qat_device_gen qat_dev_gen); diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h index 6ebc176729..73493ec864 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -55,6 +55,11 @@ #define QAT_SESSION_IS_SLICE_SET(flags, flag) \ (!!((flags) & (flag))) +struct qat_sym_session; + +typedef int (*qat_sym_build_request_t)(void *in_op, struct qat_sym_session *ctx, + uint8_t *out_msg, void *op_cookie); + enum qat_sym_proto_flag { QAT_CRYPTO_PROTO_FLAG_NONE = 0, QAT_CRYPTO_PROTO_FLAG_CCM = 1, @@ -107,6 +112,7 @@ struct qat_sym_session { /* Some generations need different setup of counter */ uint32_t slice_types; enum qat_sym_proto_flag qat_proto_flag; + qat_sym_build_request_t build_request[2]; }; int