From patchwork Mon Nov 1 17:44:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 103356 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7DFAEA0548; Mon, 1 Nov 2021 18:44:22 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 45B1140E28; Mon, 1 Nov 2021 18:44:22 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 31C1C40DF6 for ; Mon, 1 Nov 2021 18:44:21 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A1HYrTv008745 for ; Mon, 1 Nov 2021 10:44:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=zLFyzILiqB/I289Q6c/aRSy/0euXLvCC79Bhc1/CSWI=; b=MFfxtk9hVlKqo/IzGf2J+HlCkUXVYzRWpcItV/9EZGGr25mHj9FnR3ocx3xP/xjo6Lpa 5QkpWkn6E1GFp0i6mgGjNzTpRb30jvkaVEzT28kzarFNyj2cy0rqF9AUikOOxrQsnQ7i XQjs8nrEqxyVpUdOaoXzssq6PHhN0ZOjd9WQhWcjw+owSx6wdEnm0+TOl2X2czgkCbgF qSecZShkskuxUjkBaWjA41mLtAQhtSvbMH8HVxZBtAA0I5sDrTWdTol7DDORY4Zg6+HQ GemixXKXuhyMIe83FkTe8f8GendlenfJnvArCjSDrD2136dEGc069ODnwwaySuZDoG0N BA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3c25c4br0w-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 01 Nov 2021 10:44:20 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 1 Nov 2021 10:44:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 1 Nov 2021 10:44:18 -0700 Received: from localhost.marvell.com (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 86EF13F70C7; Mon, 1 Nov 2021 10:44:16 -0700 (PDT) From: Harman Kalra To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Harman Kalra Date: Mon, 1 Nov 2021 23:14:07 +0530 Message-ID: <20211101174407.81854-1-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Hj4yz4CpG6v7B3GUMNtgEVkXkHqPfGCI X-Proofpoint-GUID: Hj4yz4CpG6v7B3GUMNtgEVkXkHqPfGCI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-01_06,2021-11-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH] common/cnxk: fix device MSIX greater than default value X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Handling the case where number of MSIX interrupts are greater than default value i.e. PLT_MAX_RXTX_INTR_VEC_ID. On PCI probe device is queried for supported MSIX interrupts, and respective interrupt resources are reallocated with this value. Same MSIX count should be used while registering new interrupt vectors. Fixes: d61138d4f0e2 ("drivers: remove direct access to interrupt handle") Signed-off-by: Harman Kalra --- drivers/common/cnxk/roc_irq.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/common/cnxk/roc_irq.c b/drivers/common/cnxk/roc_irq.c index 3b34467b96..7a24297d72 100644 --- a/drivers/common/cnxk/roc_irq.c +++ b/drivers/common/cnxk/roc_irq.c @@ -14,7 +14,8 @@ #include #define MSIX_IRQ_SET_BUF_LEN \ - (sizeof(struct vfio_irq_set) + sizeof(int) * (PLT_MAX_RXTX_INTR_VEC_ID)) + (sizeof(struct vfio_irq_set) + sizeof(int) * \ + (plt_intr_max_intr_get(intr_handle))) static int irq_get_info(struct plt_intr_handle *intr_handle) @@ -34,7 +35,7 @@ irq_get_info(struct plt_intr_handle *intr_handle) plt_base_dbg("Flags=0x%x index=0x%x count=0x%x max_intr_vec_id=0x%x", irq.flags, irq.index, irq.count, PLT_MAX_RXTX_INTR_VEC_ID); - if (irq.count > PLT_MAX_RXTX_INTR_VEC_ID) { + if (irq.count == 0) { plt_err("HW max=%d > PLT_MAX_RXTX_INTR_VEC_ID: %d", irq.count, PLT_MAX_RXTX_INTR_VEC_ID); plt_intr_max_intr_set(intr_handle, PLT_MAX_RXTX_INTR_VEC_ID); @@ -92,14 +93,6 @@ irq_init(struct plt_intr_handle *intr_handle) int32_t *fd_ptr; uint32_t i; - if (plt_intr_max_intr_get(intr_handle) > - PLT_MAX_RXTX_INTR_VEC_ID) { - plt_err("Max_intr=%d greater than PLT_MAX_RXTX_INTR_VEC_ID=%d", - plt_intr_max_intr_get(intr_handle), - PLT_MAX_RXTX_INTR_VEC_ID); - return -ERANGE; - } - len = sizeof(struct vfio_irq_set) + sizeof(int32_t) * plt_intr_max_intr_get(intr_handle);