diff mbox series

[v2] net/ice: fix order of flow filter parser list

Message ID 20211102104505.961727-1-yuying.zhang@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Qi Zhang
Headers show
Series [v2] net/ice: fix order of flow filter parser list | expand

Checks

Context Check Description
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance fail Performance Testing issues
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/intel-Testing success Testing PASS
ci/Intel-compilation fail Compilation issues
ci/github-robot: build success github build: passed
ci/checkpatch warning coding style issues

Commit Message

Yuying Zhang Nov. 2, 2021, 10:45 a.m. UTC
The order of flow filter parser list was not definite and
linked to the register order of parsers. It caused ACL filter
covered by switch filter in some cases.

This patch fixed order of parser list to guarantee the usage
of each filter. Below lists the order.
ACL filter > Switch filter > FDIR > Hash filter.

Fixes: e4a0a7599d97 ("net/ice: fix flow priority support in non-pipeline mode")
Cc: stable@dpdk.org

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
---
v2:
* Fix the spelling mistake in commit log.
---
 drivers/net/ice/ice_generic_flow.c | 33 +++++++++++++++++++++++++-----
 1 file changed, 28 insertions(+), 5 deletions(-)

Comments

Qi Zhang Nov. 4, 2021, 10:47 a.m. UTC | #1
> -----Original Message-----
> From: Zhang, Yuying <yuying.zhang@intel.com>
> Sent: Tuesday, November 2, 2021 6:45 PM
> To: dev@dpdk.org; Zhang, Qi Z <qi.z.zhang@intel.com>; Zhang, Yuying
> <yuying.zhang@intel.com>
> Cc: stable@dpdk.org
> Subject: [PATCH v2] net/ice: fix order of flow filter parser list
> 
> The order of flow filter parser list was not definite and linked to the register
> order of parsers. It caused ACL filter covered by switch filter in some cases.
> 
> This patch fixed order of parser list to guarantee the usage of each filter. Below
> lists the order.
> ACL filter > Switch filter > FDIR > Hash filter.
> 
> Fixes: e4a0a7599d97 ("net/ice: fix flow priority support in non-pipeline
> mode")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>

Acked-by: Qi Zhang <qi.z.zhang@intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi
diff mbox series

Patch

diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c
index 02f854666a..8e3e2e04d6 100644
--- a/drivers/net/ice/ice_generic_flow.c
+++ b/drivers/net/ice/ice_generic_flow.c
@@ -1906,6 +1906,8 @@  ice_register_parser(struct ice_flow_parser *parser,
 {
 	struct ice_parser_list *list;
 	struct ice_flow_parser_node *parser_node;
+	struct ice_flow_parser_node *existing_node;
+	void *temp;
 
 	parser_node = rte_zmalloc("ice_parser", sizeof(*parser_node), 0);
 	if (parser_node == NULL) {
@@ -1921,16 +1923,37 @@  ice_register_parser(struct ice_flow_parser *parser,
 	if (ad->devargs.pipe_mode_support) {
 		TAILQ_INSERT_TAIL(list, parser_node, node);
 	} else {
-		if (parser->engine->type == ICE_FLOW_ENGINE_SWITCH ||
-				parser->engine->type == ICE_FLOW_ENGINE_HASH)
+		if (parser->engine->type == ICE_FLOW_ENGINE_SWITCH) {
+			RTE_TAILQ_FOREACH_SAFE(existing_node, list,
+					       node, temp) {
+				if (existing_node->parser->engine->type ==
+				    ICE_FLOW_ENGINE_ACL) {
+					TAILQ_INSERT_AFTER(list, existing_node,
+							   parser_node, node);
+					goto DONE;
+				}
+			}
+			TAILQ_INSERT_HEAD(list, parser_node, node);
+		} else if (parser->engine->type == ICE_FLOW_ENGINE_FDIR) {
+			RTE_TAILQ_FOREACH_SAFE(existing_node, list,
+					       node, temp) {
+				if (existing_node->parser->engine->type ==
+				    ICE_FLOW_ENGINE_SWITCH) {
+					TAILQ_INSERT_AFTER(list, existing_node,
+							   parser_node, node);
+					goto DONE;
+				}
+			}
 			TAILQ_INSERT_HEAD(list, parser_node, node);
-		else if (parser->engine->type == ICE_FLOW_ENGINE_FDIR)
+		} else if (parser->engine->type == ICE_FLOW_ENGINE_HASH) {
 			TAILQ_INSERT_TAIL(list, parser_node, node);
-		else if (parser->engine->type == ICE_FLOW_ENGINE_ACL)
+		} else if (parser->engine->type == ICE_FLOW_ENGINE_ACL) {
 			TAILQ_INSERT_HEAD(list, parser_node, node);
-		else
+		} else {
 			return -EINVAL;
+		}
 	}
+DONE:
 	return 0;
 }