From patchwork Tue Nov 2 10:45:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yuying" X-Patchwork-Id: 103439 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BDABFA0C4E; Tue, 2 Nov 2021 08:03:18 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A89E7410FF; Tue, 2 Nov 2021 08:03:18 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 5137A410FF; Tue, 2 Nov 2021 08:03:16 +0100 (CET) X-IronPort-AV: E=McAfee;i="6200,9189,10155"; a="231153176" X-IronPort-AV: E=Sophos;i="5.87,202,1631602800"; d="scan'208";a="231153176" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2021 00:03:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,202,1631602800"; d="scan'208";a="488983683" Received: from dpdk-yyzhang2.sh.intel.com ([10.67.117.57]) by orsmga007.jf.intel.com with ESMTP; 02 Nov 2021 00:03:13 -0700 From: Yuying Zhang To: dev@dpdk.org, qi.z.zhang@intel.com, yuying.zhang@intel.com Cc: stable@dpdk.org Date: Tue, 2 Nov 2021 10:45:05 +0000 Message-Id: <20211102104505.961727-1-yuying.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2] net/ice: fix order of flow filter parser list X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The order of flow filter parser list was not definite and linked to the register order of parsers. It caused ACL filter covered by switch filter in some cases. This patch fixed order of parser list to guarantee the usage of each filter. Below lists the order. ACL filter > Switch filter > FDIR > Hash filter. Fixes: e4a0a7599d97 ("net/ice: fix flow priority support in non-pipeline mode") Cc: stable@dpdk.org Signed-off-by: Yuying Zhang Acked-by: Qi Zhang --- v2: * Fix the spelling mistake in commit log. --- drivers/net/ice/ice_generic_flow.c | 33 +++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c index 02f854666a..8e3e2e04d6 100644 --- a/drivers/net/ice/ice_generic_flow.c +++ b/drivers/net/ice/ice_generic_flow.c @@ -1906,6 +1906,8 @@ ice_register_parser(struct ice_flow_parser *parser, { struct ice_parser_list *list; struct ice_flow_parser_node *parser_node; + struct ice_flow_parser_node *existing_node; + void *temp; parser_node = rte_zmalloc("ice_parser", sizeof(*parser_node), 0); if (parser_node == NULL) { @@ -1921,16 +1923,37 @@ ice_register_parser(struct ice_flow_parser *parser, if (ad->devargs.pipe_mode_support) { TAILQ_INSERT_TAIL(list, parser_node, node); } else { - if (parser->engine->type == ICE_FLOW_ENGINE_SWITCH || - parser->engine->type == ICE_FLOW_ENGINE_HASH) + if (parser->engine->type == ICE_FLOW_ENGINE_SWITCH) { + RTE_TAILQ_FOREACH_SAFE(existing_node, list, + node, temp) { + if (existing_node->parser->engine->type == + ICE_FLOW_ENGINE_ACL) { + TAILQ_INSERT_AFTER(list, existing_node, + parser_node, node); + goto DONE; + } + } + TAILQ_INSERT_HEAD(list, parser_node, node); + } else if (parser->engine->type == ICE_FLOW_ENGINE_FDIR) { + RTE_TAILQ_FOREACH_SAFE(existing_node, list, + node, temp) { + if (existing_node->parser->engine->type == + ICE_FLOW_ENGINE_SWITCH) { + TAILQ_INSERT_AFTER(list, existing_node, + parser_node, node); + goto DONE; + } + } TAILQ_INSERT_HEAD(list, parser_node, node); - else if (parser->engine->type == ICE_FLOW_ENGINE_FDIR) + } else if (parser->engine->type == ICE_FLOW_ENGINE_HASH) { TAILQ_INSERT_TAIL(list, parser_node, node); - else if (parser->engine->type == ICE_FLOW_ENGINE_ACL) + } else if (parser->engine->type == ICE_FLOW_ENGINE_ACL) { TAILQ_INSERT_HEAD(list, parser_node, node); - else + } else { return -EINVAL; + } } +DONE: return 0; }