diff mbox series

[1/1] net/mlx5: fix modify field action conversion mask

Message ID 20211108141131.16128-1-viacheslavo@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series [1/1] net/mlx5: fix modify field action conversion mask |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/github-robot: build success github build: passed
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS

Commit Message

Slava Ovsiienko Nov. 8, 2021, 2:11 p.m. UTC 
  The routine converting RTE flow modify field action into
field driver's presentation did not specify the field mask
correctly and this resulted into wrong conversion for
the actions with shifted fields.

Fixes: 40c8fb1fd3b3 ("net/mlx5: update modify field action")

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 46 ++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 24 deletions(-)

Comments

Raslan Darawsheh Nov. 10, 2021, 8:50 a.m. UTC | #1 
Hi,
h

> -----Original Message-----
> From: Slava Ovsiienko <viacheslavo@nvidia.com>
> Sent: Monday, November 8, 2021 4:12 PM
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; Alexander Kozyrev <akozyrev@nvidia.com>
> Subject: [PATCH 1/1] net/mlx5: fix modify field action conversion mask
> 
> The routine converting RTE flow modify field action into
> field driver's presentation did not specify the field mask
> correctly and this resulted into wrong conversion for
> the actions with shifted fields.
> 
> Fixes: 40c8fb1fd3b3 ("net/mlx5: update modify field action")
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawshe
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 842ada2ea9..de7923e288 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1470,11 +1470,11 @@  mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){2, 4,
 						MLX5_MODI_OUT_DMAC_15_0};
 				if (width < 16) {
-					mask[idx] = rte_cpu_to_be_16(0xffff >>
+					mask[1] = rte_cpu_to_be_16(0xffff >>
 								 (16 - width));
 					width = 0;
 				} else {
-					mask[idx] = RTE_BE16(0xffff);
+					mask[1] = RTE_BE16(0xffff);
 					width -= 16;
 				}
 				if (!width)
@@ -1483,8 +1483,8 @@  mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){4, 0,
 						MLX5_MODI_OUT_DMAC_47_16};
-			mask[idx] = rte_cpu_to_be_32((0xffffffff >>
-						      (32 - width)) << off);
+			mask[0] = rte_cpu_to_be_32((0xffffffff >>
+						    (32 - width)) << off);
 		} else {
 			if (data->offset < 16)
 				info[idx++] = (struct field_modify_info){2, 4,
@@ -1500,11 +1500,11 @@  mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){2, 4,
 						MLX5_MODI_OUT_SMAC_15_0};
 				if (width < 16) {
-					mask[idx] = rte_cpu_to_be_16(0xffff >>
+					mask[1] = rte_cpu_to_be_16(0xffff >>
 								 (16 - width));
 					width = 0;
 				} else {
-					mask[idx] = RTE_BE16(0xffff);
+					mask[1] = RTE_BE16(0xffff);
 					width -= 16;
 				}
 				if (!width)
@@ -1513,8 +1513,8 @@  mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){4, 0,
 						MLX5_MODI_OUT_SMAC_47_16};
-			mask[idx] = rte_cpu_to_be_32((0xffffffff >>
-						      (32 - width)) << off);
+			mask[0] = rte_cpu_to_be_32((0xffffffff >>
+						    (32 - width)) << off);
 		} else {
 			if (data->offset < 16)
 				info[idx++] = (struct field_modify_info){2, 4,
@@ -1582,12 +1582,12 @@  mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4, 12,
 						MLX5_MODI_OUT_SIPV6_31_0};
 				if (width < 32) {
-					mask[idx] =
+					mask[3] =
 						rte_cpu_to_be_32(0xffffffff >>
 								 (32 - width));
 					width = 0;
 				} else {
-					mask[idx] = RTE_BE32(0xffffffff);
+					mask[3] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1598,12 +1598,12 @@  mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4, 8,
 						MLX5_MODI_OUT_SIPV6_63_32};
 				if (width < 32) {
-					mask[idx] =
+					mask[2] =
 						rte_cpu_to_be_32(0xffffffff >>
 								 (32 - width));
 					width = 0;
 				} else {
-					mask[idx] = RTE_BE32(0xffffffff);
+					mask[2] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1614,12 +1614,12 @@  mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4, 4,
 						MLX5_MODI_OUT_SIPV6_95_64};
 				if (width < 32) {
-					mask[idx] =
+					mask[1] =
 						rte_cpu_to_be_32(0xffffffff >>
 								 (32 - width));
 					width = 0;
 				} else {
-					mask[idx] = RTE_BE32(0xffffffff);
+					mask[1] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1628,8 +1628,7 @@  mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){4, 0,
 						MLX5_MODI_OUT_SIPV6_127_96};
-			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
-						     (32 - width));
+			mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
 		} else {
 			if (data->offset < 32)
 				info[idx++] = (struct field_modify_info){4, 12,
@@ -1651,12 +1650,12 @@  mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4, 12,
 						MLX5_MODI_OUT_DIPV6_31_0};
 				if (width < 32) {
-					mask[idx] =
+					mask[3] =
 						rte_cpu_to_be_32(0xffffffff >>
 								 (32 - width));
 					width = 0;
 				} else {
-					mask[idx] = RTE_BE32(0xffffffff);
+					mask[3] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1667,12 +1666,12 @@  mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4, 8,
 						MLX5_MODI_OUT_DIPV6_63_32};
 				if (width < 32) {
-					mask[idx] =
+					mask[2] =
 						rte_cpu_to_be_32(0xffffffff >>
 								 (32 - width));
 					width = 0;
 				} else {
-					mask[idx] = RTE_BE32(0xffffffff);
+					mask[2] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1683,12 +1682,12 @@  mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4, 4,
 						MLX5_MODI_OUT_DIPV6_95_64};
 				if (width < 32) {
-					mask[idx] =
+					mask[1] =
 						rte_cpu_to_be_32(0xffffffff >>
 								 (32 - width));
 					width = 0;
 				} else {
-					mask[idx] = RTE_BE32(0xffffffff);
+					mask[1] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1697,8 +1696,7 @@  mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){4, 0,
 						MLX5_MODI_OUT_DIPV6_127_96};
-			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
-						     (32 - width));
+			mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
 		} else {
 			if (data->offset < 32)
 				info[idx++] = (struct field_modify_info){4, 12,