diff mbox series

common/mlx5: fix user mode register access attribute

Message ID 20211117105709.2059941-1-michaelba@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series common/mlx5: fix user mode register access attribute |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/github-robot: build success github build: passed
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS

Commit Message

Michael Baum Nov. 17, 2021, 10:57 a.m. UTC 
  From: Michael Baum <michaelba@nvidia.com>

To detect the timestamp mode configured on the NIC the mlx5 PMD uses the
firmware command ACCESS_REGISTER_USER.
The HCA capability command has an attribute flag checking whether
firmware supports the command.

However, the HCA capability query command read the flag from wrong place
in PRM structure.

This patch move the plag to correct place.

Fixes: 972a1bf8120d ("common/mlx5: fix user mode register access command")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Raslan Darawsheh Nov. 17, 2021, 2:43 p.m. UTC | #1 
Hi,

> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: Wednesday, November 17, 2021 12:57 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>; Michael
> Baum <michaelba@nvidia.com>; stable@dpdk.org
> Subject: [PATCH] common/mlx5: fix user mode register access attribute
> 
> From: Michael Baum <michaelba@nvidia.com>
> 
> To detect the timestamp mode configured on the NIC the mlx5 PMD uses
> the
> firmware command ACCESS_REGISTER_USER.
> The HCA capability command has an attribute flag checking whether
> firmware supports the command.
> 
> However, the HCA capability query command read the flag from wrong place
> in PRM structure.
> 
> This patch move the plag to correct place.
> 
> Fixes: 972a1bf8120d ("common/mlx5: fix user mode register access
> command")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Michael Baum <michaelba@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 13959575e3..2ded67e85e 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1370,13 +1370,14 @@  struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 reserved_at_bc[0x4];
 	u8 reserved_at_c0[0x8];
 	u8 log_max_cq_sz[0x8];
-	u8 reserved_at_d0[0xb];
+	u8 reserved_at_d0[0x2];
+	u8 access_register_user[0x1];
+	u8 reserved_at_d3[0x8];
 	u8 log_max_cq[0x5];
 	u8 log_max_eq_sz[0x8];
 	u8 relaxed_ordering_write[0x1];
 	u8 relaxed_ordering_read[0x1];
-	u8 access_register_user[0x1];
-	u8 log_max_mkey[0x5];
+	u8 log_max_mkey[0x6];
 	u8 reserved_at_f0[0x8];
 	u8 dump_fill_mkey[0x1];
 	u8 reserved_at_f9[0x3];