From patchwork Fri Nov 26 23:51:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Dumitrescu X-Patchwork-Id: 104721 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CE78EA0C43; Sat, 27 Nov 2021 00:51:49 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3CC564275B; Sat, 27 Nov 2021 00:51:38 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 700394273A for ; Sat, 27 Nov 2021 00:51:35 +0100 (CET) X-IronPort-AV: E=McAfee;i="6200,9189,10180"; a="299130311" X-IronPort-AV: E=Sophos;i="5.87,267,1631602800"; d="scan'208";a="299130311" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2021 15:51:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,267,1631602800"; d="scan'208";a="510837566" Received: from silpixa00400573.ir.intel.com (HELO silpixa00400573.ger.corp.intel.com) ([10.237.223.107]) by orsmga008.jf.intel.com with ESMTP; 26 Nov 2021 15:51:33 -0800 From: Cristian Dumitrescu To: dev@dpdk.org Cc: yogesh.jangra@intel.com Subject: [PATCH 4/4] pipeline: add drop port for each pipeline Date: Fri, 26 Nov 2021 23:51:29 +0000 Message-Id: <20211126235129.35781-4-cristian.dumitrescu@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211126235129.35781-1-cristian.dumitrescu@intel.com> References: <20211126235129.35781-1-cristian.dumitrescu@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org An additional output port is now implicitly created for every pipeline to seve as the packet drop port. Up to now, the drop port had to be explicitly created for each pipeline. Signed-off-by: Cristian Dumitrescu Signed-off-by: Yogesh Jangra --- examples/pipeline/cli.c | 15 +++++++++++---- examples/pipeline/examples/fib.cli | 1 - examples/pipeline/examples/learner.cli | 1 - examples/pipeline/examples/selector.cli | 1 - examples/pipeline/examples/varbit.cli | 1 - examples/pipeline/examples/vxlan.cli | 1 - examples/pipeline/examples/vxlan_pcap.cli | 1 - lib/pipeline/rte_swx_pipeline.c | 11 +++++++++++ 8 files changed, 22 insertions(+), 10 deletions(-) diff --git a/examples/pipeline/cli.c b/examples/pipeline/cli.c index 83b460caf6..c32349e5f0 100644 --- a/examples/pipeline/cli.c +++ b/examples/pipeline/cli.c @@ -2551,10 +2551,17 @@ cmd_pipeline_stats(char **tokens, rte_swx_ctl_pipeline_port_out_stats_read(p->p, i, &stats); - snprintf(out, out_size, "\tPort %u:" - " packets %" PRIu64 - " bytes %" PRIu64 "\n", - i, stats.n_pkts, stats.n_bytes); + if (i != info.n_ports_out - 1) + snprintf(out, out_size, "\tPort %u:" + " packets %" PRIu64 + " bytes %" PRIu64 "\n", + i, stats.n_pkts, stats.n_bytes); + else + snprintf(out, out_size, "\tDROP:" + " packets %" PRIu64 + " bytes %" PRIu64 "\n", + stats.n_pkts, stats.n_bytes); + out_size -= strlen(out); out += strlen(out); } diff --git a/examples/pipeline/examples/fib.cli b/examples/pipeline/examples/fib.cli index b20aed3cf6..93ab2b08f8 100644 --- a/examples/pipeline/examples/fib.cli +++ b/examples/pipeline/examples/fib.cli @@ -25,7 +25,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32 -pipeline PIPELINE0 port out 4 sink none pipeline PIPELINE0 build ./examples/pipeline/examples/fib.spec diff --git a/examples/pipeline/examples/learner.cli b/examples/pipeline/examples/learner.cli index af7792624f..688ce34f34 100644 --- a/examples/pipeline/examples/learner.cli +++ b/examples/pipeline/examples/learner.cli @@ -25,7 +25,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32 -pipeline PIPELINE0 port out 4 sink none pipeline PIPELINE0 build ./examples/pipeline/examples/learner.spec diff --git a/examples/pipeline/examples/selector.cli b/examples/pipeline/examples/selector.cli index 36f3ead541..123782c57b 100644 --- a/examples/pipeline/examples/selector.cli +++ b/examples/pipeline/examples/selector.cli @@ -19,7 +19,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32 -pipeline PIPELINE0 port out 4 sink none pipeline PIPELINE0 build ./examples/pipeline/examples/selector.spec diff --git a/examples/pipeline/examples/varbit.cli b/examples/pipeline/examples/varbit.cli index 0589e32c15..9caeb9ca26 100644 --- a/examples/pipeline/examples/varbit.cli +++ b/examples/pipeline/examples/varbit.cli @@ -25,7 +25,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32 -pipeline PIPELINE0 port out 4 sink none pipeline PIPELINE0 build ./examples/pipeline/examples/varbit.spec diff --git a/examples/pipeline/examples/vxlan.cli b/examples/pipeline/examples/vxlan.cli index a3bde6a9f9..444f3f7bd8 100644 --- a/examples/pipeline/examples/vxlan.cli +++ b/examples/pipeline/examples/vxlan.cli @@ -19,7 +19,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32 -pipeline PIPELINE0 port out 4 sink none pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec pipeline PIPELINE0 table vxlan_table add ./examples/pipeline/examples/vxlan_table.txt diff --git a/examples/pipeline/examples/vxlan_pcap.cli b/examples/pipeline/examples/vxlan_pcap.cli index c03dc9303d..83fca8d0d9 100644 --- a/examples/pipeline/examples/vxlan_pcap.cli +++ b/examples/pipeline/examples/vxlan_pcap.cli @@ -14,7 +14,6 @@ pipeline PIPELINE0 port out 0 sink none pipeline PIPELINE0 port out 1 sink none pipeline PIPELINE0 port out 2 sink none pipeline PIPELINE0 port out 3 sink none -pipeline PIPELINE0 port out 4 sink none pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec pipeline PIPELINE0 table vxlan_table add ./examples/pipeline/examples/vxlan_table.txt diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c index a05a4edc7d..9dfbe9bb7f 100644 --- a/lib/pipeline/rte_swx_pipeline.c +++ b/lib/pipeline/rte_swx_pipeline.c @@ -9199,6 +9199,9 @@ pipeline_compile(struct rte_swx_pipeline *p); int rte_swx_pipeline_build(struct rte_swx_pipeline *p) { + struct rte_swx_port_sink_params drop_port_params = { + .file_name = NULL, + }; int status; CHECK(p, EINVAL); @@ -9208,6 +9211,14 @@ rte_swx_pipeline_build(struct rte_swx_pipeline *p) if (status) goto error; + /* Drop port. */ + status = rte_swx_pipeline_port_out_config(p, + p->n_ports_out, + "sink", + &drop_port_params); + if (status) + goto error; + status = port_out_build(p); if (status) goto error;