From patchwork Tue Nov 30 05:48:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 104769 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AEA3EA0C58; Tue, 30 Nov 2021 06:50:06 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4E1F34068F; Tue, 30 Nov 2021 06:50:06 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E56C94068B for ; Tue, 30 Nov 2021 06:50:04 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1AU01luS025977 for ; Mon, 29 Nov 2021 21:50:04 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ycyWnGdOHhoh4IgxY6xYxP64Jntwtbrj9yo6rSBWG9g=; b=VSzeghCuHVC7TMlJkHxKOPx+7M041mU6nQqYFAN+rDZfulLO6B2ZB1hT9/6Y0gSuzGTi YzFKbthpiRCCYWZKyR8ENv4hFaWclbNGwffZIdQkP2HsQn+709xqH+EDidyrfadmtybh Qa0BFPe9evSp8/NcJt2t+mRpKRLLZTU6Mve6twyPUxbvIi7KeRidTkXYkvUMNZ7Tq2YY BrCEGQQLl9iOX0NUDLugx/nSnVEdSqtrFA0/YGMquJuf+ZQ4yenljhDTjKwoGLxmOGpq ZUy5sveeULi+DCrtKvNYR+0jNQkIRnNdz6m7r2rLUZ98fS47y6fdF4LuGH0I9vT28tGu XQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cn23wu1y2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 29 Nov 2021 21:50:03 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 29 Nov 2021 21:50:02 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 29 Nov 2021 21:50:02 -0800 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 90A5F3F7073; Mon, 29 Nov 2021 21:49:58 -0800 (PST) From: Ashwin Sekhar T K To: CC: , , , , , , , , , Subject: [PATCH] common/cnxk: update cpu directive in NPA assembly code Date: Tue, 30 Nov 2021 11:18:09 +0530 Message-ID: <20211130054809.2697001-1-asekhar@marvell.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: LQasaCo8B-kV-MDErYDc39E6xQ3KsJWV X-Proofpoint-GUID: LQasaCo8B-kV-MDErYDc39E6xQ3KsJWV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-30_04,2021-11-28_01,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update the CPU directive in ROC NPA assembly code snippets. Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_npa.h | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 46350fdb48..aeadc3d5e2 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -433,7 +433,7 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t *buf, unsigned int num, switch (num) { case 30: asm volatile( - ".cpu generic+lse\n" + ".arch_extension lse\n" "mov v18.d[0], %[dst]\n" "mov v18.d[1], %[loc]\n" "mov v19.d[0], %[wdata]\n" @@ -497,7 +497,7 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t *buf, unsigned int num, break; case 16: asm volatile( - ".cpu generic+lse\n" + ".arch_extension lse\n" "mov x16, %[wdata]\n" "mov x17, %[wdata]\n" "casp x0, x1, x16, x17, [%[loc]]\n" @@ -517,15 +517,14 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t *buf, unsigned int num, "stp x12, x13, [%[dst], #96]\n" "stp x14, x15, [%[dst], #112]\n" : - : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr) + : [wdata] "r"(wdata), [dst] "r"(buf), [loc] "r"(addr) : "memory", "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", - "x15", "x16", "x17" - ); + "x15", "x16", "x17"); break; case 8: asm volatile( - ".cpu generic+lse\n" + ".arch_extension lse\n" "mov x16, %[wdata]\n" "mov x17, %[wdata]\n" "casp x0, x1, x16, x17, [%[loc]]\n" @@ -537,14 +536,13 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t *buf, unsigned int num, "stp x4, x5, [%[dst], #32]\n" "stp x6, x7, [%[dst], #48]\n" : - : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr) + : [wdata] "r"(wdata), [dst] "r"(buf), [loc] "r"(addr) : "memory", "x0", "x1", "x2", "x3", "x4", "x5", "x6", - "x7", "x16", "x17" - ); + "x7", "x16", "x17"); break; case 4: asm volatile( - ".cpu generic+lse\n" + ".arch_extension lse\n" "mov x16, %[wdata]\n" "mov x17, %[wdata]\n" "casp x0, x1, x16, x17, [%[loc]]\n" @@ -552,21 +550,19 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t *buf, unsigned int num, "stp x0, x1, [%[dst]]\n" "stp x2, x3, [%[dst], #16]\n" : - : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr) - : "memory", "x0", "x1", "x2", "x3", "x16", "x17" - ); + : [wdata] "r"(wdata), [dst] "r"(buf), [loc] "r"(addr) + : "memory", "x0", "x1", "x2", "x3", "x16", "x17"); break; case 2: asm volatile( - ".cpu generic+lse\n" + ".arch_extension lse\n" "mov x16, %[wdata]\n" "mov x17, %[wdata]\n" "casp x0, x1, x16, x17, [%[loc]]\n" "stp x0, x1, [%[dst]]\n" : - : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr) - : "memory", "x0", "x1", "x16", "x17" - ); + : [wdata] "r"(wdata), [dst] "r"(buf), [loc] "r"(addr) + : "memory", "x0", "x1", "x16", "x17"); break; case 1: buf[0] = roc_npa_aura_op_alloc(aura_handle, drop);