diff mbox series

[4/8] common/cnxk: reset stale values on error debug registers

Message ID 20211209091342.27017-4-ndabilpuram@marvell.com (mailing list archive)
State Changes Requested, archived
Delegated to: Jerin Jacob
Headers
Series [1/8] common/cnxk: fix shift offset for tl3 length disable |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram Dec. 9, 2021, 9:13 a.m. UTC 
  From: Harman Kalra <hkalra@marvell.com>

LF's error debug registers like NIX_LF_SQ_OP_ERR_DBG,
NIX_LF_MNQ_ERR_DBG, NIX_LF_SEND_ERR_DBG captures debug
info for an error detected during LMT operation or meta
enqueue or after meta enqueue granted respectively. HW
sets a valid bit when info is captured and SW is expected
to clear this valid bit by writing 1, else these registers
will show stale values of first interrupt when occurred and
will never update with subsequent interrupts.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
 drivers/common/cnxk/roc_nix_irq.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Jerin Jacob Jan. 19, 2022, 4:25 p.m. UTC | #1 
On Thu, Dec 9, 2021 at 2:44 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Harman Kalra <hkalra@marvell.com>
>
> LF's error debug registers like NIX_LF_SQ_OP_ERR_DBG,
> NIX_LF_MNQ_ERR_DBG, NIX_LF_SEND_ERR_DBG captures debug
> info for an error detected during LMT operation or meta
> enqueue or after meta enqueue granted respectively. HW
> sets a valid bit when info is captured and SW is expected
> to clear this valid bit by writing 1, else these registers
> will show stale values of first interrupt when occurred and
> will never update with subsequent interrupts.
>
> Signed-off-by: Harman Kalra <hkalra@marvell.com>

Acked-by: Jerin Jacob <jerinj@marvell.com>
Applied to dpdk-next-net-mrvl/for-next-net. Thanks

> ---
>  drivers/common/cnxk/roc_nix_irq.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c
> index a5cd9d4..7dcd533 100644
> --- a/drivers/common/cnxk/roc_nix_irq.c
> +++ b/drivers/common/cnxk/roc_nix_irq.c
> @@ -202,9 +202,12 @@ nix_lf_sq_debug_reg(struct nix *nix, uint32_t off)
>         uint64_t reg;
>
>         reg = plt_read64(nix->base + off);
> -       if (reg & BIT_ULL(44))
> +       if (reg & BIT_ULL(44)) {
>                 plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff),
>                         (uint8_t)(reg & 0xff));
> +               /* Clear valid bit */
> +               plt_write64(BIT_ULL(44), nix->base + off);
> +       }
>  }
>
>  static void
> --
> 2.8.4
>
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c
index a5cd9d4..7dcd533 100644
--- a/drivers/common/cnxk/roc_nix_irq.c
+++ b/drivers/common/cnxk/roc_nix_irq.c
@@ -202,9 +202,12 @@  nix_lf_sq_debug_reg(struct nix *nix, uint32_t off)
 	uint64_t reg;
 
 	reg = plt_read64(nix->base + off);
-	if (reg & BIT_ULL(44))
+	if (reg & BIT_ULL(44)) {
 		plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff),
 			(uint8_t)(reg & 0xff));
+		/* Clear valid bit */
+		plt_write64(BIT_ULL(44), nix->base + off);
+	}
 }
 
 static void