diff mbox series

config/cn10k: align mempool elements to 128 bytes

Message ID 20211213110615.4458-1-pbhagavatula@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series config/cn10k: align mempool elements to 128 bytes |

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Commit Message

Pavan Nikhilesh Bhagavatula Dec. 13, 2021, 11:06 a.m. UTC 
  From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Mempool elements are by default aligned to CACHELINE_SIZE.
In CN10K cacheline size is 64B but the RoC requires buffers to be
aligned to 128B.
Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
128 bytes.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Ruifeng Wang Dec. 14, 2021, 9:23 a.m. UTC | #1 
> -----Original Message-----
> From: pbhagavatula@marvell.com <pbhagavatula@marvell.com>
> Sent: Monday, December 13, 2021 7:06 PM
> To: jerinj@marvell.com; Jan Viktorin <viktorin@rehivetech.com>; Ruifeng
> Wang <Ruifeng.Wang@arm.com>; Bruce Richardson
> <bruce.richardson@intel.com>
> Cc: dev@dpdk.org; Pavan Nikhilesh <pbhagavatula@marvell.com>
> Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes
> 
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Mempool elements are by default aligned to CACHELINE_SIZE.
> In CN10K cacheline size is 64B but the RoC requires buffers to be aligned to
> 128B.
> Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
> 128 bytes.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/meson.build | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> 213324d262..33afe1a9ad 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -276,7 +276,8 @@ soc_cn10k = {
>      'implementer' : '0x41',
>      'flags': [
>          ['RTE_MAX_LCORE', 24],
> -        ['RTE_MAX_NUMA_NODES', 1]
> +        ['RTE_MAX_NUMA_NODES', 1],
> +        ['RTE_MEMPOOL_ALIGN', 128]
>      ],
>      'part_number': '0xd49',
>      'extra_march_features': ['crypto'],
> --
> 2.17.1

Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Kevin Traynor Dec. 14, 2021, 10:30 a.m. UTC | #2 
On 13/12/2021 11:06, pbhagavatula@marvell.com wrote:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Mempool elements are by default aligned to CACHELINE_SIZE.
> In CN10K cacheline size is 64B but the RoC requires buffers to be
> aligned to 128B.

It would be good to say what the implication is in the commit message.

> Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
> 128 bytes.
> 

Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K")

This is for backport? If so please add stable@ tag

> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>   config/arm/meson.build | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 213324d262..33afe1a9ad 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -276,7 +276,8 @@ soc_cn10k = {
>       'implementer' : '0x41',
>       'flags': [
>           ['RTE_MAX_LCORE', 24],
> -        ['RTE_MAX_NUMA_NODES', 1]
> +        ['RTE_MAX_NUMA_NODES', 1],
> +        ['RTE_MEMPOOL_ALIGN', 128]
>       ],
>       'part_number': '0xd49',
>       'extra_march_features': ['crypto'],
>
Jerin Jacob Jan. 20, 2022, 9:51 a.m. UTC | #3 
On Tue, Dec 14, 2021 at 2:53 PM Ruifeng Wang <Ruifeng.Wang@arm.com> wrote:
>
> > -----Original Message-----
> > From: pbhagavatula@marvell.com <pbhagavatula@marvell.com>
> > Sent: Monday, December 13, 2021 7:06 PM
> > To: jerinj@marvell.com; Jan Viktorin <viktorin@rehivetech.com>; Ruifeng
> > Wang <Ruifeng.Wang@arm.com>; Bruce Richardson
> > <bruce.richardson@intel.com>
> > Cc: dev@dpdk.org; Pavan Nikhilesh <pbhagavatula@marvell.com>
> > Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes
> >
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> >
> > Mempool elements are by default aligned to CACHELINE_SIZE.
> > In CN10K cacheline size is 64B but the RoC requires buffers to be aligned to
> > 128B.
> > Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
> > 128 bytes.
> >
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > ---
> >  config/arm/meson.build | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > 213324d262..33afe1a9ad 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -276,7 +276,8 @@ soc_cn10k = {
> >      'implementer' : '0x41',
> >      'flags': [
> >          ['RTE_MAX_LCORE', 24],
> > -        ['RTE_MAX_NUMA_NODES', 1]
> > +        ['RTE_MAX_NUMA_NODES', 1],
> > +        ['RTE_MEMPOOL_ALIGN', 128]
> >      ],
> >      'part_number': '0xd49',
> >      'extra_march_features': ['crypto'],
> > --
> > 2.17.1
>
> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>

Applied to dpdk-next-net-mrvl/for-next-net. Thanks


Added
    Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K")
    Cc: stable@dpdk.org
>
Jerin Jacob Jan. 21, 2022, 9:37 a.m. UTC | #4 
On Thu, Jan 20, 2022 at 3:21 PM Jerin Jacob <jerinjacobk@gmail.com> wrote:
>
> On Tue, Dec 14, 2021 at 2:53 PM Ruifeng Wang <Ruifeng.Wang@arm.com> wrote:
> >
> > > -----Original Message-----
> > > From: pbhagavatula@marvell.com <pbhagavatula@marvell.com>
> > > Sent: Monday, December 13, 2021 7:06 PM
> > > To: jerinj@marvell.com; Jan Viktorin <viktorin@rehivetech.com>; Ruifeng
> > > Wang <Ruifeng.Wang@arm.com>; Bruce Richardson
> > > <bruce.richardson@intel.com>
> > > Cc: dev@dpdk.org; Pavan Nikhilesh <pbhagavatula@marvell.com>
> > > Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes
> > >
> > > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > >
> > > Mempool elements are by default aligned to CACHELINE_SIZE.
> > > In CN10K cacheline size is 64B but the RoC requires buffers to be aligned to
> > > 128B.
> > > Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
> > > 128 bytes.
> > >
> > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > > ---
> > >  config/arm/meson.build | 3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > > 213324d262..33afe1a9ad 100644
> > > --- a/config/arm/meson.build
> > > +++ b/config/arm/meson.build
> > > @@ -276,7 +276,8 @@ soc_cn10k = {
> > >      'implementer' : '0x41',
> > >      'flags': [
> > >          ['RTE_MAX_LCORE', 24],
> > > -        ['RTE_MAX_NUMA_NODES', 1]
> > > +        ['RTE_MAX_NUMA_NODES', 1],
> > > +        ['RTE_MEMPOOL_ALIGN', 128]
> > >      ],
> > >      'part_number': '0xd49',
> > >      'extra_march_features': ['crypto'],
> > > --
> > > 2.17.1
> >
> > Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
>
> Applied to dpdk-next-net-mrvl/for-next-net. Thanks

As per @Ferruh Yigit  suggestion, This patch will be taken through the
main tree.
I changed state as New and Delegate as @Thomas Monjalon for this patch in pw.

>
>
> Added
>     Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K")
>     Cc: stable@dpdk.org
> >
Thomas Monjalon Feb. 12, 2022, 2:14 p.m. UTC | #5 
21/01/2022 10:37, Jerin Jacob:
> On Thu, Jan 20, 2022 at 3:21 PM Jerin Jacob <jerinjacobk@gmail.com> wrote:
> >
> > On Tue, Dec 14, 2021 at 2:53 PM Ruifeng Wang <Ruifeng.Wang@arm.com> wrote:
> > >
> > > > -----Original Message-----
> > > > From: pbhagavatula@marvell.com <pbhagavatula@marvell.com>
> > > > Sent: Monday, December 13, 2021 7:06 PM
> > > > To: jerinj@marvell.com; Jan Viktorin <viktorin@rehivetech.com>; Ruifeng
> > > > Wang <Ruifeng.Wang@arm.com>; Bruce Richardson
> > > > <bruce.richardson@intel.com>
> > > > Cc: dev@dpdk.org; Pavan Nikhilesh <pbhagavatula@marvell.com>
> > > > Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes
> > > >
> > > > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > > >
> > > > Mempool elements are by default aligned to CACHELINE_SIZE.
> > > > In CN10K cacheline size is 64B but the RoC requires buffers to be aligned to
> > > > 128B.
> > > > Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
> > > > 128 bytes.
> > > >
> > > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > > > ---
> > > >  config/arm/meson.build | 3 ++-
> > > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > > > 213324d262..33afe1a9ad 100644
> > > > --- a/config/arm/meson.build
> > > > +++ b/config/arm/meson.build
> > > > @@ -276,7 +276,8 @@ soc_cn10k = {
> > > >      'implementer' : '0x41',
> > > >      'flags': [
> > > >          ['RTE_MAX_LCORE', 24],
> > > > -        ['RTE_MAX_NUMA_NODES', 1]
> > > > +        ['RTE_MAX_NUMA_NODES', 1],
> > > > +        ['RTE_MEMPOOL_ALIGN', 128]
> > > >      ],
> > > >      'part_number': '0xd49',
> > > >      'extra_march_features': ['crypto'],
> > > > --
> > > > 2.17.1
> > >
> > > Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
> >
> > Applied to dpdk-next-net-mrvl/for-next-net. Thanks
> 
> As per @Ferruh Yigit  suggestion, This patch will be taken through the
> main tree.
> I changed state as New and Delegate as @Thomas Monjalon for this patch in pw.
> 
> >
> >
> > Added
> >     Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K")
> >     Cc: stable@dpdk.org

Applied
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 213324d262..33afe1a9ad 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -276,7 +276,8 @@  soc_cn10k = {
     'implementer' : '0x41',
     'flags': [
         ['RTE_MAX_LCORE', 24],
-        ['RTE_MAX_NUMA_NODES', 1]
+        ['RTE_MAX_NUMA_NODES', 1],
+        ['RTE_MEMPOOL_ALIGN', 128]
     ],
     'part_number': '0xd49',
     'extra_march_features': ['crypto'],