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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.235) by BN8NAM11FT068.mail.protection.outlook.com (10.13.177.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4844.14 via Frontend Transport; Thu, 30 Dec 2021 03:08:42 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Dec 2021 03:08:41 +0000 Received: from nvidia.com (172.20.187.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Wed, 29 Dec 2021 19:08:40 -0800 From: Sean Zhang To: , , Viacheslav Ovsiienko CC: , Subject: [RFC 3/3] net/mlx5: support matching on optional fields of GRE Date: Thu, 30 Dec 2021 05:08:17 +0200 Message-ID: <20211230030817.15264-4-xiazhang@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211230030817.15264-1-xiazhang@nvidia.com> References: <20211230030817.15264-1-xiazhang@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e744b79a-1927-4d7e-825e-08d9cb41af80 X-MS-TrafficTypeDiagnostic: DM6PR12MB2634:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(36840700001)(40470700002)(46966006)(426003)(82310400004)(110136005)(336012)(1076003)(83380400001)(36860700001)(186003)(54906003)(356005)(2616005)(16526019)(30864003)(26005)(7696005)(508600001)(316002)(36756003)(5660300002)(55016003)(2906002)(8936002)(6666004)(6636002)(40460700001)(47076005)(70586007)(8676002)(70206006)(6286002)(4326008)(81166007)(86362001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2021 03:08:42.5664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e744b79a-1927-4d7e-825e-08d9cb41af80 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2634 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds matching on the optional fields (checksum/key/sequence) of GRE header. The matching of checksum and sequence fields requests support from rdma-core with capability of misc5 and tunner_header 0-3. For patterns without checksum and sequence specified, keep using misc for matching as before, but for patterns with checksum or sequence, validate capability first and then use misc5 for the matching. Signed-off-by: Sean Zhang --- drivers/common/mlx5/mlx5_devx_cmds.c | 3 + drivers/net/mlx5/linux/mlx5_os.c | 2 + drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_flow.c | 94 +++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 6 ++ drivers/net/mlx5/mlx5_flow_dv.c | 133 +++++++++++++++++++++++++++++++++++ 6 files changed, 239 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index e52b995..3accb7b 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1027,6 +1027,9 @@ struct mlx5_devx_obj * attr->flow.tunnel_header_0_1 = MLX5_GET (flow_table_nic_cap, hcattr, ft_field_support_2_nic_receive.tunnel_header_0_1); + attr->flow.tunnel_header_2_3 = MLX5_GET + (flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.tunnel_header_2_3); attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); attr->inner_ipv4_ihl = MLX5_GET (flow_table_nic_cap, hcattr, diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index c29fe3d..3bfcb5c 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1385,6 +1385,8 @@ } if (config->hca_attr.flow.tunnel_header_0_1) sh->tunnel_header_0_1 = 1; + if (config->hca_attr.flow.tunnel_header_2_3) + sh->tunnel_header_2_3 = 1; #endif #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO if (config->hca_attr.flow_hit_aso && diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 8466531..9b5685a 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1150,6 +1150,7 @@ struct mlx5_dev_ctx_shared { uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ + uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */ uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ uint32_t reclaim_mode:1; /* Reclaim memory. */ uint32_t dr_drop_action_en:1; /* Use DR drop action. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index f34e4b8..ad948c3 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -2802,6 +2802,100 @@ struct mlx5_flow_tunnel_info { } /** + * Validate GRE optional item. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] item + * Item specification. + * @param[in] item_flags + * Bit flags to mark detected items. + * @param[in] attr + * Flow rule attributes. + * @param[in] gre_item + * Pointer to gre_item + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + uint64_t item_flags, + const struct rte_flow_attr *attr, + const struct rte_flow_item *gre_item, + struct rte_flow_error *error) +{ + const struct rte_flow_item_gre *gre_spec = gre_item->spec; + const struct rte_flow_item_gre *gre_mask = gre_item->mask; + const struct rte_gre_hdr_option *spec = item->spec; + const struct rte_gre_hdr_option *mask = item->mask; + struct mlx5_priv *priv = dev->data->dev_private; + int ret = 0; + + if (!(item_flags & MLX5_FLOW_LAYER_GRE)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "No preceding GRE header"); + if (item_flags & MLX5_FLOW_LAYER_INNER) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "GRE option following a wrong item"); + if (!gre_mask) + gre_mask = &rte_flow_item_gre_mask; + + struct rte_gre_hdr_option gre_option_default_mask = { + .checksum = 0xffff, + .key = 0xffffffff, + .sequence = 0xffffffff, + }; + + if (!mask) + mask = &gre_option_default_mask; + + if (spec && mask->checksum) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "Checksum bit must be on"); + + if (spec && mask->key) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "Key bit must be on"); + + if (spec && mask->sequence) + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "Sequence bit must be on"); + + if (spec && (mask->checksum || mask->sequence)) { + if (priv->sh->steering_format_version == + MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || + ((attr->group || attr->transfer) && !priv->sh->misc5_cap) || + (!(priv->sh->tunnel_header_0_1 && priv->sh->tunnel_header_2_3) && + !attr->group && !attr->transfer)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, item, + "Checksum/Sequence not supported"); + } + + ret = mlx5_flow_item_acceptable + (item, (const uint8_t *)mask, + (const uint8_t *)&gre_option_default_mask, + sizeof(struct rte_gre_hdr_option), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); + + return ret; +} + +/** * Validate GRE item. * * @param[in] item diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 1f54649..59857ec 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1523,6 +1523,12 @@ int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, uint64_t item_flags, const struct rte_flow_item *gre_item, struct rte_flow_error *error); +int mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + uint64_t item_flags, + const struct rte_flow_attr *attr, + const struct rte_flow_item *gre_item, + struct rte_flow_error *error); int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, uint64_t item_flags, uint64_t last_item, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 3da122c..28462f8 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7112,6 +7112,13 @@ struct mlx5_list_entry * gre_item = items; last_item = MLX5_FLOW_LAYER_GRE; break; + case RTE_FLOW_ITEM_TYPE_GRE_OPTION: + ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags, + attr, gre_item, error); + if (ret < 0) + return ret; + last_item = MLX5_FLOW_LAYER_GRE; + break; case RTE_FLOW_ITEM_TYPE_NVGRE: ret = mlx5_flow_validate_item_nvgre(items, item_flags, next_protocol, @@ -8833,6 +8840,122 @@ struct mlx5_list_entry * } /** + * Add GRE optional items to matcher and to the value. + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] item + * Flow pattern to translate. + * @param[in] gre_item + * Pointer to gre_item. + * @param[in] pattern_flags + * Accumulated pattern flags. + */ +static void +flow_dv_translate_item_gre_option(void *matcher, void *key, + const struct rte_flow_item *item, + const struct rte_flow_item *gre_item, + uint64_t pattern_flags) +{ + void *misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5); + void *misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5); + const struct rte_gre_hdr_option *option_m = item->mask; + const struct rte_gre_hdr_option *option_v = item->spec; + const struct rte_flow_item_gre *gre_m = gre_item->mask; + const struct rte_flow_item_gre *gre_v = gre_item->spec; + static const struct rte_flow_item_gre empty_gre = {0}; + struct rte_flow_item gre_key_item; + uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v; + uint16_t protocol_m, protocol_v; + uint32_t *tunnel_header_v[4]; + uint32_t *tunnel_header_m[4]; + + struct rte_gre_hdr_option gre_option_default_mask = { + .checksum = 0xffff, + .key = 0xffffffff, + .sequence = 0xffffffff, + }; + + if (!option_v) + return; + if (!option_m) + option_m = &gre_option_default_mask; + + if (!(option_m->sequence || option_m->checksum)) { + flow_dv_translate_item_gre(matcher, key, gre_item, pattern_flags); + gre_key_item.spec = &option_v->key; + gre_key_item.mask = &option_m->key; + flow_dv_translate_item_gre_key(matcher, key, &gre_key_item); + return; + } + + if (!gre_v) { + gre_v = &empty_gre; + gre_m = &empty_gre; + } else { + if (!gre_m) + gre_m = &rte_flow_item_gre_mask; + } + + tunnel_header_v[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_v, tunnel_header_0); + tunnel_header_m[0] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_m, tunnel_header_0); + tunnel_header_v[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_v, tunnel_header_1); + tunnel_header_m[1] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_m, tunnel_header_1); + tunnel_header_v[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_v, tunnel_header_2); + tunnel_header_m[2] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_m, tunnel_header_2); + tunnel_header_v[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_v, tunnel_header_3); + tunnel_header_m[3] = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, + misc5_m, tunnel_header_3); + + protocol_v = gre_v->protocol; + protocol_m = gre_m->protocol; + if (!protocol_m) { + /* Force next protocol to prevent matchers duplication */ + uint16_t ether_type = mlx5_translate_tunnel_etypes(pattern_flags); + if (ether_type) { + protocol_v = rte_be_to_cpu_16(ether_type); + protocol_m = 0xFFFF; + } + } + c_rsvd0_ver_v = gre_v->c_rsvd0_ver; + c_rsvd0_ver_m = gre_m->c_rsvd0_ver; + + + if (option_m->sequence) { + c_rsvd0_ver_v |= RTE_BE16(0x1000); + c_rsvd0_ver_m |= RTE_BE16(0x1000); + } + + if (option_m->key) { + c_rsvd0_ver_v |= RTE_BE16(0x2000); + c_rsvd0_ver_m |= RTE_BE16(0x2000); + } + + if (option_m->checksum) { + c_rsvd0_ver_v |= RTE_BE16(0x8000); + c_rsvd0_ver_m |= RTE_BE16(0x8000); + } + + *tunnel_header_v[0] = c_rsvd0_ver_v | protocol_v << 16; + *tunnel_header_m[0] = c_rsvd0_ver_m | protocol_m << 16; + *tunnel_header_v[1] = option_v->checksum; + *tunnel_header_m[1] = option_m->checksum; + *tunnel_header_v[2] = option_v->key; + *tunnel_header_m[2] = option_m->key; + *tunnel_header_v[3] = option_v->sequence; + *tunnel_header_m[3] = option_m->sequence; +} + +/** * Add NVGRE item to matcher and to the value. * * @param[in, out] matcher @@ -12708,6 +12831,7 @@ struct mlx5_list_entry * }; const struct rte_flow_item *integrity_items[2] = {NULL, NULL}; const struct rte_flow_item *tunnel_item = NULL; + const struct rte_flow_item *gre_item = NULL; if (!wks) return rte_flow_error_set(error, ENOMEM, @@ -13480,12 +13604,18 @@ struct mlx5_list_entry * matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GRE; tunnel_item = items; + gre_item = items; break; case RTE_FLOW_ITEM_TYPE_GRE_KEY: flow_dv_translate_item_gre_key(match_mask, match_value, items); last_item = MLX5_FLOW_LAYER_GRE_KEY; break; + case RTE_FLOW_ITEM_TYPE_GRE_OPTION: + matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); + last_item = MLX5_FLOW_LAYER_GRE; + tunnel_item = items; + break; case RTE_FLOW_ITEM_TYPE_NVGRE: matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GRE; @@ -13645,6 +13775,9 @@ struct mlx5_list_entry * else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE) flow_dv_translate_item_nvgre(match_mask, match_value, tunnel_item, item_flags); + else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION) + flow_dv_translate_item_gre_option(match_mask, match_value, + tunnel_item, gre_item, item_flags); else MLX5_ASSERT(false); }