@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright 2016,2018-2021 NXP
+ * Copyright 2016,2018-2022 NXP
*
*/
@@ -493,6 +493,18 @@ rte_fslmc_probe(void)
return 0;
}
+static int
+rte_fslmc_close(void)
+{
+ int ret = 0;
+
+ ret = fslmc_vfio_close_group();
+ if (ret)
+ DPAA2_BUS_ERR("Unable to close devices %d", ret);
+
+ return 0;
+}
+
static struct rte_device *
rte_fslmc_find_device(const struct rte_device *start, rte_dev_cmp_t cmp,
const void *data)
@@ -668,6 +680,7 @@ struct rte_fslmc_bus rte_fslmc_bus = {
.bus = {
.scan = rte_fslmc_scan,
.probe = rte_fslmc_probe,
+ .close = rte_fslmc_close,
.parse = rte_fslmc_parse,
.find_device = rte_fslmc_find_device,
.get_iommu_class = rte_dpaa2_get_iommu_class,
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
*
*/
@@ -1066,3 +1066,90 @@ fslmc_vfio_setup_group(void)
return 0;
}
+
+static void
+fslmc_close_iodevices(struct rte_dpaa2_device *dev)
+{
+ struct rte_dpaa2_object *object = NULL;
+ struct rte_dpaa2_driver *drv;
+ int ret, probe_all;
+
+ switch (dev->dev_type) {
+ case DPAA2_IO:
+ case DPAA2_CON:
+ case DPAA2_CI:
+ case DPAA2_BPOOL:
+ case DPAA2_MUX:
+ TAILQ_FOREACH(object, &dpaa2_obj_list, next) {
+ if (dev->dev_type == object->dev_type)
+ object->close(dev->object_id);
+ else
+ continue;
+ }
+ break;
+ case DPAA2_ETH:
+ case DPAA2_CRYPTO:
+ case DPAA2_QDMA:
+ probe_all = rte_fslmc_bus.bus.conf.scan_mode !=
+ RTE_BUS_SCAN_ALLOWLIST;
+ TAILQ_FOREACH(drv, &rte_fslmc_bus.driver_list, next) {
+ if (drv->drv_type != dev->dev_type)
+ continue;
+ if (rte_dev_is_probed(&dev->device))
+ continue;
+ if (probe_all ||
+ (dev->device.devargs &&
+ dev->device.devargs->policy ==
+ RTE_DEV_ALLOWED)) {
+ ret = drv->remove(dev);
+ if (ret)
+ DPAA2_BUS_ERR("Unable to remove");
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ DPAA2_BUS_LOG(DEBUG, "Device (%s) Closed",
+ dev->device.name);
+}
+
+int
+fslmc_vfio_close_group(void)
+{
+ struct rte_dpaa2_device *dev, *dev_temp;
+
+ RTE_TAILQ_FOREACH_SAFE(dev, &rte_fslmc_bus.device_list, next, dev_temp) {
+ if (dev->device.devargs &&
+ dev->device.devargs->policy == RTE_DEV_BLOCKED) {
+ DPAA2_BUS_LOG(DEBUG, "%s Blacklisted, skipping",
+ dev->device.name);
+ TAILQ_REMOVE(&rte_fslmc_bus.device_list, dev, next);
+ continue;
+ }
+ switch (dev->dev_type) {
+ case DPAA2_ETH:
+ case DPAA2_CRYPTO:
+ case DPAA2_QDMA:
+ case DPAA2_IO:
+ fslmc_close_iodevices(dev);
+ break;
+ case DPAA2_CON:
+ case DPAA2_CI:
+ case DPAA2_BPOOL:
+ case DPAA2_MUX:
+ if (rte_eal_process_type() == RTE_PROC_SECONDARY)
+ continue;
+
+ fslmc_close_iodevices(dev);
+ break;
+ case DPAA2_DPRTC:
+ default:
+ DPAA2_BUS_DEBUG("Device cannot be closed: Not supported (%s)",
+ dev->device.name);
+ }
+ }
+
+ return 0;
+}
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016,2019 NXP
+ * Copyright 2016,2019,2021-2022 NXP
*
*/
@@ -55,6 +55,7 @@ int rte_dpaa2_vfio_setup_intr(struct rte_intr_handle *intr_handle,
int fslmc_vfio_setup_group(void);
int fslmc_vfio_process_group(void);
+int fslmc_vfio_close_group(void);
char *fslmc_get_container(void);
int fslmc_get_container_group(int *gropuid);
int rte_fslmc_vfio_dmamap(void);
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
*
* Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2019,2021-2022 NXP
*
*/
#ifndef __FSL_DPCON_H
@@ -26,6 +26,7 @@ int dpcon_open(struct fsl_mc_io *mc_io,
int dpcon_id,
uint16_t *token);
+__rte_internal
int dpcon_close(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token);
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016 NXP
+ * Copyright 2016,2021-2022 NXP
*
*/
@@ -33,6 +33,19 @@ TAILQ_HEAD(dpbp_dev_list, dpaa2_dpbp_dev);
static struct dpbp_dev_list dpbp_dev_list
= TAILQ_HEAD_INITIALIZER(dpbp_dev_list); /*!< DPBP device list */
+static struct dpaa2_dpbp_dev *get_dpbp_from_id(uint32_t dpbp_id)
+{
+ struct dpaa2_dpbp_dev *dpbp_dev = NULL;
+
+ /* Get DPBP dev handle from list using index */
+ TAILQ_FOREACH(dpbp_dev, &dpbp_dev_list, next) {
+ if (dpbp_dev->dpbp_id == dpbp_id)
+ break;
+ }
+
+ return dpbp_dev;
+}
+
static int
dpaa2_create_dpbp_device(int vdev_fd __rte_unused,
struct vfio_device_info *obj_info __rte_unused,
@@ -109,6 +122,20 @@ void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp)
}
}
+static void dpaa2_close_dpbp_device(int object_id)
+{
+ struct dpaa2_dpbp_dev *dpbp_dev = NULL;
+
+ dpbp_dev = get_dpbp_from_id((uint32_t)object_id);
+
+ if (dpbp_dev) {
+ dpaa2_free_dpbp_dev(dpbp_dev);
+ dpbp_close(&dpbp_dev->dpbp, CMD_PRI_LOW, dpbp_dev->token);
+ TAILQ_REMOVE(&dpbp_dev_list, dpbp_dev, next);
+ rte_free(dpbp_dev);
+ }
+}
+
int dpaa2_dpbp_supported(void)
{
if (TAILQ_EMPTY(&dpbp_dev_list))
@@ -119,6 +146,7 @@ int dpaa2_dpbp_supported(void)
static struct rte_dpaa2_object rte_dpaa2_dpbp_obj = {
.dev_type = DPAA2_BPOOL,
.create = dpaa2_create_dpbp_device,
+ .close = dpaa2_close_dpbp_device,
};
RTE_PMD_REGISTER_DPAA2_OBJECT(dpbp, rte_dpaa2_dpbp_obj);
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright 2017 NXP
+ * Copyright 2017,2021-2022 NXP
*
*/
@@ -30,6 +30,19 @@ TAILQ_HEAD(dpci_dev_list, dpaa2_dpci_dev);
static struct dpci_dev_list dpci_dev_list
= TAILQ_HEAD_INITIALIZER(dpci_dev_list); /*!< DPCI device list */
+static struct dpaa2_dpci_dev *get_dpci_from_id(uint32_t dpci_id)
+{
+ struct dpaa2_dpci_dev *dpci_dev = NULL;
+
+ /* Get DPCI dev handle from list using index */
+ TAILQ_FOREACH(dpci_dev, &dpci_dev_list, next) {
+ if (dpci_dev->dpci_id == dpci_id)
+ break;
+ }
+
+ return dpci_dev;
+}
+
static int
rte_dpaa2_create_dpci_device(int vdev_fd __rte_unused,
struct vfio_device_info *obj_info __rte_unused,
@@ -179,9 +192,24 @@ void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci)
}
}
+static void rte_dpaa2_close_dpci_device(int object_id)
+{
+ struct dpaa2_dpci_dev *dpci_dev = NULL;
+
+ dpci_dev = get_dpci_from_id((uint32_t)object_id);
+
+ if (dpci_dev) {
+ rte_dpaa2_free_dpci_dev(dpci_dev);
+ dpci_close(&dpci_dev->dpci, CMD_PRI_LOW, dpci_dev->token);
+ TAILQ_REMOVE(&dpci_dev_list, dpci_dev, next);
+ rte_free(dpci_dev);
+ }
+}
+
static struct rte_dpaa2_object rte_dpaa2_dpci_obj = {
.dev_type = DPAA2_CI,
.create = rte_dpaa2_create_dpci_device,
+ .close = rte_dpaa2_close_dpci_device,
};
RTE_PMD_REGISTER_DPAA2_OBJECT(dpci, rte_dpaa2_dpci_obj);
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2019,2021-2022 NXP
*
*/
#include <unistd.h>
@@ -86,6 +86,19 @@ static int dpaa2_cluster_sz = 2;
* Cluster 4 (ID = x07) : CPU14, CPU15;
*/
+static struct dpaa2_dpio_dev *get_dpio_dev_from_id(int32_t dpio_id)
+{
+ struct dpaa2_dpio_dev *dpio_dev = NULL;
+
+ /* Get DPIO dev handle from list using index */
+ TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
+ if (dpio_dev->hw_id == dpio_id)
+ break;
+ }
+
+ return dpio_dev;
+}
+
static int
dpaa2_get_core_id(void)
{
@@ -634,9 +647,30 @@ dpaa2_free_eq_descriptors(void)
MAX_EQ_RESP_ENTRIES - 1;
}
+static void
+dpaa2_close_dpio_device(int object_id)
+{
+ struct dpaa2_dpio_dev *dpio_dev = NULL;
+
+ dpio_dev = get_dpio_dev_from_id((int32_t)object_id);
+
+ if (dpio_dev) {
+ if (dpio_dev->dpio) {
+ dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
+ dpio_dev->token);
+ dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
+ dpio_dev->token);
+ rte_free(dpio_dev->dpio);
+ }
+ TAILQ_REMOVE(&dpio_dev_list, dpio_dev, next);
+ rte_free(dpio_dev);
+ }
+}
+
static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
.dev_type = DPAA2_IO,
.create = dpaa2_create_dpio_device,
+ .close = dpaa2_close_dpio_device,
};
RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright 2021 NXP
+ * Copyright 2021-2022 NXP
*
*/
@@ -92,9 +92,38 @@ rte_dpaa2_create_dprc_device(int vdev_fd __rte_unused,
return 0;
}
+static struct dpaa2_dprc_dev *
+get_dprc_from_id(uint32_t dprc_id)
+{
+ struct dpaa2_dprc_dev *dprc_dev = NULL;
+
+ /* Get DPRC dev handle from list using index */
+ TAILQ_FOREACH(dprc_dev, &dprc_dev_list, next) {
+ if (dprc_dev->dprc_id == dprc_id)
+ break;
+ }
+
+ return dprc_dev;
+}
+
+static void
+rte_dpaa2_close_dprc_device(int object_id)
+{
+ struct dpaa2_dprc_dev *dprc_dev = NULL;
+
+ dprc_dev = get_dprc_from_id((uint32_t)object_id);
+
+ if (dprc_dev) {
+ dprc_close(&dprc_dev->dprc, CMD_PRI_LOW, dprc_dev->token);
+ TAILQ_REMOVE(&dprc_dev_list, dprc_dev, next);
+ rte_free(dprc_dev);
+ }
+}
+
static struct rte_dpaa2_object rte_dpaa2_dprc_obj = {
.dev_type = DPAA2_DPRC,
.create = rte_dpaa2_create_dprc_device,
+ .close = rte_dpaa2_close_dprc_device,
};
RTE_PMD_REGISTER_DPAA2_OBJECT(dprc, rte_dpaa2_dprc_obj);
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright 2016,2021 NXP
+ * Copyright 2016,2021-2022 NXP
*
*/
@@ -104,6 +104,8 @@ typedef int (*rte_dpaa2_obj_create_t)(int vdev_fd,
struct vfio_device_info *obj_info,
int object_id);
+typedef void (*rte_dpaa2_obj_close_t)(int object_id);
+
/**
* A structure describing a DPAA2 object.
*/
@@ -112,6 +114,7 @@ struct rte_dpaa2_object {
const char *name; /**< Name of Object. */
enum rte_dpaa2_dev_type dev_type; /**< Type of device */
rte_dpaa2_obj_create_t create;
+ rte_dpaa2_obj_close_t close;
};
/**
@@ -34,6 +34,7 @@ INTERNAL {
dpci_get_opr;
dpci_set_opr;
dpci_set_rx_queue;
+ dpcon_close;
dpcon_get_attributes;
dpcon_open;
dpdmai_close;
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright 2017 NXP
+ * Copyright 2017,2022 NXP
*
*/
@@ -30,6 +30,19 @@ TAILQ_HEAD(dpcon_dev_list, dpaa2_dpcon_dev);
static struct dpcon_dev_list dpcon_dev_list
= TAILQ_HEAD_INITIALIZER(dpcon_dev_list); /*!< DPCON device list */
+static struct dpaa2_dpcon_dev *get_dpcon_from_id(uint32_t dpcon_id)
+{
+ struct dpaa2_dpcon_dev *dpcon_dev = NULL;
+
+ /* Get DPCONC dev handle from list using index */
+ TAILQ_FOREACH(dpcon_dev, &dpcon_dev_list, next) {
+ if (dpcon_dev->dpcon_id == dpcon_id)
+ break;
+ }
+
+ return dpcon_dev;
+}
+
static int
rte_dpaa2_create_dpcon_device(int dev_fd __rte_unused,
struct vfio_device_info *obj_info __rte_unused,
@@ -105,9 +118,25 @@ void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon)
}
}
+static void
+rte_dpaa2_close_dpcon_device(int object_id)
+{
+ struct dpaa2_dpcon_dev *dpcon_dev = NULL;
+
+ dpcon_dev = get_dpcon_from_id((uint32_t)object_id);
+
+ if (dpcon_dev) {
+ rte_dpaa2_free_dpcon_dev(dpcon_dev);
+ dpcon_close(&dpcon_dev->dpcon, CMD_PRI_LOW, dpcon_dev->token);
+ TAILQ_REMOVE(&dpcon_dev_list, dpcon_dev, next);
+ rte_free(dpcon_dev);
+ }
+}
+
static struct rte_dpaa2_object rte_dpaa2_dpcon_obj = {
.dev_type = DPAA2_CON,
.create = rte_dpaa2_create_dpcon_device,
+ .close = rte_dpaa2_close_dpcon_device,
};
RTE_PMD_REGISTER_DPAA2_OBJECT(dpcon, rte_dpaa2_dpcon_obj);
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright 2018-2021 NXP
+ * Copyright 2018-2022 NXP
*/
#include <sys/queue.h>
@@ -44,7 +44,7 @@ static struct dpaa2_dpdmux_dev *get_dpdmux_from_id(uint32_t dpdmux_id)
{
struct dpaa2_dpdmux_dev *dpdmux_dev = NULL;
- /* Get DPBP dev handle from list using index */
+ /* Get DPDMUX dev handle from list using index */
TAILQ_FOREACH(dpdmux_dev, &dpdmux_dev_list, next) {
if (dpdmux_dev->dpdmux_id == dpdmux_id)
break;
@@ -359,9 +359,25 @@ dpaa2_create_dpdmux_device(int vdev_fd __rte_unused,
return -1;
}
+static void
+dpaa2_close_dpdmux_device(int object_id)
+{
+ struct dpaa2_dpdmux_dev *dpdmux_dev;
+
+ dpdmux_dev = get_dpdmux_from_id((uint32_t)object_id);
+
+ if (dpdmux_dev) {
+ dpdmux_close(&dpdmux_dev->dpdmux, CMD_PRI_LOW,
+ dpdmux_dev->token);
+ TAILQ_REMOVE(&dpdmux_dev_list, dpdmux_dev, next);
+ rte_free(dpdmux_dev);
+ }
+}
+
static struct rte_dpaa2_object rte_dpaa2_dpdmux_obj = {
.dev_type = DPAA2_MUX,
.create = dpaa2_create_dpdmux_device,
+ .close = dpaa2_close_dpdmux_device,
};
RTE_PMD_REGISTER_DPAA2_OBJECT(dpdmux, rte_dpaa2_dpdmux_obj);