diff mbox series

[v1,6/6] net/axgbe: alter the port speed bit range

Message ID 20220110113509.553184-7-ssebasti@amd.com (mailing list archive)
State Changes Requested, archived
Delegated to: Ferruh Yigit
Headers
Series [v1,1/6] net/axgbe: always attempt link training in KR mode |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/github-robot: build fail github build: failed
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-aarch64-unit-testing fail Testing issues
ci/iol-abi-testing warning Testing issues
ci/iol-x86_64-unit-testing fail Testing issues
ci/iol-aarch64-compile-testing fail Testing issues

Commit Message

Selwin Sebastian Jan. 10, 2022, 11:35 a.m. UTC 
  From: Selwin Sebastian <selwin.sebastian@amd.com>

Newer generation Hardware uses the slightly different
port speed bit widths, so alter the existing port speed
bit range to extend support to the newer generation hardware
while maintaining the backward compatibility with older
generation hardware.

The previously reserved bits are now being used which
then requires the adjustment to the BIT values, e.g.:

Before:
   PORT_PROPERTY_0[22:21] - Reserved
   PORT_PROPERTY_0[26:23] - Supported Speeds

After:
   PORT_PROPERTY_0[21] - Reserved
   PORT_PROPERTY_0[26:22] - Supported Speeds

To make this backwards compatible, the existing BIT
definitions for the port speeds are incremented by one
to maintain the original position.

Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
 drivers/net/axgbe/axgbe_common.h   | 4 ++--
 drivers/net/axgbe/axgbe_phy_impl.c | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

Comments

Namburu, Chandu-babu Jan. 24, 2022, 4:40 p.m. UTC | #1 
[Public]

Acked-by: Chandubabu Namburu <chandu@amd.com>

-----Original Message-----
From: ssebasti@amd.com <ssebasti@amd.com> 
Sent: Monday, January 10, 2022 5:05 PM
To: dev@dpdk.org
Subject: [PATCH v1 6/6] net/axgbe: alter the port speed bit range

From: Selwin Sebastian <selwin.sebastian@amd.com>

Newer generation Hardware uses the slightly different port speed bit widths, so alter the existing port speed bit range to extend support to the newer generation hardware while maintaining the backward compatibility with older generation hardware.

The previously reserved bits are now being used which then requires the adjustment to the BIT values, e.g.:

Before:
   PORT_PROPERTY_0[22:21] - Reserved
   PORT_PROPERTY_0[26:23] - Supported Speeds

After:
   PORT_PROPERTY_0[21] - Reserved
   PORT_PROPERTY_0[26:22] - Supported Speeds

To make this backwards compatible, the existing BIT definitions for the port speeds are incremented by one to maintain the original position.

Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
 drivers/net/axgbe/axgbe_common.h   | 4 ++--
 drivers/net/axgbe/axgbe_phy_impl.c | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index a5431dd998..5310ac54f5 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1032,8 +1032,8 @@
 #define XP_PROP_0_PORT_ID_WIDTH			8
 #define XP_PROP_0_PORT_MODE_INDEX		8
 #define XP_PROP_0_PORT_MODE_WIDTH		4
-#define XP_PROP_0_PORT_SPEEDS_INDEX		23
-#define XP_PROP_0_PORT_SPEEDS_WIDTH		4
+#define XP_PROP_0_PORT_SPEEDS_INDEX		22
+#define XP_PROP_0_PORT_SPEEDS_WIDTH		5
 #define XP_PROP_1_MAX_RX_DMA_INDEX		24
 #define XP_PROP_1_MAX_RX_DMA_WIDTH		5
 #define XP_PROP_1_MAX_RX_QUEUES_INDEX		8
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 2aad8babd2..776144696a 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -7,10 +7,10 @@
 #include "axgbe_common.h"
 #include "axgbe_phy.h"
 
-#define AXGBE_PHY_PORT_SPEED_100	BIT(0)
-#define AXGBE_PHY_PORT_SPEED_1000	BIT(1)
-#define AXGBE_PHY_PORT_SPEED_2500	BIT(2)
-#define AXGBE_PHY_PORT_SPEED_10000	BIT(3)
+#define AXGBE_PHY_PORT_SPEED_100	BIT(1)
+#define AXGBE_PHY_PORT_SPEED_1000	BIT(2)
+#define AXGBE_PHY_PORT_SPEED_2500	BIT(3)
+#define AXGBE_PHY_PORT_SPEED_10000	BIT(4)
 
 #define AXGBE_MUTEX_RELEASE		0x80000000
 
--
2.25.1
diff mbox series

Patch

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index a5431dd998..5310ac54f5 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1032,8 +1032,8 @@ 
 #define XP_PROP_0_PORT_ID_WIDTH			8
 #define XP_PROP_0_PORT_MODE_INDEX		8
 #define XP_PROP_0_PORT_MODE_WIDTH		4
-#define XP_PROP_0_PORT_SPEEDS_INDEX		23
-#define XP_PROP_0_PORT_SPEEDS_WIDTH		4
+#define XP_PROP_0_PORT_SPEEDS_INDEX		22
+#define XP_PROP_0_PORT_SPEEDS_WIDTH		5
 #define XP_PROP_1_MAX_RX_DMA_INDEX		24
 #define XP_PROP_1_MAX_RX_DMA_WIDTH		5
 #define XP_PROP_1_MAX_RX_QUEUES_INDEX		8
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 2aad8babd2..776144696a 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -7,10 +7,10 @@ 
 #include "axgbe_common.h"
 #include "axgbe_phy.h"
 
-#define AXGBE_PHY_PORT_SPEED_100	BIT(0)
-#define AXGBE_PHY_PORT_SPEED_1000	BIT(1)
-#define AXGBE_PHY_PORT_SPEED_2500	BIT(2)
-#define AXGBE_PHY_PORT_SPEED_10000	BIT(3)
+#define AXGBE_PHY_PORT_SPEED_100	BIT(1)
+#define AXGBE_PHY_PORT_SPEED_1000	BIT(2)
+#define AXGBE_PHY_PORT_SPEED_2500	BIT(3)
+#define AXGBE_PHY_PORT_SPEED_10000	BIT(4)
 
 #define AXGBE_MUTEX_RELEASE		0x80000000